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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? 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(note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
sh7751 group, sh7751r group hardware manual 32 users manual rev.4.00 2008.10 renesas 32-bit risc microcomputer superh? risc engine family/ sh7750 series
rev.4.00 oct. 10, 2008 page ii of xcviii rej09b0370-0400 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials
rev.4.00 oct. 10, 200 8 page iii of xcviii rej09b0370-0400 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/ mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manua l. if the descriptions under general precautions in the handli ng of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are gen erally in the high-impedance state. in operation with an unused pin in the open-circui t state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recogni tion of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from t he moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from t he moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to anothe r, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the sa me group but having different type numbers may differ because of the differences in inte rnal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products.
rev.4.00 oct. 10, 2008 page iv of xcviii rej09b0370-0400
rev.4.00 oct. 10, 2008 page v of xcviii rej09b0370-0400 preface the sh-4 (sh7751 group (sh7751, sh7751r)) microprocessor incorporates the 32-bit sh-4 cpu and is also equipped with peripheral functio ns necessary for configuring a user system. the sh7751 group is bu ilt in with a variety of peripheral functions such as cache memory, memory management unit (mmu), interrupt cont roller, floating-point unit (fpu), timers, two serial communication interfaces (sci, scif), real -time clock (rtc), user break controller (ubc), bus state controller (bsc) and pci controller (pcic). this series can be used in a wide range of multimedia equipment. the bus controller is compatible with rom, sram, dram, synchronous dram and pcmcia. target readers: this manual is designed for use by people who design application systems using the sh7751 or sh7751r. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. this hardware manual contains revisions related to the addition of r-mask functionality. be sure to check the text for the updated content. purpose: this manual provides the information of the hardware func tions and electrical characteristics of the sh7751 and sh7751r. the sh-4 software manual contains detailed info rmation of executable instructions. please read the software manual together with this manual. how to use the book: ? to understand general functions read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions refer to the separate sh-4 software manual. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are availa ble on our web site. please make sure that you have the latest version. (http://www.renesas.com/)
rev.4.00 oct. 10, 2008 page vi of xcviii rej09b0370-0400 ? user manuals for sh7751 and sh7751r name of document document no. sh7751 group, sh7751r group hardware manual this manual sh-4 software manual rej09b0318-0600 ? user manuals for development tools name of document document no. superh ? c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0047-0100h superh ? risc engine simulator/debugger user's manual REJ10B0210-0300 high-performance embedded workshop user's manual rej10j1554-0100
rev.4.00 oct. 10, 2008 page vii of xcviii rej09b0370-0400 main revisions for this edition item page revision (s ee manual for details) all ? notification of change in company name amended hitachi, ltd. renesas technology corp. 1.1 sh7751/sh7751r group features 1 description amended the sh7751/sh7751r group al so feature a bus state controller (bsc) that can be coupled to dram (page/edo) and synchronous dram . also, because of its built-in functions, such as pci bus controller, timers, and serial communications functions, required for multimedia and oa equipment, use of the sh7751/sh7751r group enable a dramatic reduction in system costs. table 1.1 sh7751/sh7751r group features 2 table amended item features lsi ? superscalar architecture: parallel execution of two instructions ? external buses (sh buses) ? separate 26-bit address and 32-bit data buses ? external bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency ? external bus (pci bus): ? 32-bit address/data multiplexing ? selection of internal clock or external pci-dedicated clock
rev.4.00 oct. 10, 2008 page viii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 1.1 sh7751/sh7751r group features table 1.1 sh7751/sh7751r group features 3 table amended item features fpu ? floating-point registers: 32 bits 16 2 banks (single-precision 32 bits 16 or double-precision 64 bits 8) 2 banks ? 3-d graphics instructions (single-precision only): ? 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles (latency) ? 4-dimensional vector inner product (fipr): 1 cycle (pitch), 4 cycles (latency) 8 table amended item features pci bus controller (pcic) ? pci bus controller (supports a subset of pci revision 2.1) * product lineup abbreviation voltage operating frequency model no. package sh7751 1.8 v 167 mhz hd6417751bp167 256-pin bga hd6417751f167 256-pin qfp sh7751r 1.5 v 240 mhz hd6417751rbp240 256-pin bga hd6417751rf240 256-pin qfp hd6417751rbg240 292-pin bga 200 mhz hd6417751rbp200 256-pin bga hd6417751rf200 256-pin qfp hd6417751rbg200 292-pin bga
rev.4.00 oct. 10, 2008 page ix of xcviii rej09b0370-0400 item page revision (s ee manual for details) 1.2 block diagram figure 1.1 block diagram of sh7751 series functions 9 figure amended lower 32-bit data 64-bit data (store) cpg intc sci (scif) rtc tmu external (sh) bus interface dmac 32-bit data 29-bit address 32-bit data address 32-bit data 32-bit data upper 32-bit data 32-bit address (instructions) 32-bit data (instructions) 32-bit address (data) peripheral address bus 26-bit sh bus address 32-bit pci address/ data 32-bit sh bus data peripheral data bus ubc 32-bit data (store) 32-bit data (load) cpu i cache o cache itlb utlb cache and tlb controller fpu 32-bit data pcic bsc address (pci)dmac sh-4 core
rev.4.00 oct. 10, 2008 page x of xcviii rej09b0370-0400 item page revision (s ee manual for details) 1.3 pin arrangement figure 1.4 pin arrangement (292-pin bga) 12 newly added a b c d e f g h 1234567891011121314151617 1920 18 j k l m n p r t u v w y bga292 (top view) vddq(io) vdd (internal) vss-pll1/2 vdd-pll1/2 vdd-cpg/rtc vss-cpg/rtc extal vdd-pll2 vdd-pll1 vss-cpg vdd-cpg vss-pll1 vss-pll2 vss-rtc vdd-rtc tck drak0 drak1 asebrk / brkack md5 dack0 audata1 md3/ ce2a audata0 xtal audata2 ca audsync md8/ rts2 md2/rxd2 md0/sck2 rxd audck md7/ cts2 txd mreset tclk sck md1/txd2 md4/ ce2b dack1 audata3 tdo dreq0 status1 tms cs0 cs4 cs5 we0 / reg dreq1 status0 md6/ iois16 back / bsreq breq / bsack trst reset rdy nmi tdi cs1 bs d5 d8 d11 d14 a17 cas1 /dqm1 cke rd/ wr we1 cs6 d1 ad6 d2 c/ be0 d4 d6 d7 d9 d10 d12 c/ be1 cas0 / dqm0 ckio rd / cass / frame cs3 a3 a6 a9 a14 cas3 /dqm3 d17 d23 d18 d21 d19 d16 d22 d27 a18 a24 a13 cas2 /dqm2 a12 d20 ad19 a0 ad23 ad24 ad22 ad17 cs2 ras ad13 par ad10 ad3 ad0 ad27 ad28 ad30 ad31 ad21 c/ be3 ad16 ad18 ad26 a23 a22 pciframe ad12 ad8 d3 ad7 ad5 d0 ad1 ad4 ad2 irl0 xtal2 extal2 ad11 ad14 ad9 ad25 ad15 devsel c/ be2 pcirst inta pcignt3 idsel vss serr we2 / iciord a25 ad29 pcignt2 pcireq1 / gntin pcignt1 / reqout irl2 irl1 irl3 pcilock d15 d13 irdy pcistop perr trdy pcireq2 /md9 pcireq3 /md10 pcireq4 pcignt4 a21 pciclk we3 / iciowr sleep d26 d25 d24 d31 d30 d29 a20 d28 a19 a15 a16 a7 a4 a1 ad20 a2 a5 a8 a10 a11 note: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. 1.4.1 pin functions (256-pin qfp) table 1.2 pin functions 14 table amended memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 38 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 39 ckio o clock output ckio ckio ckio ckio 20 table amended memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 197 ca * 2 i hardware standby 23 note amended note: supply power to all po wer pins. however, on the sh7751 in hardware standby mode, supply power to rtc at the minimum.
rev.4.00 oct. 10, 2008 page xi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 1.4.2 pin functions (256-pin bga) table 1.3 pin functions 25 table amended memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 38 m3 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 39 m1 ckio o clock output ckio ckio ckio ckio 34 note amended note: supply power to all po wer pins. however, on the sh7751 in hardware standby mode, supply power to rtc at the minimum. 1.4.3 pin functions (292-pin bga) 35 to 46 newly added 2.2.1 privileged mode and banks table 2.1 initial register values 49 table amended type registers initial value * sr md bit = 1, rb bit = 1, bl bit = 1, fd bit = 0, imask = 1111 (h'f), reserved bits = 0, others undefined control registers 2.6 processor states figure 2.6 processor state transitions 61 figure amended reset = 0 power-on reset state manual reset state from any state when reset = 0 reset = 1 and mreset = 0 reset state
rev.4.00 oct. 10, 2008 page xii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 3.3.7 address space identifier (asid) 77, 78 note amended notes: 2. when the sh7751 is operating in single virtual memory mode and user mode, the lsi may hang during hardware itlb miss handling (see section 3.5.4, hardware itlb miss handling), or an itlb multiple hit exception may occur, if an itlb miss occurs and the utlb contains address translation information including an itlb miss address with a different asid and unshared state (sh bit is 0). to avoid this, use workaround (1) or (2) below. (1) purge the utlb when switching the asid values (pteh and asid) of the current processing. (2) manage the behavior of program instruction addresses in user mode so that no instruction is executed in an address area (including overrun prefetch of an instruction) that is registered in the utlb with a different asid and unshared address translation information. note that accessing a different asid in single virtual memory mode can only be used to trigger an exception during data access. 3.5.5 avoiding synonym problems 87 note amended note: when multiple items of address translation information use the same physical memory to provide for future superh risc engine family ex pansion, ensure that the vpn [20:10] values are the same. also, do not use the same physical address for address translation information of different page sizes. 3.8 usage notes 100 newly added 4.1.1 features 101 description amended the sh7751 has an on-chip 8-kbyte instruction cache (ic) for instructions and 16-kbyte operand cache (oc) for data. half of the memory of the operand cache (8 kbytes) can also be used as on-chip ram. the features of these caches are summarized in table 4.1. the sh7751 has an on-chip 16-kbyte instruction cache (ic) for instructions and 32-kbyte o perand cache (oc) for data. half of the operand cache memory (16 kbytes) can also be used as on-chip ram. when the emode bit in the ccr register is cleared to 0 in the sh7751r, both the ic and oc are set to sh7751 compatible mode. when the emode bit in the ccr register is set to 1, the cache characteristics are as shown in table 4.2...
rev.4.00 oct. 10, 2008 page xiii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 4.2 register descriptions ? ora: oc ram enable bit * 3 104 description amended when the oc is enabled (oce = 1), the ora bit specifies whether the half of the oc ar e to be used as ram. when the oc is not enabled (oce = 0), the ora bit should be cleared to 0. 0: normal mode (the entire oc is used as a cache) 1: ram mode (half of the oc is used as a cache and the other half is used as ram) 4.3.1 configuration lru (sh7751r only) 108 description deleted in a 2-way set-associative system, up to two entry addresses can register the same data in cache. 4.3.10 notes on using oc ram mode (sh7751r only) when in cache enhanced mode 114 to 116 newly added 4.4.1 configuration lru (sh7751r only) 119 description deleted in a 2-way set-associative system, up to two entry addresses can register the same data in cache. 4.7 store queues 131, 132 description added note that power-down modes (stbcr2.mstp6 = 1) that stop sq functions cannot be used on the sh7751 when using the operand cache for write-back operations. * note: * cases where write-back operations are performed: ? when the operand cache is used in copy-back mode (determined by the ccr.cb and ccr.wt bits and, if address translation is performed, the wt bit in the page management information) ? when the memory allocation cache function is used to write to the oc address array, and an entry is generated when both the v and u bits are set to 1 4.7.6 sq usage notes (sh7751r only) 134 title amended
rev.4.00 oct. 10, 2008 page xiv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 5.3.2 exception handling vector addresses 139 description amended the reset vector address is fi xed at h'a000 0000. general exception and interrupt vector addresses are determined by adding the offset for the specif ic event to the vector base address, which is set by software in the vector base register (vbr). 5.4 exception types and priorities table 5.2 exceptions 142 table amended exception category execution mode exception priority level priority order vector address offset exception code pcic pciserr h'a00 pcierr ae0 interrupt completion type peripheral module interrupt (module/ source) h' 4 * 2 br) h'600 (v 5.5.3 exception requests and bl bit 146 description amended when the bl bit in sr is 0, general exceptions and interrupts are accepted. when the bl bit in sr is 1 and a general exception other than a user break is generated, the cp u's internal registers and the registers of the other modules ar e set to their post-reset state, and the cpu branches to the same address as in a reset (h'a000 0000). for the operation in the event of a user break, see section 20, user break controller (ubc). 5.6.1 resets (1) power-on reset 147 description amended in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. sr.imask = b'1111; (2) manual reset 148 description amended in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. sr.imask = b'1111;
rev.4.00 oct. 10, 2008 page xv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 5.6.1 resets (3) h-udi reset 149 description amended in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. sr.imask = b'1111; (4) instruction tlb multiple-hit exception 150 description amended in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. sr.imask = b'1111; (5) data tlb multiple- hit exception 151 description amended in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. sr.imask = b'1111; 5.6.2 general exceptions (11) general fpu disable exception 162 note amended note: * fpu instructions are instructions in which the first 4 bits of the instruction code are h'f (but excluding undefined instruction h 'fffd), and the lds, sts, lds.l, and sts.l instructions corresponding to fpul and fpscr.
rev.4.00 oct. 10, 2008 page xvi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 5.7 usage notes 170 description amended 2. if a general exception or interrupt occurs when sr.bl = 1 a. general exception when a general exception other than a user break occurs, manual reset occurs . the value in expevt at this time is h'0000 0020; the value of the spc and ssr registers is undefined. 3. spc when an exception occurs a. re-execution type general exception the pc value for the instruction in which the general exception occurred is set in spc, and the instruction is re-executed after returning from exception handling. if an exception occurs in a delay slot instruction, however, the pc value for the delay slot instruction is saved in spc regardless of whether or not the preceding delayed branch instruction condition is satisfied. b. completion type general exception or interrupt the pc value for the instruction following that in which the general exception occurred is set in spc. if an exception occurs in a branch instruction with delay slot, however, the pc value for the branch destination is saved in spc. 6.5 floating-point exceptions 182 description amended for information on possibilities (which differ depending on the individual instruction), see section 9, instruction descriptions, in the sh-4 software manual . 6.6.2 pair single- precision data transfer 184 description amended the powerful geometric operation instructions, fpu also supports high-speed data transfer instructions. when fpscr.sz = 1, fpu can perform data transfer by means of pair single-precision data transfer instructions. 6.7 usage notes 185 to 188 newly added 7.3 instruction set table 7.12 floating- point graphics acceleration instructions 207 table amended instruction operation instruction code privileged t bit frchg ~fpscr.fr fpscr.fr 1111101111111101 ? ? fschg ~fpscr.sz fpscr.sz 1111001111111101 ? ? 7.4 usage notes 207 to 209 newly added 8.4 usage notes 238 newly added
rev.4.00 oct. 10, 2008 page xvii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 9.1.1 types of power- down modes 239 description amended ? module standby function (tmu, rtc, sci/scif, dmac, sq, and ubc) 9.2.4 standby control register 2 (stbcr2) 245 description amended for details regarding the sh7 751, see section 4.7, store queues. 9.6.2 exit from standby mode 251 notes amended notes: 1. only when the rtc clock (32.768 khz) is operating (see section 19.2.2, irl interrupts), standby mode can be exited by means of irl3?irl0 (when the irl3?irl0 level is higher than the sr register imask mask level). 2. gpic can be used to cancel standby mode when the rtc clock (32.768 khz) is operating (when the gpic level is higher than the sr register imask mask level). 9.8.1 transition to hardware standby mode 253 description amended 3. on the sh7751, the rtc co ntinues to operate even when no power is supplied to power pins other than the rtc power supply pin. 9.8.2 exit from hardware standby mode 253, 254 description replaced hardware standby mode can only be cancelled by a power-on reset. driving the ca pin high when the reset pin is being driven low causes clock oscillation to start. at this point, maintain the reset pin at low level until clock oscillation stabilizes. the cpu will start pow er-on reset processing if the reset pin is driven high. hardware standby mode cannot be cancelled by an interrupt or a manual reset. 9.8.3 usage notes 254 description added 1. the ca pin level must be kept high when the rtc power supply is started (figure 9.15). 2. on the sh7751r, supply power to the v dd , v ddq , v dd-cpg , v dd ? pll1 , and v dd-pll2 power supply pins in addition to the rtc power supply pin in hardware standby mode.
rev.4.00 oct. 10, 2008 page xviii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 9.9.1 in reset figure 9.2 status output in manual reset 255 figure amended ckio (high) reset m reset * status normal reset normal 0?30 bcyc 0 bcyc must be asserted for t resw or longer 9.9.5 hardware standby mode timing figure 9.15 timing when vdd-rtc power is off on 264 figure amended ca v dd-rtc reset v dd , v ddq * min 0s note: * v dd , v dd-pll1/2 , v ddq , v dd-cpg power-on oscillation settling time 9.10 usage notes 264, 265 newly added 10.1.1 features 267 description amended ? three clocks the cpg can generate the cpu clock (ick) used by the cpu, fpu, caches, and tlb, the peripheral module clock (pck) used by the peripheral modules, and the bus clock (bck) used by the external bus interface. ? frequency change function pll (phase-locked loop) circuits and a frequency divider in the cpg enable the cpu clock, bus clock, and peripheral module clock frequencies to be changed . frequency changes are performed by software in accordance with the settings in the frequency control register (frqcr).
rev.4.00 oct. 10, 2008 page xix of xcviii rej09b0370-0400 item page revision (s ee manual for details) 10.2.1 block diagram of cpg pll circuit 1: 271 description added pll circuit 1: pll circuit 1 has a function for multiplying the clock frequency from the extal pin or crystal oscillation circuit by 6 (sh7751 and sh7751r) or 12 (sh7751r). starting and stopping is controlled by a frequency control register setting. control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. 10.3 clock operating modes table 10.3 (1) clock operating modes (sh7751) 273 table amended external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 off on on 6 3/2 3/2 h'0e1a 1 0 0 1 off on on 6 1 1 h'0e23 2 on on on 3 1 1/2 h'0e13 3 0 1 0 1 off on on 6 2 1 h'0e13 4 1 0 0 on on on 3 3/2 3/4 h'0e0a 5 1 off on on 6 3 3/2 h'0e0a 6 1 0 off off off 1 1/2 1/2 h'0808 10.3 clock operating modes table 10.4 frqcr settings and internal clock frequencies 274 table amended frequency division ratio of frequency divider 2 frqcr (lower 9 bits) cpu clock bus clock peripheral module clock h'000 h'002 h'004 1 1/8 h'008 h'00a h'00c 1/2 1/8 h'011 h'013 1/3 1/6 h'01a h'01c 1/4 1/8 h'023 1/6 h'02c 1 1/8 h'048 h'04a h'04c 1/2 1/8 h'05a h'05c 1/4 1/8 h'063 1/6 1/6 h'06c 1/2 1/8 1/8 h'091 h'093 1/3 1/3 1/6 h'0a3 1/3 1/6 1/6 h'0da h'0dc 1/4 1/4 h'0ec 1/4 1/8 1/8 h'123 1/6 1/6 1/6 h'16c 1/8 1/8 1/8 note: do not set values other than those shown in the table for the lower 9 bits of frqcr. 1/4 1/4 1/2 1/2 1/3 1/3 1/4 1/6 1/8 1/2 1/4 1/4
rev.4.00 oct. 10, 2008 page xx of xcviii rej09b0370-0400 item page revision (s ee manual for details) 10.10 notes on board design figure 10.5 points for attention when using pll oscillator circuit 288 figure amended vdd-pll1 cpb1 cpb2 cb rcb1 recommended values rcb1 = rcb2 = 10 cpb1 = cpb2 = 10 f rb = 10 cb = 10 f rcb2 rb power supply (vdd) power supply (vddq) vss-pll1 vdd-pll2 sh7751 sh7751r vss-pll2 vdd-cpg vss-cpg 10.11 usage notes 289 newly added 11.1.2 block diagram figure 11.1 block diagram of rtc 292 figure amended rtcclk 16.384 khz 32.768 khz 128 hz prescaler rtc crystal oscillation circuit 11.1.3 pin configuration table 11.1 rtc pins 293 table amended pin name abbreviation i/o function rtc oscillation circuit crystal pin extal2 connects crystal to rtc oscillation circuit rtc oscillation circuit crystal pin xtal2 connects crystal to rtc oscillation circuit clock input/clock output tclk i/o external clock input pin/input capture control input pin/rtc output pin (shared with tmu) dedicated rtc power supply v dd-rtc ? rtc oscillation circuit power supply pin * dedicated rtc gnd pin v ss-rtc ? rtc oscillation circuit gnd pin * output input 12.1.2 block diagram figure 12.1 block diagram of tmu 316 figure amended pck/4, 16, 64 * prescaler
rev.4.00 oct. 10, 2008 page xxi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 12.2.7 input capture register 2 (tcpr2) 326 title amended 12.4 interrupts 332 description amended there are six tmu interrupt sources, comprising underflow interrupts and the input captur e interrupt (when the input capture function is used). unde rflow interrupts are generated on channels 0 to 4, and input capture interrupts on channel 2 only. 12.5.4 external clock frequency 333 description amended ensure that the external clock frequency for any channel does not exceed pck/8. 13.1.4 register configuration table 13.2 bsc registers 340 table amended name abbrevia- tion r/w initial value bus control register 3 * 2 bcr3 r/w h'0001 13.1.6 pcmcia support table 13.5 pcmcia support interfaces 347 table and notes amended pin corresponding lsi pin 57 ? 58 output from port 59 rdy * 2 notes: 1. wp is not supported. 2. input an external wait request with correct polarity. 13.2.3 bus control register 3 (bcr3) (sh7751r only) 359 description amended bcr3 is initialized to h'0001 by a power-on reset, but is not initialized by a manual reset or in standby mode. 13.2.7 wait control register 3 (wcr3) 375 description amended of bits 4n+3 bits 4n+3 ? area n (4 or 1) read-strobe negate timing (anrdh) (setting only possible in the sh7751r): when reading, these bits specify the timing for the negation of read strobe. these bits should be cleared to 0 when a byte control sram setting is made. valid only for the sram interface. gate bit 4n + 3: anrdh read-strobe ne timing 0 read strobe negated after hold wait cycles specified by wcr3.anh bits (initial value) 1 read strobe negated according to data sampling timing note: n = 4 or 1
rev.4.00 oct. 10, 2008 page xxii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.2.8 memory control register (mcr) 377 description amended of bit 31 bit 31?ras down (rasd): sets ras down mode. when ras down mode is used, set be to 1. do not set ras down mode in slave mode areas 2 and 3 are both designated as synchronous dram interface. table amended of bit 31 bit 31: rasd description 0 charge mode (initial value) 1 ras down mode note: when synchronous dram is used in ras down mode, set bits dmaiw2?dmaiw0 to 000 and bits a3iw2?a3iw0 to 000. auto-pre note added, bits 29 to 27 note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. 13.2.8 memory control register (mcr) 378 description and note added, bits 21 to 19 bits 21 to 19?ras precharge period (tpc2?tpc0): when the dram interface is selected, these bits specify the minimum number of cycles until ras is asserted again after being negated. when the synchronous dram interface is selected, these bits specify the minimum number of cycles until the next bank active command after precharging. note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. 379 description amended of bits 15 to 13 after a write cycle, the next active command is not issued for a period set by tpc[2:0] and trwl[2:0] bits * . note: * for setting values and the period during which no command is issued, see 23.3.3, bus timing. 380 description amended of bits 12 to 10 bits 12 to 10?cas-before-ras refresh ras assertion period (tras2?tras0): when the dram interface is set, these bits set the ras assertion period in cas-before-ras refreshing. when the synchronous dram interface is set, the bank active command is not issued for a period set by tpc[2:0] and tras[2:0] bits after an auto-refresh command is issued. note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. 13.2.10 synchronous dram mode register (sdmr) 387 description amended lmode: cas latency bl: burst length wt: wrap type (0: sequential)
rev.4.00 oct. 10, 2008 page xxiii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.2 areas area 0: 400 description amended area 0: for area 0, external address bits 28 to 26 are 000. area 1: description amended area 1: for area 1, external address bits 28 to 26 are 001. area 2: 401 description amended area 2: for area 2, external address bits 28 to 26 are 010. area 3: description amended area 3: for area 3, external address bits 28 to 26 are 011. area 4: 402 description amended area 4: for area 4, physical address bits 28 to 26 are 100. area 5: 403 description amended area 5: for area 5, external address bits 28 to 26 are 101. area 6: 404 description amended area 6: for area 6, external address bits 28 to 26 are 110. 13.3.3 sram interface figure 13.12 sram interface wait state timing (read strobe negate timing setting) 412 figure amended ts1 ckio a25?a0 csn rd/ wr rd d31?d0 bs t1 tw tw tw tw t2 th1 th2 * ts1: setup wait wcr3.ans (0 to 1) tw: access wait wcr2.anw (0 to 15) th1, th2: hold wait wcr3.anh (0 to 3) note: * when anrdh is set to 1
rev.4.00 oct. 10, 2008 page xxiv of xcviii rej09b0370-0400 item page revision (see manual for details) 13.3.3 sram interface figure 13.12 sram interface wait state timing (read strobe negate timing setting) 412 figure amended ts1 ckio a25?a0 csn rd/ wr rd d31?d0 bs t1 tw tw tw tw t2 th1 th2 * ts1: setup wait wcr3.ans (0 to 1) tw: access wait wcr2.anw (0 to 15) th1, th2: hold wait wcr3.anh (0 to 3) note: * when anrdh is set to 1 13.3.4 dram interface refresh: ? self-refresh 425 description deleted after the self-refresh is cleared, the refresh controller immediately generates a refresh request. the ras precharge time immediately after the end of the self-refreshing can be set by bits trc2?trc0 in mcr. cas-before-ras refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. ? relationship between refresh requests and bus cycle requests figure 13.22 dram self-refresh cycle timing 426 figure amended d31 ? d0
rev.4.00 oct. 10, 2008 page xxv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.5 synchronous dram interface 427, 428 description deleted the control signals for connection of synchronous dram are ras , cass , rd/ wr , cs2 or cs3 , dqm0 to dqm3, and cke. commands for synchronous dram are specified by ras , cass , rd/ wr , and specific address signals. figure 13.23 example of 32-bit data width synchronous dram connection (area 3) 428 figure amended a11?a2 ckio cke cs3 ras cass rd/ wr d31?d16 dqm3 dqm2 sh7751/sh7751r burst read: figure 13.24 basic timing for synchronous dram burst read 431 figure amended ckio bank prechar g e-sel address csn rd/ wr ras cass d31?d0 (read) dqmn bs dackn (sa: io memory) cke td8 tpc c7 c8 refreshing: ? auto-refreshing figure 13.36 synchronous dram auto-refresh timing 448 figure amended d31 ? d0 ? self-refreshing figure 13.37 synchronous dram self-refresh timing 450 figure amended d31 ? d0 power-on sequence: figure 13.38 (1) synchronous dram mode write timing (pall) 452 figure amended d31?d0
rev.4.00 oct. 10, 2008 page xxvi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.5 synchronous dram interface figure 13.38 (2) synchronous dram mode write timing (mode register setting) 453 figure amended d31?d0 changing the burst length (sh7751r only): ? burst read figure 13.39 basic timing of a burst read from synchronous dram (burst length = 8) 455 figure amended cke dackn (sa: io memory) 13.3.7 pcmcia interface figure 13.45 basic timing for pcmcia memory card interface 465 figure amended d15?d0 (write) we1 (write) figure 13.46 wait timing for pcmcia memory card interface 466 figure amended d15?d0 (write) we1 (write) rd (read) d15?d0 (read) figure 13.48 basic timing for pcmcia i/o card interface 468 figure amended iciowr (write) d15?d0 (write)
rev.4.00 oct. 10, 2008 page xxvii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.7 pcmcia interface figure 13.49 wait timing for pcmcia i/o card interface 469 figure amended iciowr (write) d15?d0 (write) 13.3.8 mpx interface 471 description amended values output to address pins a25?a0 are not guaranteed. figure 13.51 example of 32-bit data width mpx connection 472 figure amended ckio csn bs rd / frame rd/ wr d31?d0 rdy sh7751/sh7751r
rev.4.00 oct. 10, 2008 page xxviii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.8 mpx interface figure 13.64 mpx interface timing 5 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 32 bytes) figure 13.65 mpx interface timing 6(burst read cycle, anw = 0, external wait control, bus width: 32 bits,transfer data size: 32 bytes) figure 13.66 mpx interface timing 7(burst write cycle, anw = 0, no external wait, bus width: 32 bits,transfer data size: 32 bytes) figure 13.67 mpx interface timing 8(burst write cycle, anw = 1, external wait control, bus width: 32 bits,transfer data size: 32 bytes) ? figures deleted 13.3.9 byte control sram interface figure 13.64 example of 32-bit data width byte control sram 485 figure amended, note deleted a17?a2 csn rd rd/wr sh7751/sh7751r d15?d0 we1 we0 d31?d16 we3 we2
rev.4.00 oct. 10, 2008 page xxix of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.11 bus arbitration 490, 491 description amended there are two bus arbitrati on modes: master mode, and slave mode. in master mode the bus is held on a constant basis, and is released to another device in response to a bus request. in slave mode the bus is not held on a constant basis; a bus request is issued each time an external bus cycle occurs, and the bus is released again at the end of the access. master mode and slave mode can be specified by the external mode pins. see appendix c, mode pin settings, for the external mode pin settings. in master mode and slave mode, the bus goes to the high-imp edance state when not being held. instead of a slave mode chip. in the following description, an external device that issues bus requests is also referred to as a slave. to prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated before the bus is released. when mastership of the bus is rece ived, also, bus control signals begin driving the bus from the neg ated state. since signals are driven to the same value by t he master and slave exchanging the bus, output buffer collisions can be avoided.
rev.4.00 oct. 10, 2008 page xxx of xcviii rej09b0370-0400 item page revision (s ee manual for details) 13.3.15 notes on usage 495, 496 description amended refresh: auto refresh operations stop when a transition is made to standby mode, hardware standby mode, or deep-sleep mode. if the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode, hard ware standby mode, or deep- sleep mode. synchronous dram mode register settings (sh7751 only): the following conditions must be satisfied when setting the synchronous dram mode register. ? the dmac must not be activated until synchronous dram mode register setting is completed. * 1 ? register setting for the on-chip peripheral modules * 2 must not be performed until synchronous dram mode register setting is completed. * 3 notes: 1. if a conflict occurs between synchronous dram mode register setting and memory access using the dmac, neither operation can be guaranteed. 2. this applies to the following on-chip peripheral modules: cpg, rtc, intc, tmu, sci, scif, and h-udi. 3. if synchronous dram mode register setting is performed immediately following write access to the on-chip peripheral modules * 2 , the values written to the on-chip peripheral modules cannot be guaranteed. note that following power-on, synchronous dram mode register settings should be performed before accessing synchronous dram. after making mode register settings, do not change them.
rev.4.00 oct. 10, 2008 page xxxi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 14.1.1 features 498, 499 description amended ? on-chip peripheral modules request note: * dtr.count [7:4] (dtr [ 23:20]): sets the port as not used. in ddt mode on the sh7751, an external device and the dmac perform handshaking using the dbreq , bavl , tr , tdack , id[1:0], and d[31:0] signals during data transfer. on the sh7751r, the dbreq , bavl , tr , tdack , id[2:0], and d[31:0] signals are used for handshaking during data transfer between an external device and the dmac. 14.2.4 dma channel control registers 0-3 (chcr0-chcr3) 508 description added bit 28?source address wait control select (stc): specifies cs5 or cs6 space wait control for pcmcia interface area access. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. 14.3.4 types of dma transfer (a) normal dma mode table 14.8 external request transfer sources and destinations in normal dma mode 533 table title amended (b) ddt mode table 14.9 external request transfer sources and destinations in ddt mode 534 table amended transfer direction (settable memory interface) transfer source transfer destination address mode usable dmac channels 1 synchronous dram external device with dack single 0, 1, 2, 3 2 external device with dack synchronous dram single 0, 1, 2, 3 3 synchronous dram sram-type, mpx, pcmcia * dual 1, 2, 3 4 sram-type, mpx, pcmcia * synchronous dram dual 1, 2, 3 5 sram-type, dram, pcmcia, mpx sram-type, mpx, pcmcia * dual 1, 2, 3 6 sram-type, mpx, pcmcia * sram-type, dram, pcmcia, mpx dual 1, 2, 3
rev.4.00 oct. 10, 2008 page xxxii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 14.5.2 pins in ddt mode figure 14.24 shows the system configuration in ddt mode. 555 figure amended synchronous dram dbreq / dreq0 bavl /drak0 tr / dreq1 tdack /dack0 id1, id0/drak1, dack1 ckio d31?d0 = dtr external device sh7751/sh7751r a25?a0, ras, cas, we, dqmn, cke ? tr : description amended assertion of tr has the following different meanings. ? in normal data transfer mode (channel 0, except channel 0), tr is asserted, and at the same time the dtr format is output, two cycles after bavl is asserted. data transfer request format (dtr) figure 14.25 data transfer request format 556 figure amended sz id md (reserved) 31 28 29 27 25 23 0 (reserved) 26 24 description amended, bits 31 to 29 ? 000: dtr format selected data transfer request format (dtr) 557 notes amended note: 4. when specifying data transfer requests using a handshake protocol for channel 0, set dtr.id = 00, dtr.md = 00, and dtr.sz 101, 110 for the dtr format. 14.5.4 notes on use of ddt module 580 description amended 2. normal data transfer mode ( channel 1 to channel 3) 7. dtr format 581 note added note: do not use setting values other than the above. 14.6.3 register configuration (sh7751r) table 14.14 register configuration 587 notes amended notes: * bit 1 of chcr0?chcr7 and bits 2 and 1 of dmaor can only be written with 0 after being read as 1, to clear the flags.
rev.4.00 oct. 10, 2008 page xxxiii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 14.7.4 dma channel control registers 0- 7(chcr0-chcr7) bit 17-acknowledge mode (am) 591 description amended in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr7. (ddt mode: tdack) 14.8.3 transfer channel notification in ddt mode 596 description amended when the dmac is set up for eight-channel external request acceptance in ddt mode (dmaor.dbl = 1), the id [1:0] bits and the simultaneous (on the timing of tdack assertion) assertion of id2 from the bavl (data bus available) pin are used to notify the external device of the dmac channel that is to be used (see table 14.16, notification of transfer channel in eight-channel ddt mode). table 14.17 function of bavl table amended function of bav b a v l tdack = hi g h bus available tdack = low notification of channel number ( id2 ) 15.1 overview 603 description amended the sci supports a smart card interface. this is a serial communication function supporting a subset of the iso/iec 7816-3 (identification cards) st andard. for details, see section 17, smart card interface. 15.3.3 multiprocessor communication function 644 description amended the transmitting station first s ends the id of the receiving station with which it wants to perform serial communication as data with the multiprocessor bit set to 1. it then sends transmit data as data with the multiprocessor bit cleared to 0.
rev.4.00 oct. 10, 2008 page xxxiv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 15.3.3 multiprocessor communication function 649, 650 description amended multiprocessor serial data reception 1. method for determining whethe r an interrupt generated during receive operation is a multiprocessor interrupt when an interrupt such as rxi occurs during receive operation using the on-chip sci multiprocessor communication function, check t he state of the mpie bit in the scscr1 register as part of the interrupt handling routine. a. if the mpie bit in the scscr1 register is set to 1 ignore the received data. data with the multiprocessor bit (mpb) set to 0 and intended for another station was received, and the rdrf bit in the scscr1 register was set to 1. therefore, clear the rdrf bit in the scscr1 register to 0. b. if the mpie bit in the scscr1 register is cleared to 0 a multiprocessor interrupt indi cating that data (id) with the multiprocessor bit (mpb) set to 1 was received, or a receive data full interrupt (rxi) occurred when data with the multiprocessor bit (mpb) set to 0 and intended for this station was received. 2. method for determining whether received data is id or data do not use the mpb bit in the scssr1 register for software processing. when using software processing to determine whether received data is id (mpb = 1) or data (mpb = 0), use a procedure such as saving a user-defined flag in memory to indicate receive start. figure 15.15 shows a flowchart of a sample software workaround. figure 15.15 sample flowchart of multiprocessor serial reception with interrupt generation 651 newly added
rev.4.00 oct. 10, 2008 page xxxv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 15.3.3 multiprocessor communication function figure 15.16 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit) 652 figure replaced 15.5 usage notes handling of tend flag and te bit 667, 668 description added to send a break signal during serial transmission, clear the spb0dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardle ss of its current state, and the txd pin becomes an output port outputting the value 0. handling of tend flag and te bit: the tend flag is set to 1 when the stop bit of the final data segment is transmitted. if the te bit is cleared immediately after confirming that the tend flag was set, transmission may not complete properly because stop bit transmission processing is still underway. therefore, wait at least 0.5 serial clock cycl es (1.5 cycles if two stop bits are used) after confirming that the tend flag was set before clearing the te bit. 17.1 overview 719 description amended the serial communication interfac e (sci) supports a subset of the iso/iec 7816-3 (identificat ion cards) standard as an extended function. 17.2.3 serial control register (scscr1) 724 description added bits 3 and 2?reserved: 17.2.4 serial status register (scssr1) 726 description added bits 1 and 0?reserved: 19.1.2 block diagram figure 19.1 block diagram of intc 770 figure amended interrupt request imask sr cpu
rev.4.00 oct. 10, 2008 page xxxvi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 19.1.3 pin configuration table 19.1 intc pins 771 table amended pin name function nonmaskable interrupt input pin input of nonmaskable interrupt request si g nal interrupt input pins input of interrupt request si g nals (maskable by imask in sr) 19.2.1 nmi interrupt 772 description amended nmi interrupt exception handling does not affect the interrupt mask level bits (imask) in the status register (sr). 19.2.2 irl interrupts 774 description amended the interrupt mask bits (imask) in the status register (sr) are not affected by irl interrupt handling. 19.2.3 on-chip peripheral module interrupts 775 description amended the interrupt mask bits (imask) in the status register (sr) are not affected by on-chip peripheral module interrupt handling. 19.2.4 interrupt exception handling and priority table 19.4 interrupt exception handling sources and priority order 777 table amended interrupt source intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority pcic pciserr h'a00 15?0 (0) intpri00 (3?0) ? pcierr h'ae0 15?0 (0) high pcipwdwn h'ac0 pcipwon h'aa0 pcidma0 h'a80 pcidma1 h'a60 pcidma2 h'a40 pcidma3 h'a20 intpri00 (7?4) low high 19.4.1 interrupt operation sequence 787 description amended 3. the priority level of the in terrupt selected by the interrupt controller is compared with th e interrupt mask bits (imask) in the status register (sr) of the cpu. if the request priority level is higher that the leve l in bits imask, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. notes: 1. the interrupt mask bits (imask) in the status register (sr) are not changed by acceptance of an interrupt in this lsi.
rev.4.00 oct. 10, 2008 page xxxvii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 19.4.1 interrupt operation sequence figure 19.3 interrupt operation flowchart 788 figure amended no no yes yes no yes no yes no yes save sr to ssr; save pc to spc set interrupt source in intevt set bl, md, rb bits in sr to 1 branch to exception handler level 14 interrupt? level 1 interrupt? imask = level 13 or lower? imask = level 0? yes imask * = level 14 or lower? note: * imask: interrupt mask bits in status re g ister (sr) 19.6 usage notes 791 to 793 newly added 20.2.1 access to ubc registers 798 description amended 2. execute instructions requirin g 5 states for execution after the memory store instruction that updated the register. as the cpu executes two instructions in parallel and a minimum of 0.5 state is r equired for execution of one instruction, 11 instructions must be inserted. the updated value will be valid from the 6th state onward. 20.3.1 explanation of terms relating to accesses 808 description amended in this lsi, all operand accesses are treated as either read accesses or write accesses. the following instructions require special attention: this lsi handles all operand accesses as having a data size. the data size can be byte, word, longword, or quadword. the operand data size for the pref, ocbp, ocbwb, movca.l, and ocbi instructions is treated as longword. 21.1.1 features 823 description amended the high-performance user debug interface (h-udi) is a serial input/output interface supporting a subset of the jtag, ieee 1149.1, ieee standard test a ccess port and boundary-scan architecture.
rev.4.00 oct. 10, 2008 page xxxviii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 21.1.3 pin configuration 826 note amended 3. fixed to the ground or connected to the same signal line as reset , or to a signal line that behaves in the same way. however, there is a problem when this pin is fixed to the ground. trst is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. the size of this current is determined by the rating of the pull-up resistor. although this current has no effect on the chip's operation, unnecessary current will be dissipated. 21.2.5 boundary scan register (sdbsr) table 21.3 structure of boundary scan register 829 to 842 description amended and table replaced the boundary scan register (sdbsr) is a shift register that is placed on the pads to control the chip's i/o pins. this register can perform a boundary scan test equivalent to the jtag (ieee std 1149.1) standard using ext est, sample, and preload commands. 21.3.4 boundary scan (extest, sample/preload, bypass) 845 description amended and 6. moved to 21.4 in this lsi, setting a command from the h-udi in sdir can place the h-udi pins in the boundary scan mode. however, the following limitations apply. 21.4 usage notes 5. moved from 21.3.4 6. 22.1.1 features 847 description and notes amended ? supports a subset of pci version 2.1. note: * mpx is only supported by the sh7751r and is not supported by the sh7751. 22.1.3 pin configuration table 22.1 pin configuration 850 note amended 3. pull down this pin to low level when idsel is not in use. if a configuration access to an external pci device occurs while idsel is high level, the pcic itself may respond. 22.2.1 pci configuration register 0 (pciconf0) 857 note added note: * the vendor id h'1054 spec ifies hitachi, ltd., but the sh7751 and sh7751r are now products of renesas technology corp. for information on these products, contact renesas technology corp.
rev.4.00 oct. 10, 2008 page xxxix of xcviii rej09b0370-0400 item page revision (s ee manual for details) 22.2.3 pci configuration register 2 (pciconf2) 864 description amended bits 23 to 16?sub class codes (class15 to 8): shows the subclass code. for details, please see appendix d, pin functions of the pci local bus specifications, revision 2.1. bits 15 to 8?register level programming interface (class7 to 0): shows the register level programming interface. for details, please see appendix d, pi n functions of the pci local bus specifications, revision 2.1. 22.2.17 pci control register (pcicr) 886 description added of bit 3 bit 3: serr description 0 serr pin at hi-z (driven to high by pull-up resistor) (initial value) 1 ssert serr (low output) a 887 description deleted of bit 1 22.2.24 pci arbiter interrupt register (pciaint) 900 description amended the pciaint register is initia lized to h'00000000 at a power-on reset or software reset. 901 description added of bit 13 bit 13?master broken interrupt (mst_brkn): detects when the master granted with bus privileges does not start a transaction ( frame not asserted) within 16 clocks. for the sh7751, see 22.12, usage notes. description added of bit 12 bit 12?target bus timeout inte rrupt (tgt_busto): neither trdy nor stop are not returned within 16 clocks in the case of the first data transfer, or withi n 8 clocks in the case of second and subsequent data transfers. for the sh7751, see 22.12, usage notes. description added of bit 11 bit 11?master bus timeout inte rrupt (mst_busto): indicates the detection that irdy was not asserted within 8 clock cycles in a transaction initiated by a device including pcic. description amended of bit 1 bit 1?write data parity error interrupt (dperr_wt): indicates the detection of the assertion of perr in a data write operation when a device other than the pcic is operating as the bus master.
rev.4.00 oct. 10, 2008 page xl of xcviii rej09b0370-0400 item page revision (s ee manual for details) 22.2.24 pci arbiter interrupt register (pciaint) 901 description amended of bit 0 bit 0?read data pari ty error interrupt (d perr_rd): indicates the detection of the assertion of perr in a data read operation when a device other than the pcic is operating as the bus master. 22.2.25 pci arbiter interrupt mask register (pciaintm) 902 description amended the pci arbiter interrupt mask register (pciaintm) sets interrupt masks for the individual interrupts that occur due to errors generated during pci transfers performed by other pci devices when the pcic is o perating as the host with the arbitration function. it is a 32-bi t register that is readable and writable from both the peripheral bus and the pci bus. each bit is set to 0 to disable the respective interrupt, or 1 to enable that interrupt. 22.2.29 pci dma transfer local bus start address register [3:0] (pcidla [3:0]) 907, 908 description amended the transfer address of a byte boundary or character boundary can be set, but the 2 least signific ant bits of the register are ignored, and the data of the lo ngword boundary is transferred. note that the local bus starting addr ess set in this register is the external address of the sh bus. bits 28 to 0?dma transfer local bus starting address (pdla28 to 0): these bits set t he starting address of the local bus (external address of sh bus) for dma transfer. bits 28 to 26 indicate the local bus area. 22.2.30 pci dma transfer counter register [3:0] (pcidtc [3:0]) 909 description amended bits 25 to 0?dma transfer byte count (ptc25 to 0): specify the number of bytes in dma transfer. the maximum number of transfer bits are 64 mb (when set to h'00000000). 22.2.31 pcidma control register [3:0](pcidcr[3:0]) 910 description amended when setting the dmastop bit, do not write 1 to the dmastart bit. also, write the same setting at the start of transfer to the dmaim, dmais, lahold, iosel and dir bits. 22.2.36 pci power management interrupt mask register (pcipintm) 920 description amended bit 1?power state d3 (dperr_wt): transition request to power-down mode interrupt mask for this lsi. bit 0?power state d0 (dperr_rd): restore from power- down mode interrupt mask for this lsi.
rev.4.00 oct. 10, 2008 page xli of xcviii rej09b0370-0400 item page revision (s ee manual for details) 22.2.38 pcic-bsc registers 921 description added the pcic-bsc performs the same type of control as the slave function of the bus controller ( bsc). however, the pcic-bsc returns bus rights to the bsc after each data transfer of up to 32 bytes of data. there are six registers in the pcic-bsc: pcibcr1 (equivalent to the bcr1 of the bsc), pcibcr2 (equivalent to the bcr2 of the bsc), pcibcr3 (equivalent to the bcr3 of the bsc) * 1 , pciwcr1 (equivalent to the wcr1 of the bsc), pciwcr2 (equivalent to the wcr2 of the bsc), pciwcr3 (equivalent to the wcr3 of the bsc), and pcimcr (equivalent to the mcr of the bsc). 922 description amended ? the external memory capable of data transfers to the pci bus is sram, dram, synchronous dram, and mpx * 2 . ? also, the memory data width is 32-bit or 16-bit only (only 32- bit in the case of synchronous dram). ? do not specify other external memory types (burst rom, mpx, byte control sram or pcmcia) as the external memory for data transfers with the pci bus. ? also, do not implement any settings that are not allowed in slave mode in the pcic-bsc registers. this is because bit 30: master/slave flag (master) of the pcibcr1 is fixed low, regardless of the value of the external master/slave setting pin (md7) at a power-on reset, and the pcic-bsc therefore is set in slave mode. 22.2.41 pio data register (pcipdr) 928 description amended always write to this register before accessing the pci configuration space. always read/ write to this register after setting the value in the pio address register (pcipar). 22.3.3 pcic initialization 930 description amended also, as the bsc has bcr1.breqen bits that enable an external request and a bus request from the pcic to be accepted, bcr1.breqen should be set to 1 when the pcic is used.
rev.4.00 oct. 10, 2008 page xlii of xcviii rej09b0370-0400 item page revision (see manual for details) 22.3.7 pio transfers figure 22.2 pio memory space access 936 figure amended 31 24 23 0 lock identifier pcimbr figure 22.3 pio i/o space access 937 figure amended 31 18 17 0 lock identifier pciiobr 22.3.8 target transfers 939 description amended to make it possible to access two or more areas from the pci bus, set the address spaces so that multiple areas are covered. i/o-read and i/o-write commands: 940 note amended note: * in version 2.1 of the pci specifications the i/o space for pci devices is defined as being no more than 256 bytes. as a result, when the sh7751 is used in a pci non-host device, for example on an add-in card, it may be identified as an unusable device during device configuration because it requires an i/o space larger than 256 bytes. configuration-read and configuration-write commands: note amended note: * version 2.1 of the pci specifications specifies that any combination of byte-enable signal ( be[3:0] ) values must be allowed when accepting a configuration access. as a result, when byte or word access is specified by the combination of be[3:0] , the remaining portion of the data in the longword unit is also overwritten by the write operation. 22.3.9 dma transfers dma arbitration 945 description amended the arbitration circuit monitors the data transfer requests (data write requests to the fifo when the fifo is empty and read requests from the fifo when it is full) 4 dma transfer channels to control the data transfers. for each transfer request, a transfer of up to 32 bytes of data is performed.
rev.4.00 oct. 10, 2008 page xliii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 22.3.11 pci bus basic interface 947 description amended the pci interface of the mcu supp orts a subset of version 2.1 of the pci specifications and enables connection to a device with a pci bus interface. target read/write cycle timing: 952 description amended and note added the following restrictions apply to the sh7751. with the sh7751r, in the following case the values of data are discarded for a target read that is executed immediately after a target write because the data read in an earlier read operation that was carried out by a different pci device are discarded. [restrictions] in a system in which access is made to the same address * 1 in local memory by two or more pci devices, the data cannot be guaranteed when a target read is performed immediately after a target write. notes: 1. address matching ad [31:2] in the address phase. 2. the address that does not correspond to the address ad[31:2] on a longword boundary. 22.4.4 endian control in target transfers (memory read/memory write) 963 description amended as shown in table 22.12, the by te data boundary mode is used, for all transfers. 22.6.1 interrupts from pcic to cpu power management interrupt (transition request to normal status) (pcipwon): 970 description amended power management interrupt (transition request to normal status) (pcipwon): the power state d0 (pwrst_d0) bit of the pci power management interrupt register (pcipint) is set. the power state d0 interrupt mask can be set using the power state d0 (pwrst_d0) bit of the pci power management interrupt mask register (pcipintm). power management interrupt (transition request to power-down mode) (pcipwdwn): description amended power management interrupt (transition request to power- down mode) (pcipwdwn): the power state d3 (pwrst_d3) bit of the pci power management interrupt register (pcipint) is set. the power state d3 interrupt mask can be set using the power state d3 (pwrst_d3) bit of the pci power management interrupt mask register (pcipintm).
rev.4.00 oct. 10, 2008 page xliv of xcviii rej09b0370-0400 item page revision (s ee manual for details) 22.9.1 power management overview 973 description amended of the power management interr upts, the power state d3 (pwrst _ d3) interrupt detects a trans ition from the power state d0 to d3, while power state d0 (pwrst_d0) interrupt detects a transition from the power state d3 to d0. 22.9.2 stopping the clock table 22.14 method of stopping clock per operating mode 974, 975 table amended pcic master slave lsi (other than pcic) pciclk operation ckio operation pciclk operation bck normal operation normal operation normal operation normal operation pck normal operation normal operation normal operation normal operation normal operation/ sleep pciclk not used normal operation not used normal operation bck stopped stopped stopped stopped pck normal operation normal operation normal operation normal operation deep sleep pciclk not used normal operation not used normal operation bck stopped stopped stopped stopped pck stopped stopped stopped stopped clock operatin g status standby pciclk not used stopped not used stopped transition sleep command bck stopped from lsi bck and pciclk stopped from lsi pci command + interrupt (pcic lsi) + bck restarted from lsi transition/ recovery deep sleep recovery 1 not used pme interrupt (connected to irl) + bck restarted from lsi pme interrupt (connected to irl) + bck and pciclk restarted from lsi pci command + interrupt (pcic lsi) + bck restarted from lsi recovery 2 nmi, irl, and reset on-chip peripheral interrupt nmi, irl, reset + bck restarted from lsi nmi, irl, reset + bck and pciclk restarted from lsi nmi, irl, reset + bck restarted from lsi + wait for pci command (recovery) transition/ recovery standby transition standby command standby command pciclk stopped from lsi + standby command pci command + interrupt (pcic lsi) + standby command recovery 1 not used pme interrupt (connected to irl) pme interrupt (connected to irl) + pciclk restarted from lsi power-on reset recovery 2 nmi, irl, and reset on-chip peripheral interrupt nmi, irl, and reset nmi, irl, reset + pciclk restarted from lsi nmi, irl, reset + wait for pci command (recovery) 22.12 usage notes 977 to 980 newly added
rev.4.00 oct. 10, 2008 page xlv of xcviii rej09b0370-0400 item page revision (s ee manual for details) section 23 electrical characteristics 981 to 1080 description of lead-free products added hd6417751rbp240(v) hd6417751rf240(v) hd6417751rbp200(v) hd6417751rf200(v) hd6417751bp167(v) hd6417751bp167i(v) hd6417751f167(v) hd6417751f167i(v) 23.1 absolute maximum ratings table 23.1 absolute maximum ratings 981 table and notes amended item symbol value unit operatin g temperature t opr ?20 to 75 c notes: * hd6417751r only. 23.2 dc characteristics table 23.2 dc characteristics (hd6417751rbp240 (v), hd6417751rbg240 (v)) 982 title and table amended item symbol min typ max unit test conditions current dissipation normal operation i ddq ? 100 145 sleep mode ? 60 115 ma bck = 120 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 table 23.3 dc characteristics (hd6417751rf240 (v)) 984, 985 table amended 70 item symbol min typ max unit test conditions current dissipation normal operation i ddq ? 100 sleep mode ? 42 80 ma bck = 84 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 ? pin capacitance all pins c l ? 10 pf table 23.4 dc characteristics (hd6417751rbp200 (v), hd6417751rbg200 (v)) 986 title and table amended item symbol min typ max unit test conditions current dissipation normal operation i ddq ? 85 120 sleep mode ? 50 95 ma bck = 100 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1
rev.4.00 oct. 10, 2008 page xlvi of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.2 dc characteristics table 23.5 dc characteristics (hd6417751rf200 (v)) 988, 989 table amended item symbol min typ max unit test conditions current dissipation normal operation i ddq ? 70 100 sleep mode ? 42 80 ma bck = 84 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 pin capacitance all pins c l ? ? 10 pf table 23.7 dc characteristics (hd6417751bp167i (v)) table 23.9 dc characteristics (hd6417751f167i (v)) table 23.10 dc characteristics (hd6417751vf133) ? tables deleted 23.3 ac characteristics table 23.9 clock timing (hd6417751rbp240 (v), hd6417751rbg240 (v)) 994 title and table amended item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 240 mhz external bus 1 ? 120 operating frequency peripheral modules 1 ? 60 table 23.11 clock timing (hd6417751rbp200 (v), hd6417751rbg200 (v)) 995 title amended table 23.13 clock timing (hd6417751bp167 (v), hd6417751f167 (v)) title amended table 23.17 clock timing (hd6417751vf133) ? table deleted
rev.4.00 oct. 10, 2008 page xlvii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.1 clock and control signal timing table 23.14 clock and control signal timing (hd6417751rbp240 (v), hd6417751rbg240 (v)) 996 title and description amended v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf table 23.15 clock and control signal timing (hd6417751rf240 (v)) 997 table amended v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure pll1/pll2 operating 25 84 mhz ckio clock output pll1/pll2 not operating f op 134mhz table 23.16 clock and control signal timing (hd6417751rbp200 (v), hd6417751rbg200 (v)) 998 title and description amended v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf table 23.17 clock and control signal timing (hd6417751rf200 (v)) 999 description amended v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf table 23.18 clock and control signal timing (hd6417751bp167 (v), hd6417751f167 (v) ) 1000 title and description amended v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf table 23.23 clock and control signal timing (hd6417751vf133) ? table deleted 23.3.2 control signal timing table 23.19 control signal timing 1006 table amended * * * * item symbol min max min max min max min max unit figure bus tri-state delay time to standby mode t boff2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (2) bus buffer on time t bon1 ? 12 ? 12 ? 12 ? 12 ns 23.11 (2) bus buffer on time from standby t bon2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 t std1 ? 6 ? 6 ? 6 ? 6 ns 23.12 (1) status 0/1 delay time to t std2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (1) (2) t std3 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (2) hd6417751r bp240 (v) hd6417751r bg240 (v) hd6417751r bp200 (v) hd6417751r bg200 (v) hd6417751r f240 (v) hd6417751r f200 (v)
rev.4.00 oct. 10, 2008 page xlviii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.2 control signal timing table 23.20 control signal timing 1007 table amended hd6417751bp167 (v) hd6417751f167 (v) * item symbol min max unit figure breq setup time t breqs 3.5 ? ns 23.11 breq hold time t breqh 1.5 ? ns 23.11 back delay time t backd ? 8 ns 23.11 bus tri-state delay time t boff1 ? 12 ns 23.11 bus tri-state delay time to standby mode t boff2 ? 2 t cyc 23.12 (2) bus buffer on time t bon1 ? 12 ns 23.11 bus buffer on time from standby t bon2 ? 2 t cyc 23.12 (2) status 0/1 delay time t std1 ? 6 ns 23.12 (1) t std2 ? 2 t cyc 23.12 (1) (2) t std3 ? 2 t cyc 23.12 (2) note: * v ddq = 3.0 to 3.6 v, v dd = 1.8 v , t a = ?20 to 75 c, c l = 30 pf, pll2 on figure 23.12 (1) pin drive timing for rest or sleep mode 1008 title amended and figure replaced figure 23.12 (2) pin drive timing for software standby mode 1009 title amended and figure replaced 23.3.3 bus timing table 23.21 bus timing (1) 1010, 1011 table and note amended hd6417751r bp240 (v) hd6417751r bg240 (v) hd6417751r bp200 (v) hd6417751r bg200 (v) hd6417751r f240 (v) hd6417751r f200 (v) * * * * item symbol min max min max min max min max unit notes note: * v ddq = 3.0 to 3.6 v, v dd = 1.5 v , t a = ?20 to +75 c, c l = 30 pf, pll2 on table 23.22 bus timing (2) 1012, 1013 table and note amended hd6417751vf133 deleted hd6417751bp167 (v) hd6417751f167 (v) * item symbol min max unit notes note: * v ddq = 3.0 to 3.6 v, v dd = 1.8 v , t a = ?20 to +75 c, c l = 30 pf, pll2 on
rev.4.00 oct. 10, 2008 page xlix of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.3 bus timing figure 23.23 synchronous dram normal read bus cycle: act + read commands, burst (rasd = 1, rcd [1:0] = 01, cas latency = 3) 1024 title amended figure 23.24 synchronous dram normal read bus cycle: pre + act + read commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, cas latency = 3) 1025 title amended figure 23.25 synchronous dram normal read bus cycle: read command, burst (rasd = 1, cas latency = 3) 1026 title amended figure 23.28 synchronous dram normal write bus cycle: act + write commands, burst (rasd=1, rcd [1:0] = 01, trwl [2:0] = 010) 1029 title amended figure 23.29 synchronous dram normal write bus cycle: pre + act + write commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, trwl [2:0] = 010) 1030 title amended figure 23.30 synchronous dram normal write bus cycle: write command, burst (rasd = 1, trwl [2:0] = 010) 1031 title amended
rev.4.00 oct. 10, 2008 page l of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.3 bus timing figure 23.34 (b) synchronous dram bus cycle: mode register setting (set) 1036 figure amended trp1 ckio bank precharge-sel address csn rd/ wr ras cass dqmn bs dackn cke t ad t rwd t dqmd t dacd t wdd t casd t rasd d31?d0 (write) figure 23.36 dram bus cycle (edo mode, rcd [1:0]=00, anw[2:0]=000, trc[2:0]=001) 1038 title amended
rev.4.00 oct. 10, 2008 page li of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.3 bus timing figure 23.50 pcmcia memory bus cycle (1) ted [2:0] = 000, teh [2:0] = 000, no wait (2) ted [2:0] = 001, teh [2:0] = 001, one internal wait + one external wait 1052 figure amended tpcm0 tpcm1 tpcm2 tpcm1w tpcm1w tpcm2w ckio cexx reg (we0) rd/wr rd d15?d0 (read) t ad t ad t rwd t csd t csd t rwd t rsd t rsd t rsd t wed1 t wedf t rdh t rds a25?a0 23.3.4 peripheral module signal timing table 23.23 peripheral module signal timing (1) 1061, 1062 table and notes amended hd6417751 rbp240 (v) hd6417751 rbg240 (v) hd6417751 rbp200 (v) hd6417751 rbg200 (v) hd6417751 rf240 (v) hd6417751 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure notes notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on table 23.24 peripheral module signal timing (2) 1063, 1064 table and notes amended hd6417751vf133 deleted hd6417751bp167 hd6417751f167 (v) * 2 module item symbol min max unit figure notes notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.8 v , t a = ?20 to 75 c, c l = 30 pf, pll2 on
rev.4.00 oct. 10, 200 8 page lii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.4 peripheral module signal timing table 23.25 pcic signal timing (in pcireq/pcignt non- port mode) (1) 1069 table amended and note added hd6417751rbp240 (v), hd6417751rbp200 (v), hd6417751rbg240 (v), hd6417751rbg200 (v), hd6417751rf240 (v), hd6417751rf200 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf 33 mhz 66 mhz pin it em symbol min max min max unit figure input hold time t pcih 1. 5 ? 1.5 ? ns 23.72 idsel input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 output data delay time t pcival ? 10 ? 8 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 input hold time t pcih 1. 5 ? 1.5 ? ns 23.72 ad31?ad0 c/ be3 ?c/ be0 par pciframe irdy trdy pcistop pcilock devsel perr input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 output data delay time t pcival ? 10 ? 8 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 12 ns 23.71 input hold time t pcih 1. 5 ? 1.5 ? ns 23.72 pcireq1 / gntin pcireq2 / md9 pcireq3 / md10 pcireq4 / pcignt1 / reqout pcignt4 ? pcignt1 input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 note: * hd6417751rf240 (v), hd6417751rf200 (v)
rev.4.00 oct. 10, 200 8 page liii of xcviii rej09b0370-0400 item page revision (s ee manual for details) 23.3.4 peripheral module signal timing table 23.26 pcic signal timing (in pcireq/pcignt non- port mode) (2) 1070 table amended and note added hd6417751f133 deleted hd6417751bp167 (v), hd6417751f167 (v): v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf 33 mhz 66 mhz pin item symbol min max min max unit figure input hold time t pcih 1 ? 1 ? ns 23.72 idsel input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 output data delay time t pcival ? 10 ? 10 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 input hold time t pcih 1 ? 1 ? ns 23.72 ad31?ad0 c/ be3 ?c/ be0 par pciframe irdy trdy pcistop pcilock devsel perr input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 output data delay time t pcival ? 10 ? 10 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 12 ns 23.71 input hold time t pcih 1 ? 1 ? ns 23.72 pcireq1 / gntin pcireq2 / md9 pcireq3 / md10 pcireq4 / pcignt1 / reqout pcignt4 ? pcignt1 input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 note: * hd6417751f167 (v) table 23.27 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (1) 1072 table amended hd6417751rbp240 (v), hd6417751rbp200 (v), hd6417751rbg240 (v), hd6417751rbg200 (v), hd6417751rf240 (v), hd6417751rf200 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf table 23.28 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (2) table amended hd6417751bp167 (v), hd6417751f167 (v): v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf table 23.34 pcic signal timing(with pcireq/pcignt port settings in non-host mode) ? table deleted
rev.4.00 oct. 10, 2008 page liv of xcviii rej09b0370-0400 item page revision (s ee manual for details) appendix a address list table a.1 address list 1077 to 1084 synchronization clock iclk ick bclk bck pclk pck 1078 table amended module register p4 address area 7 address * 1 pcic pcicr h'fe20 0100 h'1e20 0100 * 2 appendix b package dimensions figure b.3 package dimensions (256-pin bga) 1087 newly added appendix c mode pin settings table c.1 clock operating modes (sh7751) 1089 table amended and notes added external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 off on on 6 3/2 3/2 h'0e1a 1 0 1 off on on 6 1 1 h'0e23 2 on on on 3 1 1/2 h'0e13 3 0 0 0 1 1 off on on 6 2 1 h'0e13 4 1 0 0 on on on 3 3/2 3/4 h'0e0a 5 1 off on on 6 3 3/2 h'0e0a 6 1 0 off off off 1 1/2 1/2 h'0808 notes: 1. the multiplication fa ctor of 1/2 frequency driver is solely determined by the clock operating mode. 2. for the ranges input clock frequency, see the description of the extal clock input frequency (f ex ) and the ckio clock output (f op ) in section 23.3.1, clock and control signal timing. table c.7 pci mode 1091 table amended pin value mode md9 mode 0 0 0 pci host with external clock input 1 0 1 pci host with feedback input clock from ckio md10
rev.4.00 oct. 10, 2008 page lv of xcviii rej09b0370-0400 item page revision (s ee manual for details) d.1 pin states table d.1 pin states in reset, power-down state, and bus- released state (pci enable, disable common) 1093, 1094 table amended reset (power-on) reset (manual) pin name i/o master slave master slave standby bus released hard- ware standby notes we3 / ioicwr o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z we2 / ioicrd o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z drak1?drak0 o l l * 11 o * 6 o z dmac md0/sck2 i * 17 i * 17 i * 11 i * 11 i * 11 z * 11 o * 6 i * 11 o scif txd i/o pi pi z * 11 o z * 11 o z * 11 o * 6 o z sci i/o i l l z table d.2 pin states in reset, power-down state, and bus- released state (pci enable) 1095 table amended reset (power on) reset (manual) standby reset (software) pin name i/o host non- host host non- host host non- host host non- host hard- ware standby notes pcireq4 i/o pi pz z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when usin g port pcireq2 / i/o i * i * 17 17 z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when usin g port pcireq3 / i/o i * i * 17 17 z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when usin g port md9 md10 table d.3 pin states in reset, power-down state, and bus- released state (pci disable) 1097 table amended reset (power-on) reset (manual) pin name i/o master slave master slave standby bus released hard- ware standby notes pcireq4 ? z z z z z z z pcireq2 /md9 i/o i/o i * 17 i * 17 z z z z z pcireq3 /md10 i * 17 i * 17 z z z z z table d.4 handling of pins when pci is not used 1099 table amended pin name i/o handling idsel i pull down to low level when idsel is not in use d.3 note on pin processing newly added appendix e synchronous dram address multiplexing tables 1109 description amended (9) bus 32 (64m: 4m 4b 4) 8 * (128m: 4m 8b 4) 4 appendix g power-on and power-off procedures 1115 to 1118 replaced
rev.4.00 oct. 10, 2008 page lvi of xcviii rej09b0370-0400 item page revision (s ee manual for details) appendix h product lineup table h.1 sh7751/sh7751r product lineup 1119 table and notes amended product name voltage operating frequency operating temperature * 1 part number * 2 package sh7751 1.8 v 167 mhz hd6417751bp167 (v) 256-pin bga ?20 to 75?c hd6417751f167 (v) 256-pin qfp hd6417751rbp240 (v) 256-pin bga hd6417751rf240 (v) 256-pin qfp 240 mhz ?20 to 75?c hd6417751rbg240 (v) 292-pin bga hd6417751rbp200 (v) 256-pin bga sh7751r v 200 mhz hd6417751rf200 (v) 256-pin qfp hd6417751rbg200 (v) 292-pin bga 1.5 notes: 1. contact a renesas sales office regarding product versions with specifications for a wider temperature range ( ? 40 to +85 c). 2. all listed products are available in lead-free versions. lead-free products have a ?v? appended at the end of the part number. appendix i version registers 1121, 1122 newly added all trademarks and registered trademarks ar e the property of th eir respective owners.
rev.4.00 oct. 10, 2008 page lvii of xcviii rej09b0370-0400 contents section 1 overview ............................................................................................................. 1 1.1 sh7751/sh7751r features .............................................................................................. 1 1.2 block diagram .................................................................................................................. 9 1.3 pin arrangement ............................................................................................................... 10 1.4 pin functions .................................................................................................................. .. 13 1.4.1 pin functions (2 56-pin q fp)............................................................................... 13 1.4.2 pin functions (2 56-pin bg a).............................................................................. 24 1.4.3 pin functions (2 92-pin bg a).............................................................................. 35 section 2 programming model ........................................................................................ 47 2.1 data formats ................................................................................................................... .. 47 2.2 register config uration ...................................................................................................... 48 2.2.1 privileged mode and banks ................................................................................. 48 2.2.2 general registers ................................................................................................. 51 2.2.3 floating-point re gisters....................................................................................... 53 2.2.4 control registers ................................................................................................. 55 2.2.5 system registers.................................................................................................. 56 2.3 memory-mapped re gisters............................................................................................... 58 2.4 data format in registers................................................................................................... 59 2.5 data formats in memory .................................................................................................. 59 2.6 processor states............................................................................................................... .. 60 2.7 processor modes ............................................................................................................... 62 section 3 memory management unit (mmu) ........................................................... 63 3.1 overview....................................................................................................................... .... 63 3.1.1 features................................................................................................................ 63 3.1.2 role of the mmu................................................................................................. 63 3.1.3 register config uration......................................................................................... 66 3.1.4 caution................................................................................................................. 66 3.2 register desc riptions ........................................................................................................ 6 7 3.3 address space.................................................................................................................. . 71 3.3.1 physical addr ess space ....................................................................................... 71 3.3.2 external memory space....................................................................................... 74 3.3.3 virtual addres s space.......................................................................................... 75 3.3.4 on-chip ram space........................................................................................... 76 3.3.5 address translation ............................................................................................. 76 3.3.6 single virtual memory mode and mu ltiple virtual me mory mode.................... 77 3.3.7 address space iden tifier (asi d) ......................................................................... 77
rev.4.00 oct. 10, 2008 page lviii of xcviii rej09b0370-0400 3.4 tlb functions .................................................................................................................. 78 3.4.1 unified tlb (utlb) co nfiguration ................................................................... 78 3.4.2 instruction tlb (itlb) configuration................................................................ 82 3.4.3 address transla tion met hod................................................................................ 82 3.5 mmu functions................................................................................................................ 8 5 3.5.1 mmu hardware management ............................................................................. 85 3.5.2 mmu software management .............................................................................. 85 3.5.3 mmu instruction (ldtlb)................................................................................. 85 3.5.4 hardware itlb miss handling ........................................................................... 86 3.5.5 avoiding synonym problems .............................................................................. 87 3.6 mmu excepti ons.............................................................................................................. 88 3.6.1 instruction tlb multiple hit exception.............................................................. 88 3.6.2 instruction tlb miss exception.......................................................................... 88 3.6.3 instruction tlb protection violation exception ................................................. 89 3.6.4 data tlb multiple h it exceptio n ....................................................................... 90 3.6.5 data tlb miss exception ................................................................................... 91 3.6.6 data tlb protection viol ation exception........................................................... 92 3.6.7 initial page write exception ................................................................................ 93 3.7 memory-mapped tlb co nfiguration............................................................................... 94 3.7.1 itlb address array ............................................................................................ 94 3.7.2 itlb data array 1............................................................................................... 95 3.7.3 itlb data array 2............................................................................................... 96 3.7.4 utlb address array........................................................................................... 97 3.7.5 utlb data array 1 ............................................................................................. 98 3.7.6 utlb data array 2 ............................................................................................. 99 3.8 usage notes .................................................................................................................... .. 100 section 4 caches .................................................................................................................. 101 4.1 overview....................................................................................................................... .... 101 4.1.1 features................................................................................................................ 101 4.1.2 register config uration......................................................................................... 102 4.2 register desc riptions ........................................................................................................ 1 03 4.3 operand cache (oc)......................................................................................................... 105 4.3.1 configuratio n ....................................................................................................... 105 4.3.2 read operation .................................................................................................... 108 4.3.3 write operation ................................................................................................... 109 4.3.4 write-back buffer ............................................................................................... 111 4.3.5 write-through bu ffer.......................................................................................... 111 4.3.6 ram mode .......................................................................................................... 111 4.3.7 oc index m ode ................................................................................................... 113
rev.4.00 oct. 10, 2008 page lix of xcviii rej09b0370-0400 4.3.8 coherency between cache an d external memory ............................................... 113 4.3.9 prefetch operation ............................................................................................... 113 4.3.10 notes on using oc ram mode (sh7751r only) when in cache enhanced mode .................................................................................................................... 114 4.4 instruction ca che (ic)....................................................................................................... 1 16 4.4.1 configuratio n ....................................................................................................... 116 4.4.2 read operation .................................................................................................... 119 4.4.3 ic index mo de ..................................................................................................... 120 4.5 memory-mapped cache config uration (sh7 751)............................................................ 120 4.5.1 ic address array ................................................................................................. 120 4.5.2 ic data array....................................................................................................... 122 4.5.3 oc address array................................................................................................ 123 4.5.4 oc data array ..................................................................................................... 124 4.6 memory-mapped cache config uration (sh775 1r) ......................................................... 125 4.6.1 ic address array ................................................................................................. 125 4.6.2 ic data array....................................................................................................... 127 4.6.3 oc address array................................................................................................ 128 4.6.4 oc data array ..................................................................................................... 129 4.6.5 summary of memory-mappe d oc addresses..................................................... 130 4.7 store queues ................................................................................................................... .. 131 4.7.1 sq configuration ................................................................................................. 131 4.7.2 sq writes............................................................................................................. 131 4.7.3 transfer to extern al memory............................................................................... 132 4.7.4 determination of sq a ccess exception............................................................... 133 4.7.5 sq read (sh7751r only).................................................................................... 133 4.7.6 sq usage notes (sh7 751 only) .......................................................................... 134 section 5 exceptions ........................................................................................................... 137 5.1 overview....................................................................................................................... .... 137 5.1.1 features................................................................................................................ 137 5.1.2 register config uration......................................................................................... 137 5.2 register desc riptions ........................................................................................................ 1 38 5.3 exception handling functions .......................................................................................... 139 5.3.1 exception handlin g flow .................................................................................... 139 5.3.2 exception handling vect or addresses ................................................................ 139 5.4 exception types and priorities ......................................................................................... 140 5.5 exceptio n fl ow ................................................................................................................. 143 5.5.1 exception fl ow .................................................................................................... 143 5.5.2 exception source a cceptance.............................................................................. 144 5.5.3 exception requests and bl bit ........................................................................... 146
rev.4.00 oct. 10, 2008 page lx of xcviii rej09b0370-0400 5.5.4 return from exceptio n handling......................................................................... 146 5.6 description of ex ceptions................................................................................................. 146 5.6.1 resets................................................................................................................... 147 5.6.2 general exceptions .............................................................................................. 152 5.6.3 interrupts.............................................................................................................. 166 5.6.4 priority order with mu ltiple exceptions.............................................................. 169 5.7 usage notes .................................................................................................................... .. 170 5.8 restric tions ................................................................................................................... .... 171 section 6 floating-point unit .......................................................................................... 173 6.1 overview....................................................................................................................... .... 173 6.2 data formats................................................................................................................... .. 173 6.2.1 floating-point format.......................................................................................... 173 6.2.2 non-numbers (nan) ........................................................................................... 175 6.2.3 denormalized nu mbers ....................................................................................... 176 6.3 registers...................................................................................................................... ...... 177 6.3.1 floating-point re gisters....................................................................................... 177 6.3.2 floating-point status/contro l register ( fpscr)................................................. 179 6.3.3 floating-point communicati on register (fpul) ................................................ 180 6.4 rounding....................................................................................................................... .... 181 6.5 floating-point ex ceptions................................................................................................. 181 6.6 graphics support functions.............................................................................................. 183 6.6.1 geometric operation instructio ns........................................................................ 183 6.6.2 pair single-precision data transfer..................................................................... 184 6.7 usage notes .................................................................................................................... .. 185 6.7.1 rounding mode and un derflow flag .................................................................. 185 6.7.2 setting of overflow flag by fipr or ftrv instruction ..................................... 186 6.7.3 sign of operation result when using fipr or ftrv instruction....................... 187 6.7.4 notes on double-precisi on fadd and fsub instructions ................................. 187 section 7 instruction set .................................................................................................... 189 7.1 execution enviro nment..................................................................................................... 189 7.2 addressing modes ............................................................................................................ 19 1 7.3 instruction set ................................................................................................................ ... 195 7.4 usage notes .................................................................................................................... .. 207 7.4.1 notes on trapa instruction, sleep instruction, and undefined instruction (h'fffd).............................................................................................................. 207
rev.4.00 oct. 10, 2008 page lxi of xcviii rej09b0370-0400 section 8 pipelining ............................................................................................................ 211 8.1 pipelines...................................................................................................................... ...... 211 8.2 parallel-exe cutab ility ........................................................................................................ 218 8.3 execution cycles and pi peline stallin g ............................................................................ 222 8.4 usage notes .................................................................................................................... .. 238 section 9 power-down modes ........................................................................................ 239 9.1 overview....................................................................................................................... .... 239 9.1.1 types of power-down modes ............................................................................. 239 9.1.2 register config uration......................................................................................... 241 9.1.3 pin configuration................................................................................................. 241 9.2 register desc riptions ........................................................................................................ 2 42 9.2.1 standby control regi ster (st bcr)..................................................................... 242 9.2.2 peripheral module pin high impedance control ................................................. 244 9.2.3 peripheral module pin pu ll-up contro l............................................................... 244 9.2.4 standby control regist er 2 (stbcr2 )................................................................ 245 9.2.5 clock stop register 00 (clkstp00) .................................................................. 246 9.2.6 clock stop clear register 00 (clkstpclr 00)................................................. 247 9.3 sleep mode ..................................................................................................................... .. 248 9.3.1 transition to sl eep mode..................................................................................... 248 9.3.2 exit from sleep mode.......................................................................................... 248 9.4 deep sleep mode .............................................................................................................. 2 48 9.4.1 transition to deep sleep mode............................................................................ 248 9.4.2 exit from deep sleep mode................................................................................. 249 9.5 pin sleep mode ................................................................................................................. 249 9.5.1 transition to pin sleep mode ............................................................................... 249 9.5.2 exit from pin sleep mode.................................................................................... 249 9.6 standby mode ................................................................................................................... 249 9.6.1 transition to stan dby mode................................................................................. 249 9.6.2 exit from standby mode...................................................................................... 250 9.6.3 clock pause f unction .......................................................................................... 251 9.7 module standby function ................................................................................................. 251 9.7.1 transition to module st andby function .............................................................. 251 9.7.2 exit from module sta ndby functio n.................................................................... 252 9.8 hardware standb y mode................................................................................................... 253 9.8.1 transition to hardware standby mo de ................................................................ 253 9.8.2 exit from hardware standby m ode ..................................................................... 253 9.8.3 usage notes ......................................................................................................... 254 9.9 status pin change timing ........................................................................................... 254
rev.4.00 oct. 10, 2008 page lxii of xcviii rej09b0370-0400 9.9.1 in reset ................................................................................................................ 255 9.9.2 in exit from standby mode ................................................................................. 256 9.9.3 in exit from sleep mode...................................................................................... 257 9.9.4 in exit from deep sleep mode ............................................................................ 260 9.9.5 hardware standby mo de timing......................................................................... 262 9.10 usage notes .................................................................................................................... .. 264 9.10.1 note on current co nsumption ............................................................................. 264 section 10 clock oscillation circuits ........................................................................... 267 10.1 overview....................................................................................................................... .... 267 10.1.1 features................................................................................................................ 267 10.2 overview of cpg.............................................................................................................. 2 69 10.2.1 block diagram of cpg........................................................................................ 269 10.2.2 cpg pin configur ation ........................................................................................ 272 10.2.3 cpg register conf iguration ................................................................................ 272 10.3 clock operating modes .................................................................................................... 273 10.4 cpg register desc ription................................................................................................. 275 10.4.1 frequency control regi ster (frq cr)................................................................. 275 10.5 changing the frequency ................................................................................................... 278 10.5.1 changing pll circuit 1 starting/stoppin g (when pll circuit 2 is off) ........... 278 10.5.2 changing pll circuit 1 starting/stoppin g (when pll circuit 2 is on)............ 278 10.5.3 changing bus clock division ratio (w hen pll circuit 2 is on) ...................... 279 10.5.4 changing bus clock division ratio (w hen pll circuit 2 is off) ..................... 279 10.5.5 changing cpu or peri pheral module clock division ra tio ............................... 279 10.6 output clock control........................................................................................................ 28 0 10.7 overview of watchdog timer .......................................................................................... 280 10.7.1 block diagra m..................................................................................................... 280 10.7.2 register config uration......................................................................................... 281 10.8 wdt register desc riptions .............................................................................................. 281 10.8.1 watchdog timer coun ter (wtcnt)................................................................... 281 10.8.2 watchdog timer control/statu s register (w tcsr)........................................... 282 10.8.3 notes on register access..................................................................................... 284 10.9 using the wdt ................................................................................................................. 285 10.9.1 standby clearing pr ocedure ................................................................................ 285 10.9.2 frequency changing procedure ........................................................................... 285 10.9.3 using watchdog ti mer mode .............................................................................. 286 10.9.4 using interval timer mode ................................................................................. 286 10.10 notes on board design ..................................................................................................... 287 10.11 usage notes .................................................................................................................... .. 289 10.11.1 invalid manual reset triggered by wa tchdog timer (sh7751 only)................ 289
rev.4.00 oct. 10, 2008 page lxiii of xcviii rej09b0370-0400 section 11 realtime clock (rtc) .................................................................................. 291 11.1 overview....................................................................................................................... .... 291 11.1.1 features................................................................................................................ 291 11.1.2 block diagra m ..................................................................................................... 292 11.1.3 pin configuration................................................................................................. 293 11.1.4 register config uration......................................................................................... 293 11.2 register desc riptions ........................................................................................................ 2 95 11.2.1 64 hz counter (r64cnt).................................................................................... 295 11.2.2 second counter (rseccnt) .............................................................................. 296 11.2.3 minute counter (r mincnt) .............................................................................. 296 11.2.4 hour counter (r hrcnt).................................................................................... 297 11.2.5 day-of-week counte r (rwkcnt)..................................................................... 297 11.2.6 day counter (rda ycnt) .................................................................................. 298 11.2.7 month counter (r moncnt) ............................................................................. 298 11.2.8 year counter (ryrcnt) .................................................................................... 299 11.2.9 second alarm regist er (rsecar) ..................................................................... 300 11.2.10 minute alarm register (rminar) ..................................................................... 300 11.2.11 hour alarm register (rhrar)........................................................................... 301 11.2.12 day-of-week alarm regi ster (rwkar)............................................................ 301 11.2.13 day alarm register (rdayar) ......................................................................... 302 11.2.14 month alarm register (rmonar) .................................................................... 303 11.2.15 rtc control register 1 (rcr1).......................................................................... 303 11.2.16 rtc control register 2 (rcr2).......................................................................... 305 11.2.17 rtc control register (rcr3) and year-alarm register (ryrar) (sh7751r only) .................................................................................................. 308 11.3 operation...................................................................................................................... ..... 309 11.3.1 time setting pr ocedures ...................................................................................... 309 11.3.2 time reading pr ocedures .................................................................................... 311 11.3.3 alarm function .................................................................................................... 312 11.4 interrupts ..................................................................................................................... ...... 313 11.5 usage notes .................................................................................................................... .. 313 11.5.1 register initiali zation........................................................................................... 313 11.5.2 carry flag and interrupt fl ag in standb y mode .................................................. 313 11.5.3 crystal oscillation circuit ................................................................................... 313 section 12 timer unit (tmu) ......................................................................................... 315 12.1 overview....................................................................................................................... .... 315 12.1.1 features................................................................................................................ 315 12.1.2 block diagra m ..................................................................................................... 316 12.1.3 pin configuration................................................................................................. 316
rev.4.00 oct. 10, 2008 page lxiv of xcviii rej09b0370-0400 12.1.4 register config uration......................................................................................... 317 12.2 register desc riptions ........................................................................................................ 3 18 12.2.1 timer output control re gister (tocr) .............................................................. 318 12.2.2 timer start regist er (tstr) ............................................................................... 319 12.2.3 timer start register 2 (tstr2)........................................................................... 320 12.2.4 timer constant regi sters (tco r) ...................................................................... 321 12.2.5 timer counters (tcnt) ...................................................................................... 321 12.2.6 timer control regist ers (tcr) ........................................................................... 322 12.2.7 input capture register 2 (tcpr2)....................................................................... 326 12.3 operation ...................................................................................................................... .... 327 12.3.1 counter operation................................................................................................ 327 12.3.2 input capture fu nction ........................................................................................ 330 12.4 interrupts..................................................................................................................... ...... 332 12.5 usage notes .................................................................................................................... .. 332 12.5.1 register writes .................................................................................................... 332 12.5.2 tcnt register reads .......................................................................................... 333 12.5.3 resetting the rtc fre quency divider................................................................. 333 12.5.4 external clock fr equency.................................................................................... 333 section 13 bus state controller (bsc) ......................................................................... 335 13.1 overview....................................................................................................................... .... 335 13.1.1 features................................................................................................................ 335 13.1.2 block diagra m..................................................................................................... 337 13.1.3 pin configuration................................................................................................. 338 13.1.4 register config uration......................................................................................... 340 13.1.5 overview of areas ............................................................................................... 341 13.1.6 pcmcia suppo rt ................................................................................................ 344 13.2 register desc riptions ........................................................................................................ 3 48 13.2.1 bus control register 1 (bcr1) ........................................................................... 348 13.2.2 bus control register 2 (bcr2) ........................................................................... 357 13.2.3 bus control register 3 ( bcr3) (sh7751r on ly) ............................................... 359 13.2.4 bus control register 4 ( bcr4) (sh7751r on ly) ............................................... 361 13.2.5 wait control register 1 (wcr1)......................................................................... 363 13.2.6 wait control register 2 (wcr2)......................................................................... 366 13.2.7 wait control register 3 (wcr3)......................................................................... 374 13.2.8 memory control regi ster (mcr) ........................................................................ 376 13.2.9 pcmcia control regi ster (pcr)........................................................................ 383 13.2.10 synchronous dram mode register (s dmr) .................................................... 386 13.2.11 refresh timer control/status register (rtc sr)................................................ 388 13.2.12 refresh timer counte r (rtcnt)........................................................................ 390
rev.4.00 oct. 10, 2008 page lxv of xcviii rej09b0370-0400 13.2.13 refresh time constant re gister (rtcor) ......................................................... 391 13.2.14 refresh count regist er (rfcr) .......................................................................... 392 13.2.15 notes on accessing refresh control regist ers.................................................... 392 13.3 operation...................................................................................................................... ..... 393 13.3.1 endian/access size and da ta alignment............................................................. 393 13.3.2 areas .................................................................................................................... 400 13.3.3 sram interface ................................................................................................... 405 13.3.4 dram interface .................................................................................................. 413 13.3.5 synchronous dram interface............................................................................. 427 13.3.6 burst rom inte rface............................................................................................ 457 13.3.7 pcmcia inte rface ............................................................................................... 460 13.3.8 mpx interface...................................................................................................... 471 13.3.9 byte control sram interface ............................................................................. 485 13.3.10 waits between acces s cycles.............................................................................. 489 13.3.11 bus arbitra tion..................................................................................................... 490 13.3.12 master mo de ........................................................................................................ 493 13.3.13 slave mode .......................................................................................................... 494 13.3.14 cooperation between mast er and slave............................................................... 495 13.3.15 notes on usage .................................................................................................... 495 section 14 direct memo ry access controller (dmac) .......................................... 497 14.1 overview....................................................................................................................... .... 497 14.1.1 features................................................................................................................ 497 14.1.2 block diagram (s h7751) .................................................................................... 500 14.1.3 pin configuration (sh7751) ................................................................................ 501 14.1.4 register configurat ion (sh77 51) ........................................................................ 502 14.2 register desc riptions ........................................................................................................ 5 04 14.2.1 dma source address register s 0?3 (sar0?sar3) .......................................... 504 14.2.2 dma destination address regi sters 0?3 (dar0?dar3).................................. 505 14.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3)......................... 506 14.2.4 dma channel control register s 0?3 (chcr0?chcr3)................................... 507 14.2.5 dma operation regist er (dmaor)................................................................... 515 14.3 operation...................................................................................................................... ..... 517 14.3.1 dma transfer procedure..................................................................................... 517 14.3.2 dma transfer re quests ...................................................................................... 520 14.3.3 channel prior ities................................................................................................. 523 14.3.4 types of dma transfer....................................................................................... 526 14.3.5 number of bus cycle states and dreq pin sampling timing .......................... 535 14.3.6 ending dma tr ansfer ......................................................................................... 549 14.4 examples of use ............................................................................................................... 552
rev.4.00 oct. 10, 2008 page lxvi of xcviii rej09b0370-0400 14.4.1 examples of transfer between extern al memory and an external device with dack .......................................................................................................... 552 14.5 on-demand data transfer mode (ddt mode)................................................................ 553 14.5.1 operation ............................................................................................................. 553 14.5.2 pins in ddt mode............................................................................................... 555 14.5.3 transfer request acceptance on each channel .................................................. 558 14.5.4 notes on use of ddt module ............................................................................. 580 14.6 configuration of the dmac (sh7751 r).......................................................................... 583 14.6.1 block diagram of the dmac.............................................................................. 583 14.6.2 pin configuration (sh7751r) ............................................................................. 584 14.6.3 register configuratio n (sh7751r) ..................................................................... 585 14.7 register descripti ons (sh7751r)..................................................................................... 588 14.7.1 dma source address registers 0 ? 7 (sar0 ? sar7).......................................... 588 14.7.2 dma destination address regi sters 0?7 (dar0?dar7).................................. 588 14.7.3 dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) ........................ 589 14.7.4 dma channel control registers 0 ? 7 (chcr0 ? chcr7) .................................. 589 14.7.5 dma operation regist er (dmaor) .................................................................. 593 14.8 operation (sh7 751r) ....................................................................................................... 595 14.8.1 channel specification for a no rmal dma transfer............................................ 595 14.8.2 channel specification for ddt -mode dma tran sfer ........................................ 595 14.8.3 transfer channel notifica tion in ddt mode ...................................................... 596 14.8.4 clearing request queues by dtr format........................................................... 597 14.8.5 interrupt-request codes ...................................................................................... 597 14.9 usage notes .................................................................................................................... .. 600 section 15 serial communication interface (sci) .................................................... 603 15.1 overview....................................................................................................................... .... 603 15.1.1 features................................................................................................................ 603 15.1.2 block diagra m..................................................................................................... 605 15.1.3 pin configuration................................................................................................. 606 15.1.4 register config uration......................................................................................... 606 15.2 register desc riptions ........................................................................................................ 6 07 15.2.1 receive shift regist er (scrsr1)........................................................................ 607 15.2.2 receive data regist er (scrdr1 ) ....................................................................... 607 15.2.3 transmit shift regist er (sctsr1) ...................................................................... 608 15.2.4 transmit data regist er (sctdr 1)...................................................................... 608 15.2.5 serial mode regist er (scsmr1)......................................................................... 609 15.2.6 serial control regist er (scscr1)....................................................................... 611 15.2.7 serial status regist er (scssr1).......................................................................... 615 15.2.8 serial port register (scsptr1) .......................................................................... 619
rev.4.00 oct. 10, 2008 page lxvii of xcviii rej09b0370-0400 15.2.9 bit rate register (scbrr1)................................................................................ 623 15.3 operation...................................................................................................................... ..... 631 15.3.1 overview.............................................................................................................. 631 15.3.2 operation in asynch ronous mode ....................................................................... 633 15.3.3 multiprocessor communi cation functi on............................................................ 644 15.3.4 operation in synchr onous mode ......................................................................... 655 15.4 sci interrupt sources and dmac .................................................................................... 665 15.5 usage notes .................................................................................................................... .. 666 section 16 serial communication interface with fifo (scif) ............................. 671 16.1 overview....................................................................................................................... .... 671 16.1.1 features................................................................................................................ 671 16.1.2 block diagra m ..................................................................................................... 673 16.1.3 pin configuration................................................................................................. 674 16.1.4 register config uration......................................................................................... 674 16.2 register desc riptions ........................................................................................................ 6 75 16.2.1 receive shift regist er (scrsr2)........................................................................ 675 16.2.2 receive fifo data regi ster (scfrd r2) ........................................................... 675 16.2.3 transmit shift regist er (sctsr2) ...................................................................... 676 16.2.4 transmit fifo data regi ster (scftdr2) .......................................................... 676 16.2.5 serial mode regist er (scsmr2)......................................................................... 677 16.2.6 serial control regist er (scscr2)....................................................................... 679 16.2.7 serial status regist er (scfsr2).......................................................................... 682 16.2.8 bit rate register (scbrr2)................................................................................ 688 16.2.9 fifo control regist er (scfcr2) ....................................................................... 689 16.2.10 fifo data count regi ster (scfdr2) ................................................................. 692 16.2.11 serial port register (scsptr2) .......................................................................... 693 16.2.12 line status regist er (sclsr2) ........................................................................... 700 16.3 operation...................................................................................................................... ..... 701 16.3.1 overview.............................................................................................................. 701 16.3.2 serial operat ion ................................................................................................... 703 16.4 scif interrupt sources and the dmac ............................................................................ 713 16.5 usage notes .................................................................................................................... .. 714 section 17 smart card interface ..................................................................................... 719 17.1 overview....................................................................................................................... .... 719 17.1.1 features................................................................................................................ 719 17.1.2 block diagra m ..................................................................................................... 720 17.1.3 pin configuration................................................................................................. 721 17.1.4 register config uration......................................................................................... 721
rev.4.00 oct. 10, 2008 page lxviii of xcviii rej09b0370-0400 17.2 register desc riptions ........................................................................................................ 7 22 17.2.1 smart card mode regist er (scscmr1) ............................................................. 722 17.2.2 serial mode regist er (scsmr1)......................................................................... 723 17.2.3 serial control regist er (scscr1)....................................................................... 724 17.2.4 serial status regist er (scssr1).......................................................................... 725 17.3 operation ...................................................................................................................... .... 726 17.3.1 overview.............................................................................................................. 726 17.3.2 pin connections ................................................................................................... 727 17.3.3 data format ......................................................................................................... 728 17.3.4 register setti ngs .................................................................................................. 729 17.3.5 clock.................................................................................................................... 731 17.3.6 data transfer operations..................................................................................... 734 17.4 usage notes .................................................................................................................... .. 741 section 18 i/o ports ............................................................................................................ 747 18.1 overview....................................................................................................................... .... 747 18.1.1 features................................................................................................................ 747 18.1.2 block diagra ms ................................................................................................... 748 18.1.3 pin configuration................................................................................................. 755 18.1.4 register config uration......................................................................................... 758 18.2 register desc riptions ........................................................................................................ 7 59 18.2.1 port control register a (pctra) ....................................................................... 759 18.2.2 port data register a (pdtra) ........................................................................... 760 18.2.3 port control regist er b (pct rb) ....................................................................... 761 18.2.4 port data register b (pdtrb) ............................................................................ 762 18.2.5 gpio interrupt control re gister (gpioic)......................................................... 763 18.2.6 serial port register (scsptr1) .......................................................................... 764 18.2.7 serial port register (scsptr2) .......................................................................... 765 section 19 interrupt controller (intc) ........................................................................ 769 19.1 overview....................................................................................................................... .... 769 19.1.1 features................................................................................................................ 769 19.1.2 block diagra m..................................................................................................... 769 19.1.3 pin configuration................................................................................................. 771 19.1.4 register config uration......................................................................................... 771 19.2 interrupt sources.............................................................................................................. . 772 19.2.1 nmi interrupt....................................................................................................... 772 19.2.2 irl interrup ts ...................................................................................................... 773 19.2.3 on-chip peripheral modu le interrupts ................................................................ 775 19.2.4 interrupt exception hand ling and prio rity........................................................... 776
rev.4.00 oct. 10, 2008 page lxix of xcviii rej09b0370-0400 19.3 register desc riptions ........................................................................................................ 7 80 19.3.1 interrupt priority registers a to d (ipra? iprd) ............................................... 780 19.3.2 interrupt control re gister (i cr).......................................................................... 781 19.3.3 interrupt priority level settting register 00 (intpri00) ................................... 783 19.3.4 interrupt factor register 00 (intreq00) ........................................................... 784 19.3.5 interrupt mask register 00 (intmsk 00)............................................................ 784 19.3.6 interrupt mask clear register 00 (intmskc lr00) .......................................... 785 19.3.7 intreq00, intmsk00, and intmsk clr00 bit allo cation .......................... 786 19.4 intc oper ation ................................................................................................................ 787 19.4.1 interrupt operati on sequence .............................................................................. 787 19.4.2 multiple interrupts ............................................................................................... 789 19.4.3 interrupt masking w ith mai bit .......................................................................... 789 19.5 interrupt respon se time ................................................................................................... 790 19.6 usage notes .................................................................................................................... .. 791 19.6.1 nmi interrupts (sh7751 only)............................................................................ 791 section 20 user break controller (ubc) ..................................................................... 795 20.1 overview....................................................................................................................... .... 795 20.1.1 features................................................................................................................ 795 20.1.2 block diagra m ..................................................................................................... 796 20.2 register desc riptions ........................................................................................................ 7 98 20.2.1 access to ubc re gisters ..................................................................................... 798 20.2.2 break address regist er a (bara) ..................................................................... 799 20.2.3 break asid register a (basra)....................................................................... 800 20.2.4 break address mask regi ster a (bamra)........................................................ 800 20.2.5 break bus cycle regist er a (bbra).................................................................. 801 20.2.6 break address regist er b (ba rb)...................................................................... 803 20.2.7 break asid register b (basrb) ....................................................................... 803 20.2.8 break address mask regi ster b (bam rb) ........................................................ 803 20.2.9 break data register b (bdrb) ........................................................................... 803 20.2.10 break data mask regi ster b (bdm rb).............................................................. 804 20.2.11 break bus cycle regi ster b ( bbrb) .................................................................. 805 20.2.12 break control regist er (brcr) .......................................................................... 805 20.3 operation...................................................................................................................... ..... 808 20.3.1 explanation of terms rela ting to acce sses......................................................... 808 20.3.2 explanation of terms relating to instruction in tervals ....................................... 808 20.3.3 user break operatio n sequence .......................................................................... 809 20.3.4 instruction access cy cle break ........................................................................... 810 20.3.5 operand access cycl e break............................................................................... 811 20.3.6 condition match fl ag setting .............................................................................. 812
rev.4.00 oct. 10, 2008 page lxx of xcviii rej09b0370-0400 20.3.7 program counter (pc) value saved .................................................................... 812 20.3.8 contiguous a and b settings fo r sequential co nditions ..................................... 813 20.3.9 usage notes ......................................................................................................... 814 20.4 user break debug supp ort functio n ................................................................................ 816 20.5 examples of use ............................................................................................................... 818 20.6 user break controller stop functi on................................................................................ 820 20.6.1 transition to user break cont roller stopped state.............................................. 820 20.6.2 cancelling the user break cont roller stopped state ........................................... 820 20.6.3 examples of stopping and restarti ng the user break controller........................ 821 section 21 high-performance user debug interface (h-udi) ............................. 823 21.1 overview....................................................................................................................... .... 823 21.1.1 features................................................................................................................ 823 21.1.2 block diagra m..................................................................................................... 823 21.1.3 pin configuration................................................................................................. 825 21.1.4 register config uration......................................................................................... 826 21.2 register desc riptions ........................................................................................................ 8 27 21.2.1 instruction regist er (sdir) ................................................................................. 827 21.2.2 data register (sddr) ......................................................................................... 828 21.2.3 bypass register (sdbpr) ................................................................................... 828 21.2.4 interrupt factor regi ster (sdint )....................................................................... 829 21.2.5 boundary scan regist er (sdbsr) ...................................................................... 829 21.3 operation ...................................................................................................................... .... 843 21.3.1 tap control......................................................................................................... 843 21.3.2 h-udi reset ........................................................................................................ 844 21.3.3 h-udi interrupt ................................................................................................... 844 21.3.4 boundary scan (extest, samp le/preload, bypass) ............................ 845 21.4 usage notes .................................................................................................................... .. 845 section 22 pci controller (pcic) .................................................................................. 847 22.1 overview....................................................................................................................... .... 847 22.1.1 features................................................................................................................ 847 22.1.2 block diagra m..................................................................................................... 848 22.1.3 pin configuration................................................................................................. 849 22.1.4 register config uration......................................................................................... 850 22.2 pcic register de scriptions .............................................................................................. 856 22.2.1 pci configuration regist er 0 (pciconf0) ........................................................ 856 22.2.2 pci configuration regist er 1 (pciconf1) ........................................................ 857 22.2.3 pci configuration regist er 2 (pciconf2) ........................................................ 863 22.2.4 pci configuration regist er 3 (pciconf3) ........................................................ 865
rev.4.00 oct. 10, 2008 page lxxi of xcviii rej09b0370-0400 22.2.5 pci configuration regist er 4 (pciconf4) ........................................................ 867 22.2.6 pci configuration regist er 5 (pciconf5) ........................................................ 869 22.2.7 pci configuration regist er 6 (pciconf6) ........................................................ 871 22.2.8 pci configuration register 7 (pciconf7) to pci configuration register 10 (pciconf10) ...................................................................................................... 873 22.2.9 pci configuration register 11 (pciconf 11) .................................................... 874 22.2.10 pci configuration register 12 (pciconf 12) .................................................... 875 22.2.11 pci configuration register 13 (pciconf 13) .................................................... 875 22.2.12 pci configuration register 14 (pciconf 14) .................................................... 876 22.2.13 pci configuration register 15 (pciconf 15) .................................................... 877 22.2.14 pci configuration register 16 (pciconf 16) .................................................... 879 22.2.15 pci configuration register 17 (pciconf 17) .................................................... 881 22.2.16 reserved area...................................................................................................... 883 22.2.17 pci control register (pcicr)............................................................................. 884 22.2.18 pci local space register [1 :0] (pcilsr [1:0]) .................................................. 888 22.2.19 pci local address register [1:0] (pcilar [1:0]).............................................. 890 22.2.20 pci interrupt regist er (pciint).......................................................................... 892 22.2.21 pci interrupt mask regi ster (pciin tm) ............................................................ 895 22.2.22 pci address data register at error (pci alr) ................................................... 897 22.2.23 pci command data register at error (pciclr) ................................................ 898 22.2.24 pci arbiter interrupt regi ster (pciaint) .......................................................... 900 22.2.25 pci arbiter interrupt mask register (pciaintm) ............................................. 902 22.2.26 pci error bus master data register (pcibmlr)............................................... 903 22.2.27 pci dma transfer arbitration register (pcidmabt) ..................................... 904 22.2.28 pci dma transfer pci address regi ster [3:0] (pcidpa [3:0]) ........................ 905 22.2.29 pci dma transfer local bus start addres s register [3:0] (pcidla [3:0]) ..... 907 22.2.30 pci dma transfer counter regist er [3:0] (pcidt c [3:0]) ............................... 908 22.2.31 pci dma control register [3 :0] (pcidcr [3:0]) .............................................. 910 22.2.32 pio address register (pcipar) ......................................................................... 913 22.2.33 memory space base regi ster (pcim br)............................................................ 915 22.2.34 i/o space base regist er (pciiobr) ................................................................... 917 22.2.35 pci power management interrup t register (pci pint)....................................... 918 22.2.36 pci power management interrupt ma sk register (pcipintm) ......................... 919 22.2.37 pci clock control regist er (pciclkr) ............................................................. 920 22.2.38 pcic-bsc regi sters............................................................................................ 921 22.2.39 port control register (pcipctr)........................................................................ 923 22.2.40 port data register (pcipdtr) ............................................................................ 926 22.2.41 pio data register (pcipdr)............................................................................... 927 22.3 description of op eration................................................................................................... 928 22.3.1 operating m odes.................................................................................................. 928
rev.4.00 oct. 10, 2008 page lxxii of xcviii rej09b0370-0400 22.3.2 pci commands .................................................................................................... 929 22.3.3 pcic initializa tion ............................................................................................... 930 22.3.4 local register access.......................................................................................... 931 22.3.5 host functio ns ..................................................................................................... 931 22.3.6 pci bus arbitration in non-host mode ............................................................... 934 22.3.7 pio transfers....................................................................................................... 934 22.3.8 target transfers................................................................................................... 937 22.3.9 dma transfers .................................................................................................... 940 22.3.10 transfer contention within pcic ........................................................................ 946 22.3.11 pci bus basic in terface ....................................................................................... 947 22.4 endians........................................................................................................................ ...... 959 22.4.1 internal bus (peripheral bus) inte rface for peripheral modules.......................... 959 22.4.2 endian control for local bus .............................................................................. 961 22.4.3 endian control in dma transfers....................................................................... 961 22.4.4 endian control in target transfer s (memory read/mem ory write) .................. 963 22.4.5 endian control in target transf ers (i/o read/i/o write) ................................... 966 22.4.6 endian control in target transfers (configuration read/confi guration write ).......................................................... 966 22.5 resett ing ...................................................................................................................... ..... 968 22.6 interrupts..................................................................................................................... ...... 969 22.6.1 interrupts from pcic to cpu .............................................................................. 969 22.6.2 interrupts from extern al pci devices.................................................................. 970 22.6.3 inta .................................................................................................................... 971 22.7 error det ection................................................................................................................ .. 971 22.8 pcic clock ..................................................................................................................... .. 971 22.9 power management .......................................................................................................... 972 22.9.1 power management overview............................................................................. 972 22.9.2 stopping the clock............................................................................................... 973 22.9.3 compatibility with st andby and sl eep................................................................. 976 22.10 port functions ................................................................................................................. .. 976 22.11 version management ........................................................................................................ 977 22.12 usage notes .................................................................................................................... .. 977 22.12.1 notes on arbiter interrupt usage (sh7751 only) ............................................... 977 22.12.2 notes on i/o read and i/o write commands (sh7751 only) ............................ 980 22.12.3 notes on configuration-read and configuration-write commands (sh7751 only )..................................................................................................... 980 22.12.4 notes on target read/write cycl e timing (sh7751 only)................................ 980 section 23 electrical characteristics ............................................................................. 981 23.1 absolute maximum ratings ............................................................................................. 981
rev.4.00 oct. 10, 2008 page lxxiii of xcviii rej09b0370-0400 23.2 dc character istics ............................................................................................................ 982 23.3 ac character istics ............................................................................................................ 994 23.3.1 clock and control si gnal timing .................................................................... 996 23.3.2 control signal timing ..................................................................................... 1006 23.3.3 bus timing ...................................................................................................... 1010 23.3.4 peripheral module si gnal timi ng.................................................................... 1061 23.3.5 ac characteristic test conditions................................................................... 1074 23.3.6 change in delay time based on load capaci tance ........................................ 1075 appendix a address list .............................................................................................. 1077 appendix b package dimensions ............................................................................... 1085 appendix c mode pin settings ................................................................................... 1089 appendix d pin functions ............................................................................................ 1093 d.1 pin states..................................................................................................................... .. 1093 d.2 handling of unus ed pins .............................................................................................. 1098 d.3 note on pin pr ocessing ................................................................................................. 1099 appendix e synchronous dram address multiplexing tables .................... 1101 appendix f instruction pref etching and its side effects ..................................... 1113 appendix g power-on and power-off procedures ............................................... 1115 g.1 power-on stipul ations .................................................................................................. 1115 g.2 power-off stipul ations ................................................................................................. 1115 g.3 common stipulations for powe r-on and powe r-off .................................................... 1118 appendix h product lineup ......................................................................................... 1119 appendix i version registers ...................................................................................... 1121
rev.4.00 oct. 10, 2008 page lxxiv of xcviii rej09b0370-0400
rev.4.00 oct. 10, 2008 page lxxv of xcviii rej09b0370-0400 figures section 1 overview figure 1.1 block diagram of sh7 751/sh7751r group functions......................................... 9 figure 1.2 pin arrangem ent (256-pin qfp) ............................................................................ 10 figure 1.3 pin arrangem ent (256-pin bga)........................................................................... 11 figure 1.4 pin arrangem ent (292-pin bga)........................................................................... 12 section 2 programming model figure 2.1 da ta formats ........................................................................................................ .. 47 figure 2.2 cpu register configura tion in each processor mode........................................... 50 figure 2.3 gene ral registers ................................................................................................... 52 figure 2.4 floating-po int registers ......................................................................................... 54 figure 2.5 data form ats in memory ....................................................................................... 60 figure 2.6 processor state transitions .................................................................................... 61 section 3 memory ma nagement unit (mmu) figure 3.1 role of the mmu ................................................................................................... 6 5 figure 3.2 mmu-relat ed registers......................................................................................... 67 figure 3.3 physical addre ss space (mmucr.at = 0) .......................................................... 71 figure 3.4 p4 area............................................................................................................. ...... 72 figure 3.5 external memory space ......................................................................................... 74 figure 3.6 virtual addres s space (mmucr.at = 1)............................................................. 75 figure 3.7 utlb co nfiguration .............................................................................................. 78 figure 3.8 relationship between pa ge size and address format............................................ 79 figure 3.9 itlb co nfiguration................................................................................................ 8 2 figure 3.10 flowchart of me mory access us ing utlb........................................................... 83 figure 3.11 flowchart of me mory access using itlb ............................................................ 84 figure 3.12 operation of ldtlb instruction............................................................................ 86 figure 3.13 memory-mapped itlb address array.................................................................. 95 figure 3.14 memory-mapped itlb data array 1 .................................................................... 96 figure 3.15 memory-mapped itlb data array 2 .................................................................... 97 figure 3.16 memory-mapped utlb address array ................................................................ 98 figure 3.17 memory-mapped utlb data array 1................................................................... 99 figure 3.18 memory-mapped u tlb data array 2................................................................... 100 section 4 caches figure 4.1 cache and store queu e control regist ers (ccr).................................................. 103 figure 4.2 configuration of operand cache (s h7751) ........................................................... 106 figure 4.3 configuration of op erand cache (sh7751r) ........................................................ 107
rev.4.00 oct. 10, 2008 page lxxvi of xcviii rej09b0370-0400 figure 4.4 configuration of write-back buffer ...................................................................... 111 figure 4.5 configuration of write-through buffer................................................................. 111 figure 4.6 configuration of in struction cache (sh7751) ....................................................... 117 figure 4.7 configuration of inst ruction cache (s h7751r)..................................................... 118 figure 4.8 memory-mapped ic address array ...................................................................... 121 figure 4.9 memory-mapped ic data array ............................................................................ 122 figure 4.10 memory-mapped oc address array..................................................................... 124 figure 4.11 memory-mapped oc data ar ray .......................................................................... 125 figure 4.12 memory-mapped ic address array ...................................................................... 127 figure 4.13 memory-mapped ic data array ............................................................................ 128 figure 4.14 memory-mapped oc address array..................................................................... 130 figure 4.15 memory-mapped oc data ar ray .......................................................................... 131 figure 4.16 store queue configuratio n..................................................................................... 132 section 5 exceptions figure 5.1 register b it configura tions.................................................................................... 138 figure 5.2 instruction executio n and exception handling...................................................... 143 figure 5.3 example of general ex ception acceptan ce order................................................. 145 section 6 floating-point unit figure 6.1 format of single-preci sion floating-poin t number............................................... 173 figure 6.2 format of double-preci sion floating-poin t number ............................................. 174 figure 6.3 single-precision nan bit pa ttern........................................................................... 176 figure 6.4 floating-po int registers......................................................................................... 17 8 section 8 pipelining figure 8.1 ba sic pipe lines ..................................................................................................... .. 212 figure 8.2 instruction ex ecution patte rns................................................................................ 213 figure 8.3 examples of pipelined execution........................................................................... 225 section 9 power-down modes figure 9.1 status output in power-on reset ..................................................................... 255 figure 9.2 status output in manual re set.......................................................................... 255 figure 9.3 status output in standby interrupt sequence............................................... 256 figure 9.4 status output in standby power-on reset sequence .................................. 256 figure 9.5 status output in standby manual reset sequence ...................................... 257 figure 9.6 status output in sleep interrupt sequence................................................... 257 figure 9.7 status output in sleep power-on reset sequence ...................................... 258 figure 9.8 status output in sleep manual reset se quence........................................... 259 figure 9.9 status output in deep sleep interrupt se quence ......................................... 260
rev.4.00 oct. 10, 2008 page lxxvii of xcviii rej09b0370-0400 figure 9.10 status output in deep sleep power-on reset sequence ............................. 260 figure 9.11 status output in deep sleep manual reset sequence ................................. 261 figure 9.12 hardware standby mode timing (when ca = low in normal operation) .......... 262 figure 9.13 hardware standb y mode timing (when ca = lo w in wdt operation) ............. 263 figure 9.14 timing when power ot her than vdd-rtc is off................................................ 263 figure 9.15 timing when vdd-rtc power is off on....................................................... 264 section 10 clock oscillation circuits figure 10.1 (1) block diag ram of cpg (s h7751)...................................................................... 269 figure 10.1 (2) block diagra m of cpg (sh7751r) ................................................................... 270 figure 10.2 block di agram of wdt ......................................................................................... 280 figure 10.3 writing to wtcnt and wt csr........................................................................... 284 figure 10.4 points for attention when using cr ystal resonator............................................... 287 figure 10.5 points for a ttention when using pll os cillator circ uit ....................................... 288 section 11 realtime clock (rtc) figure 11.1 block di agram of rtc .......................................................................................... 292 figure 11.2 examples of ti me setting pro cedures.................................................................... 309 figure 11.3 examples of ti me reading procedures.................................................................. 311 figure 11.4 example of us e of alarm f unction........................................................................ 312 figure 11.5 example of crystal os cillation circuit co nnection ............................................... 314 section 12 timer unit (tmu) figure 12.1 block di agram of tmu ......................................................................................... 316 figure 12.2 example of count op eration setting pr ocedure .................................................... 328 figure 12.3 tcnt auto-r eload opera tion ............................................................................... 329 figure 12.4 count timing when op erating on intern al clock .................................................. 329 figure 12.5 count timing when op erating on extern al clock ................................................. 330 figure 12.6 count timing when operating on on-chip rtc output cl ock............................ 330 figure 12.7 operation timing when using input captur e function ......................................... 331 section 13 bus state controller (bsc) figure 13.1 block di agram of bsc........................................................................................... 337 figure 13.2 correspondence between virtual ad dress space and external memory space..... 341 figure 13.3 external memo ry space allo cation ....................................................................... 343 figure 13.4 example of rdy sampling timing at which bcr4 is set (two wait cycles are inse rted by wcr2)............................................................ 362 figure 13.5 writing to rtcsr, rtcnt, rtcor, and rfcr................................................. 393 figure 13.6 basic timing of sram interface........................................................................... 406 figure 13.7 example of 32-bit da ta width sram co nnection ............................................... 407
rev.4.00 oct. 10, 2008 page lxxviii of xcviii rej09b0370-0400 figure 13.8 example of 16-bit da ta width sram co nnection ............................................... 408 figure 13.9 example of 8-bit da ta width sram connection ................................................. 409 figure 13.10 sram interface wait ti ming (software wa it only) ............................................ 410 figure 13.11 sram interface wait stat e timing (wait state insertion by rdy signal) .......... 411 figure 13.12 sram interface read strobe negate timing (ans = 1, anw = 4, and anh = 2) 412 figure 13.13 example of dram connectio n (32-bit data width, area 3) ............................... 413 figure 13.14 basic dram access timi ng ................................................................................. 415 figure 13.15 dram wa it state timi ng ..................................................................................... 416 figure 13.16 dram burs t access timi ng ................................................................................. 417 figure 13.17 dram bus cycle (edo mode , rcd = 0, anw = 0, tpc = 1)............................ 418 figure 13.18 burst access timi ng in dram edo mode.......................................................... 419 figure 13.19 (1) dram burst bus cycle, ras down mode start (fast page mode, rcd = 0, anw = 0)............................................................ 420 figure 13.19 (2) dram burst bus cycle, ras down mode continuation (fast page mode, rcd = 0, anw = 0)............................................................ 421 figure 13.19 (3) dram burst bus cycle, ras down mode start (edo mode, rcd = 0, anw = 0) ................................................................... 422 figure 13.19 (4) dram burst bus cycle, ras down mode continuation (edo mode, rcd = 0, anw = 0) ................................................................... 423 figure 13.20 cas-before-ras refresh oper ation..................................................................... 424 figure 13.21 dram cas-before-ras refresh cycle timing (tras = 0, trc = 1).............. 425 figure 13.22 dram self-re fresh cycle timing........................................................................ 426 figure 13.23 example of 32-bit data width synchronous dram connection (area 3) .......... 428 figure 13.24 basic timing for s ynchronous dram burst read ............................................... 431 figure 13.25 basic timing for s ynchronous dram single read.............................................. 433 figure 13.26 basic timing for s ynchronous dram burst write .............................................. 434 figure 13.27 basic timing for s ynchronous dram single write............................................. 436 figure 13.28 burs t read timing ................................................................................................. 438 figure 13.29 burst read timing (r as down, same ro w address) .......................................... 439 figure 13.30 burst read timing (ras down, different row addresses)................................. 440 figure 13.31 burs t write timing ................................................................................................ 441 figure 13.32 burst write timi ng (same row ad dress) ............................................................. 442 figure 13.33 burst write timing (different row ad dresses) .................................................... 443 figure 13.34 burst read cycle for different bank and row address following preceding burst read cycle.................................................................................................... 446 figure 13.35 auto-re fresh operation ......................................................................................... 44 8 figure 13.36 synchronous dram auto-refresh timing........................................................... 448 figure 13.37 synchronous dram self-refresh timing ............................................................ 450 figure 13.38 (1) synchronous dram mode write timing (pall)......................................... 452 figure 13.38 (2) synchronous dram mode wr ite timing (mode regi ster setting) ............... 453
rev.4.00 oct. 10, 2008 page lxxix of xcviii rej09b0370-0400 figure 13.39 basic timing of a burst read fr om synchronous dram (burst length = 8) ...... 455 figure 13.40 basic timing of a burs t write to synchr onous dram......................................... 456 figure 13.41 burst rom ba sic access ti ming .......................................................................... 458 figure 13.42 burst rom wait access ti ming ........................................................................... 459 figure 13.43 burst rom wait access ti ming ........................................................................... 460 figure 13.44 example of pcmcia interface .............................................................................. 464 figure 13.45 basic timing for pcmc ia memory card interface.............................................. 465 figure 13.46 wait timing for pcmc ia memory card interface ............................................... 466 figure 13.47 pcmcia sp ace allocatio n .................................................................................... 467 figure 13.48 basic timing for pc mcia i/o card interface ...................................................... 468 figure 13.49 wait timing for pc mcia i/o card interface ....................................................... 469 figure 13.50 dynamic bus sizing timing for pcmcia i/o card interface .............................. 470 figure 13.51 example of 32-bit da ta width mpx connection.................................................. 472 figure 13.52 mpx interface timing 1 (single r ead cycle, anw = 0, no external wait) ........ 473 figure 13.53 mpx interface timing 2 (single read , anw = 0, one external wait inserted) ... 474 figure 13.54 mpx interface timing 3 (single write cycle, anw = 0, no external wait)........ 475 figure 13.55 mpx interface timing 4 (single wr ite, anw = 1, one external wait inserted) . 476 figure 13.56 mpx interface timing 5 (burst read cycle, anw = 0, no external wait) .......... 477 figure 13.57 mpx interface timing 6 (burst read cycle, anw = 0, external wait control)... 478 figure 13.58 mpx interface timing 7 (burst write cycle, anw = 0, no external wait) ......... 479 figure 13.59 mpx interface timing 8 (burst wr ite cycle, anw = 1, external wait control). 480 figure 13.60 mpx interface timing 9 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits).................................................. 481 figure 13.61 mpx interface timing 10 (burst read cycle, anw = 0, one external wait inserted, bus width: 32 bits, tran sfer data size: 64 bits)................................... 482 figure 13.62 mpx interface timing 11 (burst write cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits).................................................. 483 figure 13.63 mpx interface timing 12 (bur st write cycle, anw = 1, one external wait inserted, bus width: 32 bits, tran sfer data size: 64 bits)................................... 484 figure 13.64 example of 32-bit data width byte cont rol sram............................................. 485 figure 13.65 byte control sram basic read cycle (no wait) ................................................ 486 figure 13.66 byte control sram basic read cycle (one internal wait cycl e) ....................... 487 figure 13.67 byte control sram basic re ad cycle (one internal wait + one external wa it) ........................................................................................................ 488 figure 13.68 waits betw een access cy cles ................................................................................ 490 figure 13.69 arb itration sequence.............................................................................................. 492 section 14 direct memory access controller (dmac) figure 14.1 block di agram of dmac ...................................................................................... 500 figure 14.2 dmac tran sfer flowchart .................................................................................... 519
rev.4.00 oct. 10, 2008 page lxxx of xcviii rej09b0370-0400 figure 14.3 round robin mode ................................................................................................ 52 4 figure 14.4 example of changes in prio rity order in roun d robin m ode............................... 525 figure 14.5 data flow in single address mode ....................................................................... 527 figure 14.6 dma transfer timing in single addr ess mode.................................................... 528 figure 14.7 operation in dual address mode........................................................................... 529 figure 14.8 example of transfer ti ming in dual a ddress mode ............................................. 530 figure 14.9 example of dma tran sfer in cycle st eal mode ................................................... 531 figure 14.10 example of dma tr ansfer in burst mode............................................................. 531 figure 14.11 bus handling with two dmac channels op erating............................................ 535 figure 14.12 dual address mode/cycle steal mode external bus external bus/ dreq (level detection), dack (read cycle) ................................................................ 538 figure 14.13 dual address mode/cycle steal mode external bus external bus/ dreq (edge detection), dack (read cycle) ................................................................. 539 figure 14.14 dual address mode/burst mode external bus external bus/ dreq (level detection), dack (read cycle) ................................................................ 540 figure 14.15 dual address mode/burst mode external bus external bus/ dreq (edge detection), dack (read cycle) ................................................................. 541 figure 14.16 dual address mode/cycle steal mode on-chip sci (level detection) external bus ...................................................................................................... 542 figure 14.17 dual address mode/cycle steal mode external bus on-chip sci (level detec tion).................................................................................................... 543 figure 14.18 single address mode/cycle steal mode external bus external bus/ dreq (level detec tion).................................................................................................... 544 figure 14.19 single address mode/cycle steal mode external bus external bus/ dreq (edge detec tion) .................................................................................................... 545 figure 14.20 single address mode/burst mode external bus external bus/ dreq (level detec tion).................................................................................................... 546 figure 14.21 single address mode/burst mode external bus external bus/ dreq (edge detec tion) .................................................................................................... 547 figure 14.22 single address mode/burst mode external bus external bus/ dreq (level detection)/32-byte block transfer (bus width: 32 bits, sdram: row hit writ e)....................................................................................................... 548 figure 14.23 on-demand transfer mode block diagram .......................................................... 553 figure 14.24 system configuration in on-demand data tran sfer mode................................... 555 figure 14.25 data transf er request fo rmat ............................................................................... 556 figure 14.26 single address mode/synchronous dram external device longword transfer sdram auto-precharge read bus cycle, burst (rcd = 1, cas latency = 3, tpc = 3)................................................................... 559
rev.4.00 oct. 10, 2008 page lxxxi of xcviii rej09b0370-0400 figure 14.27 single address mode/external device synchronous dram longword transfer sdram auto-precharge write bus cycle, burst (rcd = 1, trwl = 2, tpc=1).............................................................................. 560 figure 14.28 dual address mode/synchronous dram sram longword transfer ............ 561 figure 14.29 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-d emand data transfer ........................................... 562 figure 14.30 single address mode/burst mode/external device external bus 32-byte block transfer/channel 0 on-d emand data transfer ........................................... 562 figure 14.31 single address mode/burst mode/external bus external device 32-bit transfer/channel 0 on-dem and data tran sfer ..................................................... 563 figure 14.32 single address mode/burst mode/external device external bus 32-bit transfer/channel 0 on-dem and data tran sfer ..................................................... 564 figure 14.33 handshake protocol using data bu s (channel 0 on-demand data transfer) ..... 565 figure 14.34 handshake protocol without use of data bus (channel 0 on-demand da ta transfer) ................................................................. 566 figure 14.35 read from synchron ous dram precharge bank .................................................. 567 figure 14.36 read from synchronous dram non-precharge bank (row miss) ...................... 567 figure 14.37 read from synchr onous dram (row hit) ........................................................... 568 figure 14.38 write to synchron ous dram precharge bank...................................................... 568 figure 14.39 write to synchronous dram non-precharge bank (row miss).......................... 569 figure 14.40 write to synchr onous dram (row hit)............................................................... 569 figure 14.41 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-d emand data transfer ........................................... 570 figure 14.42 ddt mode se tting ................................................................................................. 571 figure 14.43 single address mode/burst mode/edge detection/ external device external bus data transfer ............................................................................... 571 figure 14.44 single address mode/burst mode/level detection/ external bus external device da ta transfer .......................................................................... 572 figure 14.45 single address mode/burst mode/edge detection/byte, word, longword, quadword/external bus external device da ta transfer................................... 572 figure 14.46 single address mode/burst mode/edge detection/byte, word, longword, quadword/external device external bus data transfer................................... 573 figure 14.47 single address mode/burst mode/32-byte block transfer/dma transfer request to channels 1?3 using data bus .............................................................. 574 figure 14.48 single address mode/burst mode/32-byte block transfer/ external bus external device data transfer/ direct data transfer request to channel 2 without using da ta bus ......................................................................................... 575 figure 14.49 single address mode/burst mode/external bus external device data transfer/direct data transfer request to cha nnel 2 ............................................. 576
rev.4.00 oct. 10, 2008 page lxxxii of xcviii rej09b0370-0400 figure 14.50 single address mode/burst mode/external device external bus data transfer/direct data transfer request to cha nnel 2 ............................................. 577 figure 14.51 single address mode/burst mode/external bus external device data transfer (active bank address)/direct data transfer request to channel 2........ 578 figure 14.52 single address mode/burst mode/external device external bus data transfer (active bank address)/direct data transfer request to channel 2........ 579 figure 14.53 block diag ram of the dmac ................................................................................ 583 figure 14.54 dtr format (transfer request format) (s h7751r)............................................. 594 figure 14.55 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-d emand data transfer........................................... 598 figure 14.56 single address mode/cycle steal mode/external bus external device/ 32-byte block transfer/on-demand da ta transfer on channel 4 ........................ 599 section 15 serial commu nication interface (sci) figure 15.1 block di agram of sci............................................................................................ 60 5 figure 15.2 sck pin............................................................................................................ ...... 621 figure 15.3 txd pin ............................................................................................................ ...... 622 figure 15.4 rxd pin............................................................................................................ ...... 622 figure 15.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)............................................................................................ 634 figure 15.6 relation between output clock and transfer data phase (asynchronous mode). 636 figure 15.7 sample sci ini tialization flow chart ...................................................................... 637 figure 15.8 sample serial tr ansmission flow chart .................................................................. 638 figure 15.9 example of transmit operation in asynchronous mode (example with 8-bit data, pa rity, one stop bit) ................................................... 640 figure 15.10 sample serial reception flowchar t (1).................................................................. 641 figure 15.11 example of sci receive opera tion (example with 8-bit data, parity, one stop b it).......................................................................................................... 644 figure 15.12 example of in ter-processor communication us ing multiprocessor format (transmission of data h'aa to receiving sta tion a) ........................................... 645 figure 15.13 sample multiprocessor seri al transmission flowchart ......................................... 647 figure 15.14 example of sci transmit op eration (example with 8-bit data, multiprocessor bit, on e stop b it).......................................................................... 649 figure 15.15 sample flowchart of multiprocessor serial reception with interrupt generation 651 figure 15.16 sample multiprocessor seri al reception flow chart (1)......................................... 652 figure 15.16 sample multiprocessor seri al reception flow chart (2)......................................... 653 figure 15.17 example of sci receive op eration (example with 8-bit data, multiprocessor bit, on e stop b it).......................................................................... 654 figure 15.18 data format in sy nchronous commun ication ....................................................... 655 figure 15.19 sample sci ini tialization flow chart ...................................................................... 657
rev.4.00 oct. 10, 2008 page lxxxiii of xcviii rej09b0370-0400 figure 15.20 sample serial tr ansmission flow chart .................................................................. 658 figure 15.21 example of sc i transmit oper ation ...................................................................... 660 figure 15.22 sample serial r eception flowchar t (1).................................................................. 661 figure 15.23 example of sc i receive oper ation........................................................................ 663 figure 15.24 sample flowchart for serial data transmission an d reception ............................ 664 figure 15.25 receive data sampling timing in asynch ronous mode ....................................... 668 figure 15.26 example of synchro nous transmission by dmac ............................................... 669 section 16 serial communicati on interface with fifo (scif) figure 16.1 block di agram of scif.......................................................................................... 673 figure 16.2 md8/ rts2 pin....................................................................................................... 696 figure 16.3 md7/ cts2 pin....................................................................................................... 697 figure 16.4 md 1/txd2 pin....................................................................................................... 698 figure 16.5 md 2/rxd2 pin ...................................................................................................... 698 figure 16.6 md 0/sck2 pin ...................................................................................................... 699 figure 16.7 sample scif in itialization flow chart .................................................................... 705 figure 16.8 sample serial tr ansmission flow chart .................................................................. 706 figure 16.9 example of transmit operation (example with 8-bit data, parity, one stop bi t).......................................................................................................... 708 figure 16.10 example of operation using modem control ( cts2 )........................................... 708 figure 16.11 sample serial r eception flowchar t (1).................................................................. 709 figure 16.11 sample serial r eception flowchar t (2).................................................................. 710 figure 16.12 example of scif receive oper ation (example with 8-bit data, parity, one stop bi t).......................................................................................................... 712 figure 16.13 example of operation using modem contro l (rts2)........................................... 712 figure 16.14 receive data sampling timing in asynch ronous mode ....................................... 716 section 17 smart card interface figure 17.1 block diagram of smart card in terface................................................................. 720 figure 17.2 schematic diagram of smar t card interface pi n connections............................... 727 figure 17.3 smart card in terface data fo rmat ......................................................................... 728 figure 17.4 tend gene ration timing...................................................................................... 730 figure 17.5 sample start character waveforms ....................................................................... 731 figure 17.6 difference in clock output according to gm bit se tting..................................... 734 figure 17.7 sample initia lization flowchart ............................................................................. 735 figure 17.8 sample transmission processing fl owchart .......................................................... 737 figure 17.9 sample reception processing flowchart ............................................................... 739 figure 17.10 receive data sampling timing in smart card mode ............................................ 741 figure 17.11 retransf er operation in sci receive mode ........................................................... 743 figure 17.12 retransfer operatio n in sci transm it mode.......................................................... 743
rev.4.00 oct. 10, 2008 page lxxxiv of xcviii rej09b0370-0400 figure 17.13 procedure for stopping and restarting the clock .................................................. 744 section 18 i/o ports figure 18.1 16 -bit port a ...................................................................................................... .... 748 figure 18.2 16 -bit port b ...................................................................................................... .... 749 figure 18.3 sck pin............................................................................................................ ...... 750 figure 18.4 txd pin ............................................................................................................ ...... 751 figure 18.5 rxd pin............................................................................................................ ...... 751 figure 18.6 md 1/txd2 pin....................................................................................................... 752 figure 18.7 md 2/rxd2 pin ...................................................................................................... 752 figure 18.8 md 0/sck2 pin ...................................................................................................... 753 figure 18.9 md7/ cts2 pin....................................................................................................... 754 figure 18.10 md8/ rts2 pin....................................................................................................... 755 section 19 interrupt controller (intc) figure 19.1 block di agram of intc......................................................................................... 770 figure 19.2 example of irl interrupt conn ection.................................................................... 773 figure 19.3 interrupt op eration flowchart................................................................................ 788 section 20 user break controller (ubc) figure 20.1 block diagram of user break controller............................................................... 796 figure 20.2 user break debug s upport function fl owchart .................................................... 817 section 21 high-performance user debug interface (h-udi) figure 21.1 block diagram of h-udi circuit........................................................................... 824 figure 21.2 tap control stat e transition di agram.................................................................. 843 figure 21.3 h-udi reset........................................................................................................ ... 844 section 22 pci controller (pcic) figure 22.1 pcic bl ock diagram ............................................................................................. 848 figure 22.2 pio memo ry space acces s.................................................................................... 936 figure 22.3 pio i/ o space access ............................................................................................ 93 7 figure 22.4 local address space accessing method ............................................................... 938 figure 22.5 example of dma transfer control register settings ........................................... 942 figure 22.6 example of dma transfer flowchart ................................................................... 944 figure 22.7 master write cycle in host mode (single)............................................................ 948 figure 22.8 master read cycle in host mode (single)............................................................. 949 figure 22.9 master memory write cycl e in non-host mode (burst) ...................................... 950 figure 22.10 master memory read cycl e in non-host mode (burst) ....................................... 951 figure 22.11 target read cycle in non-host mode (single) ..................................................... 953
rev.4.00 oct. 10, 2008 page lxxxv of xcviii rej09b0370-0400 figure 22.12 target write cycle in non-host mode (single) .................................................... 954 figure 22.13 target memory read cy cle in host mode (burst) ................................................ 955 figure 22.14 target memory write cy cle in host mode (burst) ............................................... 956 figure 22.15 master memory write cycle in host mode (burst, wi th stepping)...................... 957 figure 22.16 target memory read cycle in host mode (burst, wi th stepping) ....................... 958 figure 22.17 endian conversion modes for periphe ral bus ....................................................... 959 figure 22.18 peripheral bus ? pci bus data a lignment .......................................................... 960 figure 22.19 endian cont rol for local bus................................................................................. 961 figure 22.20 data alignmen t at dma tran sfer.......................................................................... 962 figure 22.21 (1) data alignment at target me mory transfer (big-endian local bus) ............ 964 figure 22.21 (2) data alignment at target me mory transfer (little-endian local bus) ......... 965 figure 22.22 data alignment at target i/o tran sfer (both big endian an d little endian) ....... 966 figure 22.23 data alignment at target configuration transfer (both big endian and little endian )...................................................................... 967 figure 22.24 target bus timeout interrupt generation example 1 (example in which the target device asserts stop at the sixteenth clock cycle after frame was asserted).................................................................................. 978 figure 22.25 target bus timeout interrupt generation example 2 (example in which the target device takes 8 clock cycles to prepare for the third data transfer). 979 figure 22.26 master bus timeout interrupt generation example 1 (example in which the master device prepares the data and asserts irdy at the eighth clock cycle after frame was asserted) ....................................................................... 979 figure 22.27 master bus timeout interrupt generation example 2 (example in which the master device takes 8 clock cycles to prepare for the third data transfer following the se cond data phase) ........................................................... 980 section 23 electrical characteristics figure 23.1 extal cloc k input timi ng .............................................................................. 1001 figure 23.2 (1) ckio cl ock output ti ming ........................................................................ 1001 figure 23.2 (2) ckio cl ock output ti ming ........................................................................ 1001 figure 23.3 power-on osci llation settling time .................................................................. 1002 figure 23.4 standby return oscillation settling time (return by reset or mreset ) .... 1002 figure 23.5 power-on osci llation settling time .................................................................. 1003 figure 23.6 standby return oscillation settling time (return by reset or mreset ) .... 1003 figure 23.7 standby return oscillati on settling time (retur n by nmi).............................. 1004 figure 23.8 standby return oscillation settling time (return by irl3 ? irl0 )................... 1004 figure 23.9 pll synchronization settling time in case of reset, mreset or nmi interrup t ..................................................................................................... 1005 figure 23.10 pll synchronization settling ti me in case of ir l interrupt............................ 1005 figure 23.11 control signal timi ng........................................................................................ 1008
rev.4.00 oct. 10, 2008 page lxxxvi of xcviii rej09b0370-0400 figure 23.12 (1) pin drive ti ming for standb y mode ........................................................... 1008 figure 23.12 (2) pin drive timing for software stan dby mode ............................................ 1009 figure 23.13 sram bus cycle: ba sic bus cycle (n o wait) ................................................. 1014 figure 23.14 sram bus cycle: basic bus cycle (one inte rnal wait) .................................. 1015 figure 23.15 sram bus cycle: basic bus cycle (one internal wait + one external wait) 1016 figure 23.16 sram bus cycle: basic bus cycle (no wait, address setup/ hold time insertion, an s = 1, anh = 1)........................................................... 1017 figure 23.17 burst rom bu s cycle (no wait) ...................................................................... 1018 figure 23.18 burst rom bus cycle (1st data: one internal wait + one external wait; 2nd/3rd/4th data: one internal wait)................................................................. 1019 figure 23.19 burst rom bus cycle (no wait, address setup/hold time insertion, ans = 1, anh = 1) ............................................................................................. 1020 figure 23.20 burst rom bus cycle (one inte rnal wait + one exte rnal wait) ..................... 1021 figure 23.21 synchronous dram auto-precharge read bus cycle: single (rcd [1:0] = 01, cas latency = 3, tpc [2:0] = 011) ...................................... 1022 figure 23.22 synchronous dram auto-p recharge read bus cycle: burst (rcd [1:0] = 01, cas latency = 3, tpc [2:0] = 011) ...................................... 1023 figure 23.23 synchronous dram normal read bus cycle: act + read commands, burst (rasd = 1, rcd [1:0] = 01, cas latenc y = 3)...................................... 1024 figure 23.24 synchronous dram normal read bus cycle: pre + act + read commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, cas latency = 3)............................................................................................... 1025 figure 23.25 synchronous dram normal read bus cycle: read command, burst (rasd = 1, cas latency = 3) .......................................................................... 1026 figure 23.26 synchronous dram auto-precharge write bus cycle: single (rcd [1:0] = 01, tpc [2:0] = 00 1, trwl [2:0] = 010).................................... 1027 figure 23.27 synchronous dram auto-precharge write bus cycle: burst (rcd [1:0] = 01, tpc [2:0] = 00 1, trwl [2:0] = 010).................................... 1028 figure 23.28 synchronous dram normal write bus cycle: act + write commands, burst (rasd = 1, rcd [1:0] = 01, trwl [2:0] = 010) ................................... 1029 figure 23.29 synchronous dram normal write bus cycle: pre + act + write commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, trwl [2:0] = 010) ............................................................................................ 1030 figure 23.30 synchronous dram normal write bus cycle: write command, burst (rasd = 1, trwl [2:0] = 010) .............................................................. 1031 figure 23.31 synchronous dram bus cycle: precharge command (tpc [2:0] = 001) ....... 1032 figure 23.32 synchronous dram bus cycle: auto-refresh (tras = 1, trc [2:0] = 001) 1033 figure 23.33 synchronous dram bus cycle: self-refresh (trc [2:0] = 001 ) .................... 1034 figure 23.34 (a) synchronous dram bus cycl e: mode register se tting (pall)............... 1035 figure 23.34 (b) synchronous dram bus cy cle: mode register setting (set) ................. 1036
rev.4.00 oct. 10, 2008 page lxxxvii of xcviii rej09b0370-0400 figure 23.35 dram bus cycles (1) rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 001 (2) rcd [1:0] = 01, anw [2:0] = 00 1, tpc [2:0] = 010 ......................................... 1037 figure 23.36 dram bus cycle (edo mode, rcd [1:0] = 00, anw [2:0] = 000, trc [2:0] = 001)................................................................................................ 1038 figure 23.37 dram bus cycle (edo mode, rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 001) ................................................................................................ 1039 figure 23.38 dram burst bus cycle (edo mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001) ................................................................................................ 1040 figure 23.39 dram burst bus cycle (edo mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001, 2-cycle cas negate pulse width) ........................................ 1041 figure 23.40 dram burst bus cy cle: ras down mode state (edo mode, rcd [1:0] = 00 , anw [2:0] = 000) .............................................. 1042 figure 23.41 dram burst bus cycle: ras down mode continuation (edo mode, rcd [1:0] = 00 , anw [2:0] = 000) .............................................. 1043 figure 23.42 dram burst bus cycle (fast page mode, rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 00 1)................................................................... 1044 figure 23.43 dram burst bus cycle (fast page mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 00 1)................................................................... 1045 figure 23.44 dram burst bus cycle (fast page mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001, 2-cycle cas negate pulse width) ........................................ 1046 figure 23.45 dram burst bus cycle: ra s down mode state (fast page mode, rcd [1:0] = 00, anw [2:0] = 00 0).................................................................... 1047 figure 23.46 dram burst bus cycle: ras down mode continuation (fast page mode, rcd [1:0] = 00, anw [2:0] = 000) ....................................... 1048 figure 23.47 dram bus cycle: dram cas-before-ras refresh (tras [2:0] = 000, t rc [2:0] = 00 1) ............................................................... 1049 figure 23.48 dram bus cycle: dram cas-before-ras refresh (tras [2:0] = 001, t rc [2:0] = 00 1) ............................................................... 1050 figure 23.49 dram bus cycle: dram self-refresh (trc [2:0] = 001) ............................. 1051 figure 23.50 pcmcia memory bus cycle (1) ted [2:0] = 000, teh [2:0] = 000, no wait (2) ted [2:0] = 001, teh [2:0] = 001, one internal wait + one external wa it...................................................................................................... 1052 figure 23.51 pcmcia i/o bus cycle (1) ted [2:0] = 000, teh [2:0] = 000, no wait (2) ted [2:0] = 001, teh [2:0] = 001, one internal wait + one external wait .............................................................................................. 1053 figure 23.52 pcmcia i/o bus cycle (ted [2:0] = 001, teh [2:0] = 001, one internal wait, bus sizing ) .......................................................................... 1054 figure 23.53 mpx basic bus cycle: read (1) 1s t data (one internal wait) (2) 1st data (one internal wait + on e external wait) .......................................................... 1055
rev.4.00 oct. 10, 2008 page lxxxviii of xcviii rej09b0370-0400 figure 23.54 mpx basic bus cycle: write (1) 1st data (no wait) (2) 1st data (one internal wait) (3) 1st data (one internal wait + one external wait) ...... 1056 figure 23.55 mpx bus cycle: burst read (1) 1st data (one internal wait), 2nd to 8th data (no internal wait) (2) 1st data (no internal wait), 2nd to 8th data (no internal wa it + external wait control) ............................. 1057 figure 23.56 mpx bus cycle: burst write (1) no internal wait (2) 1st data (one internal wait), 2nd to 8th data (no internal wait + external wait contro l) ..................................................................................................... 1058 figure 23.57 memory byte control sram bus cycles (1) basic read cycle (no wait) (2) basic read cycle (one in ternal wait) (3) basic read cycle (one internal wait + on e external wait) .......................................................... 1059 figure 23.58 memory byte control sr am bus cycle: basic read cycle (no wait, address setup/hold time insertion, ans [0] = 1, anh [1:0] = 01) . 1060 figure 23.59 tclk input timi ng ........................................................................................... 1065 figure 23.60 rtc oscillation settl ing time at po wer-on...................................................... 1065 figure 23.61 sck inpu t clock timi ng ................................................................................... 1065 figure 23.62 sci i/o synchron ous mode clock timing ........................................................ 1066 figure 23.63 i/o port in put/output ti ming............................................................................. 1066 figure 23.64 (a) dreq /drak timi ng ................................................................................. 1066 figure 23.64 (b) dbreq / tr input timing and bavl output ti ming ................................ 1067 figure 23.65 tck i nput timing.............................................................................................. 106 7 figure 23.66 reset hold timing.......................................................................................... 1068 figure 23.67 h-udi data transfer ti ming............................................................................. 1068 figure 23.68 pin break timing ............................................................................................... 10 68 figure 23.69 nmi in put timing.............................................................................................. 106 8 figure 23.70 pci cloc k input timi ng..................................................................................... 1071 figure 23.71 output signal timi ng......................................................................................... 1071 figure 23.72 output signal timi ng......................................................................................... 1072 figure 23.73 i/o port in put/output ti ming............................................................................. 1073 figure 23.74 output load circuit ........................................................................................... 107 4 figure 23.75 load capacitance ? delay time .......................................................................... 1075 appendix b package dimensions figure b.1 package dimensio ns (256-pin qfp) .................................................................. 1085 figure b.2 package dimensio ns (256-pin bga) ................................................................. 1086 figure b.3 package dimensio ns (292-pin bga) ................................................................. 1087 appendix f instruction prefetching and its side effects figure f.1 instruc tion prefetch ............................................................................................ 111 3
rev.4.00 oct. 10, 2008 page lxxxix of xcviii rej09b0370-0400 appendix g power-on and power-off procedures figure g.1 method for temporarily sele cting clock operatio n mode 6 ............................. 1117 figure g.2 power-on procedure 1 ....................................................................................... 1118 figure g.3 power-on procedure 2 ....................................................................................... 1118
rev.4.00 oct. 10, 2008 page xc of xcviii rej09b0370-0400
rev.4.00 oct. 10, 2008 page xci of xcviii rej09b0370-0400 tables section 1 overview table 1.1 sh7751/sh7751r features.................................................................................... 2 table 1.2 pin functions.......................................................................................................... 13 table 1.3 pin functions.......................................................................................................... 24 table 1.4 pin functions.......................................................................................................... 35 section 2 programming model table 2.1 initial register values ............................................................................................ 49 section 3 memory ma nagement unit (mmu) table 3.1 mmu regist ers ...................................................................................................... 66 section 4 caches table 4.1 cache features (sh7751)....................................................................................... 101 table 4.2 cache features (sh7751r) .................................................................................... 102 table 4.3 store queue features.............................................................................................. 102 table 4.4 cache control re gisters......................................................................................... 102 section 5 exceptions table 5.1 exception-related registers .................................................................................. 137 table 5.2 exceptions .............................................................................................................. 140 table 5.3 types of re set........................................................................................................ 148 section 6 floating-point unit table 6.1 floating-point number form ats and parameters ................................................... 174 table 6.2 floating-point ranges ............................................................................................ 175 section 7 instruction set table 7.1 addressing modes and effe ctive addre sses .......................................................... 191 table 7.2 notation used in inst ruction li st ........................................................................... 195 table 7.3 fixed-point transfer instructio ns........................................................................... 196 table 7.4 arithmetic operation instructions.......................................................................... 198 table 7.5 logic operation in structions.................................................................................. 200 table 7.6 shift instruc tions .................................................................................................... 201 table 7.7 branch instructions................................................................................................. 202 table 7.8 system control in structions ................................................................................... 203 table 7.9 floating-point single-precisi on instructions.......................................................... 205 table 7.10 floating-point double-preci sion instruc tions ........................................................ 206
rev.4.00 oct. 10, 2008 page xcii of xcviii rej09b0370-0400 table 7.11 floating-point control instructions........................................................................ 206 table 7.12 floating-point graphics acce leration instru ctions ................................................ 207 section 8 pipelining table 8.1 instruction groups.................................................................................................. 218 table 8.2 parallel-executab ility ............................................................................................. 222 table 8.3 execution cy cles.................................................................................................... 229 section 9 power-down modes table 9.1 status of cpu and peripheral modu les in power-down modes ............................ 240 table 9.2 power-down mode registers ................................................................................ 241 table 9.3 power-down mode pins ........................................................................................ 241 table 9.4 state of registers in standby m ode ....................................................................... 250 section 10 clock oscillation circuits table 10.1 cpg pins ................................................................................................................ 272 table 10.2 cpg regist er.......................................................................................................... 272 table 10.3 (1) clock operating mode s (sh7751) ..................................................................... 273 table 10.3 (2) clock operating mode s (sh7751r) .................................................................. 273 table 10.4 frqcr settings and internal clock frequencies .................................................. 274 table 10.5 wdt register s....................................................................................................... 281 section 11 realtime clock (rtc) table 11.1 rtc pins ................................................................................................................ 293 table 11.2 rtc register s ........................................................................................................ 293 table 11.3 crystal oscillation circuit consta nts (recommended values).............................. 313 section 12 timer unit (tmu) table 12.1 tmu pins ............................................................................................................... 316 table 12.2 tmu register s ....................................................................................................... 317 table 12.3 tmu interrupt sources .......................................................................................... 332 section 13 bus state controller (bsc) table 13.1 bsc pins ................................................................................................................ 338 table 13.2 bsc register s ........................................................................................................ 340 table 13.3 external memory space map................................................................................. 342 table 13.4 pcmcia interface features................................................................................... 344 table 13.5 pcmcia support interfaces .................................................................................. 345 table 13.6 idle insertion betw een accesses............................................................................. 365 table 13.7 when mpx interface is set (areas 0 to 6)............................................................. 373
rev.4.00 oct. 10, 2008 page xciii of xcviii rej09b0370-0400 table 13.8 32-bit external device/big-endian access and data al ignment .......................... 394 table 13.9 16-bit external device/big-endian access and data al ignment .......................... 395 table 13.10 8-bit external device/big-endian access and data alignment ............................ 396 table 13.11 32-bit external device/little-endian access and data alignment ....................... 397 table 13.12 16-bit external device/little-endian access and data alignment ....................... 398 table 13.13 8-bit external device/little-endian access and data alignment ......................... 399 table 13.14 relationship between amxext and amx2?0 bits and address multiplexing... 414 table 13.15 example of correspondence between this lsi and synchronous dram address pins (32-bit bus width, amx2?amx0 = 000, amxext = 0) 429 table 13.16 cycles in which pipelined access can be used ................................................... 445 table 13.17 relationship between address and ce when using pcmcia interface .............. 462 section 14 direct memory access controller (dmac) table 14.1 dmac pins ............................................................................................................ 501 table 14.2 dmac pins in ddt mode .................................................................................... 502 table 14.3 dmac registers .................................................................................................... 502 table 14.4 selecting external request mode with rs bits ..................................................... 521 table 14.5 selecting on-chip peripheral module request mode with rs bits ...................... 522 table 14.6 supported dma transfers ..................................................................................... 526 table 14.7 relationship between dma transfer type , request mode, and bus mode ......... 532 table 14.8 external request transfer sources and de stinations in normal dma mode ....... 533 table 14.9 external request transfer sources an d destinations in ddt mode ..................... 534 table 14.10 conditions for transfer between external memory and an external device with dack, and correspondi ng register settings ................................................ 552 table 14.11 usable sz, id, and md comb ination in ddt mode............................................. 557 table 14.12 dmac pins ............................................................................................................ 584 table 14.13 dmac pins in ddt mode .................................................................................... 585 table 14.14 register config uration ........................................................................................... 586 table 14.15 channel selection by dtr form at (dmaor.dbl = 1)....................................... 594 table 14.16 notification of transfer channel in eight-channel ddt mode ............................ 596 table 14.17 function of bavl .................................................................................................. 596 table 14.18 dtr format for clearing request queues ............................................................ 597 table 14.19 dmac interrupt-requ est codes............................................................................ 598 section 15 serial commu nication interface (sci) table 15.1 sci pins.................................................................................................................. 606 table 15.2 sci register s.......................................................................................................... 606 table 15.3 examples of bit rates and scbrr1 se ttings in asynchronous mode.................. 625 table 15.4 examples of bit rates and scbrr1 se ttings in synchrono us mode.................... 628
rev.4.00 oct. 10, 2008 page xciv of xcviii rej09b0370-0400 table 15.5 maximum bit rate for various freque ncies with baud rate generator (asynchronous mode)............................................................................................ 629 table 15.6 maximum bit rate with external cloc k input (asynchronous mode).................. 630 table 15.7 maximum bit rate with external cl ock input (synchronous mode) .................... 630 table 15.8 scsmr1 settings for serial tran sfer format selection ........................................ 632 table 15.9 scsmr1 and scscr1 settings for sc i clock source se lection.......................... 633 table 15.10 serial transfer formats (a synchronous mo de) ..................................................... 635 table 15.11 receive error co nditions ....................................................................................... 643 table 15.12 sci interrupt sources ............................................................................................. 666 table 15.13 scssr1 status flags and transf er of receive data.............................................. 667 section 16 serial communicati on interface with fifo (scif) table 16.1 scif pins ............................................................................................................... 674 table 16.2 scif regist ers ....................................................................................................... 674 table 16.3 scsmr2 settings for serial tran sfer format selection ........................................ 702 table 16.4 scscr2 settings for scif cl ock source sel ection .............................................. 702 table 16.5 serial transfer formats.......................................................................................... 703 table 16.6 scif interrupt sources........................................................................................... 714 section 17 smart card interface table 17.1 smart card inte rface pins ...................................................................................... 721 table 17.2 smart card interface registers ............................................................................... 721 table 17.3 smart card interface re gister setti ngs .................................................................. 729 table 17.4 values of n and corresponding cks1 and cks0 settings .................................... 732 table 17.5 examples of bit rate b (bits/s) for vari ous scbrr1 settings (when n = 0)....... 732 table 17.6 examples of scbrr1 settings for bit ra te b (bits/s) (w hen n = 0) .................... 732 table 17.7 maximum bit rate at various frequencie s (smart card interface mode) ............ 733 table 17.8 register settings and sck pin state ...................................................................... 733 table 17.9 smart card mode operating stat es and interrupt sources..................................... 740 section 18 i/o ports table 18.1 32-bit general-purpose i/o port pins .................................................................... 755 table 18.2 sci i/o port pins.................................................................................................... 757 table 18.3 scif i/o port pins.................................................................................................. 757 table 18.4 i/o port regi sters ................................................................................................... 758 section 19 interrupt controller (intc) table 19.1 intc pins............................................................................................................... 771 table 19.2 intc regist ers....................................................................................................... 771 table 19.3 irl3 ? irl0 pins and interr upt levels .................................................................... 774
rev.4.00 oct. 10, 2008 page xcv of xcviii rej09b0370-0400 table 19.4 interrupt exception handling sour ces and priority order ..................................... 777 table 19.5 interrupt request sources and ipra?iprd regi sters ........................................... 781 table 19.6 interrupt request sources an d intpri00 register................................................ 783 table 19.7 bit allocatio n ......................................................................................................... 786 table 19.8 interrupt respon se time ........................................................................................ 790 section 20 user break controller (ubc) table 20.1 ubc register s........................................................................................................ 797 section 21 high-performance user debug interface (h-udi) table 21.1 h-udi pins............................................................................................................. 825 table 21.2 h-udi regist ers..................................................................................................... 826 table 21.3 structure of boundary scan regist er ..................................................................... 830 section 22 pci controller (pcic) table 22.1 pin configuration ................................................................................................... 849 table 22.2 list of pci configura tion register s ....................................................................... 851 table 22.3 pci configuration regist er configura tion............................................................ 852 table 22.4 list of pcic local registers.................................................................................. 853 table 22.5 list of class23 to 16 base cla ss codes (class23 to 16)................................. 864 table 22.6 memory space base address register (base0)................................................... 870 table 22.7 memory space base address register (base1)................................................... 872 table 22.8 operating modes .................................................................................................... 928 table 22.9 pci command supp ort .......................................................................................... 929 table 22.10 access size ............................................................................................................. 960 table 22.11 dma transfer access size and e ndian conversion mode ................................... 962 table 22.12 target transfer access size and endian conversion mode .................................. 963 table 22.13 interrupts ................................................................................................................ 969 table 22.14 method of stopping clock per operating mode .................................................... 974 section 23 electrical characteristics table 23.1 absolute maximum ratings................................................................................... 981 table 23.2 dc characteristics (hd6417751rbp240 (v), hd6417751rbg240 (v)) ............ 982 table 23.3 dc characteristics (hd6417751rbp200 (v), hd6417751rbg200 (v)) ............ 984 table 23.4 dc characteristics (hd6 417751rbp200 (v )) ...................................................... 986 table 23.5 dc characteristics (hd6 417751rf200 (v )) ......................................................... 988 table 23.6 dc characteristics (hd6 417751bp167 (v )) ......................................................... 990 table 23.7 dc characteristics (hd6 417751f167 (v ))............................................................ 992 table 23.8 permissible output currents................................................................................... 994 table 23.9 clock timing (hd6417751rbp240 (v ), hd6417751rbg240 (v)) .................... 994
rev.4.00 oct. 10, 2008 page xcvi of xcviii rej09b0370-0400 table 23.10 clock timing (hd6417 751rf240 (v ))................................................................. 994 table 23.11 clock timing (hd6417751rbp200 (v ), hd6417751rbg200 (v)) .................... 995 table 23.12 clock timing (hd6417 751rf200 (v ))................................................................. 995 table 23.13 clock timing (hd6417751bp167 (v ), hd6417751f167 (v))............................. 995 table 23.14 clock and control signal timing (hd6417751rbp24 0 (v), hd6417751rbg 240 (v)) ....................................... 996 table 23.15 clock and control signal timi ng (hd6417751rf240) .................................... 997 table 23.16 clock and control signal timing (hd6417751rbp20 0 (v), hd6417751rbg 200 (v)) ....................................... 998 table 23.17 clock and control signal timing (hd6417751rf200 (v)).............................. 999 table 23.18 clock and control signal timing (hd6417751bp16 7 (v), hd6417751f1 67 (v))................................................ 1000 table 23.19 control signal timi ng (1) .................................................................................. 1006 table 23.20 control signal timi ng (2) .................................................................................. 1007 table 23.21 bus timing (1) ................................................................................................... 1010 table 23.22 bus timing (2) ................................................................................................... 1012 table 23.23 peripheral module signal timing (1)................................................................. 1061 table 23.24 peripheral module signal timing (2)................................................................. 1063 table 23.25 pcic signal timing (in pcireq/pci gnt non-port mode) (1) ...................... 1069 table 23.26 pcic signal timing (in pcireq/pci gnt non-port mode) (2) ...................... 1070 table 23.27 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (1) ....................................................................................................................... 1072 table 23.28 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (2) ....................................................................................................................... 1072 appendix a address list table a.1 address li st ....................................................................................................... 1077 appendix c mode pin settings table c.1 clock operating mode s (sh7751) ..................................................................... 1089 table c.2 clock operating mode s (sh7751r ) .................................................................. 1090 table c.3 area 0 memory map an d bus width ................................................................. 1090 table c.4 endian ................................................................................................................ 1090 table c.5 master/sla ve....................................................................................................... 1091 table c.6 clock inpu t......................................................................................................... 1091 table c.7 pci mode ........................................................................................................... 1091
rev.4.00 oct. 10, 2008 page xcvii of xcviii rej09b0370-0400 appendix d pin functions table d.1 pin states in reset, power-down st ate, and bus-released state (pci enable, disa ble commo n) ......................................................................... 1093 table d.2 pin states in reset, power-down state, and bus-released state (pci enable). 1095 table d.3 pin states in reset, power-down state, and bus-released state (pci disable) 1097 table d.4 handling of pins when pci is not used ........................................................... 1099 appendix h product lineup table h.1 sh7751/sh7751r produc t lineup .................................................................... 1119 appendix i version registers table i.1 register confi guration ....................................................................................... 1121
rev.4.00 oct. 10, 2008 page xcviii of xcviii rej09b0370-0400
1. overview rev.4.00 oct. 10, 2008 page 1 of 1122 rej09b0370-0400 section 1 overview 1.1 sh7751/sh7751r group features the sh7751/sh7751r group microprocessor, featur ing a built-in pci bus controller compatible with pcs and multimedia devices. the superh ? * risc engine is a renesas original 32-bit risc (reduced instruction set comp uter) microcomputer. the superh ? risc engine employs a fixed- length 16-bit instruction set, allowing an approximately 50 % reduction in program size over a 32- bit instruction set. the sh7751/sh7751r group feature the sh-4 core, which at the object code level is upwardly compatible with the sh-1, sh-2, and sh-3 microcomputers. the sh7751/sh7751r group have an instruction cache, an operand cache that can be switched betw een copy-back and write-through modes, a 4-entry full-associative instruction tlb (table look aside buffer), and mmu (memory management unit) with 64-entry full-associative shared tlb. the sh7751/sh7751r group also feature a bus st ate controller (bsc) that can be coupled to dram (page/edo) and synchronous dram. also, because of its built-in functions, such as pci bus controller, timers, and serial communications functions, required for multimedia and oa equipment, use of the sh7751/sh7751r group enab le a dramatic reduction in system costs. the features of the sh7 751/sh7751r group are summarized in table 1.1. note: * superh is a trademark of renesas technology corp.
1. overview rev.4.00 oct. 10, 2008 page 2 of 1122 rej09b0370-0400 table 1.1 sh7751/sh7751r group features item features lsi ? superscalar architecture: parallel execution of two instructions ? external buses (sh buses) ? separate 26-bit address and 32-bit data buses ? external bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency ? external bus (pci bus): ? 32-bit address/data multiplexing ? selection of internal clock or external pci-dedicated clock cpu ? renesas technology original superh architecture ? 32-bit internal data bus ? general register file: ? sixteen 32-bit general registers (and eight 32-bit shadow registers) ? seven 32-bit control registers ? four 32-bit system registers ? risc-type instruction set (upwar d-compatible with superh series) ? fixed 16-bit instruction length for improved code efficiency ? load-store architecture ? delayed branch instructions ? conditional execution ? c-based instruction set ? superscalar architecture (providing simultaneous execution of two instructions) including fpu ? instruction execution time: maximum 2 instructions/cycle ? virtual address space: 4 gbytes ( 448-mbyte external memory space) ? space identifier asids: 8 bits , 256 virtual address spaces ? on-chip multiplier ? five-stage pipeline
1. overview rev.4.00 oct. 10, 2008 page 3 of 1122 rej09b0370-0400 item features fpu ? on-chip floating-point coprocessor ? supports single-precision (32 bits) and double-precision (64 bits) ? supports ieee754-compliant data types and exceptions ? two rounding modes: round to nearest and round to zero ? handling of denormalized numbers: truncation to zero or interrupt generation for compliance with ieee754 ? floating-point registers: 32 bits 16 2 banks (single-precision 32 bits 16 or double-precision 64 bits 8) 2 banks ? 32-bit cpu-fpu floating-point communication register (fpul) ? supports fmac (multiply- and-accumulate) instruction ? supports fdiv (divide) and fsqrt (square root) instructions ? supports fldi0/fldi1 (load c onstant 0/1) instructions ? instruction execution times ? latency (fmac/fadd/fsub/fmul): 3 cycles (single-precision), 8 cycles (double-precision) ? pitch (fmac/fadd/fsub/fmul): 1 cycl e (single-precision), 6 cycles (double-precision) note: fmac is supported for single-precision only. ? 3-d graphics instructions (single-precision only): ? 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles (latency) ? 4-dimensional vector inner product (fipr): 1 cycle (pitch), 4 cycles (latency)
1. overview rev.4.00 oct. 10, 2008 page 4 of 1122 rej09b0370-0400 item features clock pulse generator (cpg) ? choice of main clock ? sh7751: 1/2, 1, 3, or 6 times extal ? sh7751r: 1, 6, or 12 times extal ? clock modes: (maximum frequen cy: varies with models) ? cpu frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ? bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ? peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ? power-down modes ? sleep mode ? deep sleep mode ? pin sleep mode ? standby mode ? hardware standby mode ? module standby function ? single-channel watchdog timer memory management unit (mmu) ? 4-gbyte address space, 256 address s pace identifiers (8-bit asids) ? single virtual mode and multiple virtual memory mode ? supports multiple page sizes: 1 kb yte, 4 kbytes, 64 kbytes, 1 mbyte ? 4-entry fully-associative tlb for instructions ? 64-entry fully-associative tlb for instructions and operands ? supports software-controlled replacement and random-counter replacement algorithm ? tlb contents can be accessed directly by address mapping
1. overview rev.4.00 oct. 10, 2008 page 5 of 1122 rej09b0370-0400 item features cache memory [sh7751] ? instruction cache (ic) ? 8 kbytes, direct mapping ? 256 entries, 32-byte block length ? normal mode (8-kbyte cache) ? index mode ? operand cache (oc) ? 16 kbytes, direct mapping ? 512 entries, 32-byte block length ? normal mode (16-kbyte cache) ? index mode ? ram mode (8-kbyte cache + 8-kbyte ram) ? choice of write method (copy -back or write-through) ? single-stage copy-back buffer, single-stage write-through buffer ? cache memory contents can be accessed directly by address mapping (usable as on-chip memory) ? store queue (32 bytes 2 entries) cache memory [sh7751r] ? instruction cache (ic) ? 16 kbytes, 2-way set associative ? 256 entries/way, 32-byte block length ? cache-double-mode (16-kbyte cache) ? index mode ? sh7751-compatible mode (8 kbytes, direct mapping) ? operand cache (oc) ? 32 kbytes, 2-way set associative ? 512 entries/way, 32-byte block length ? cache-double-mode (32-kbyte cache) ? index mode ? ram mode (16-kbyte cache + 16-kbyte ram) ? choice of write method (copy -back or write-through) ? sh7751-compatible mode (16 kbytes, direct mapping) ? single-stage copy-back buffer, single-stage write-through buffer ? cache memory contents can be accessed directly by address mapping (usable as on-chip memory) ? store queue (32 bytes 2 entries)
1. overview rev.4.00 oct. 10, 2008 page 6 of 1122 rej09b0370-0400 item features interrupt controller (intc) ? five independent external interrupts (nmi, irl3 to irl0) ? 15-level signed external interrupts: irl3 to irl0 ? on-chip peripheral module interrupts: priority level can be set for each module user break controller (ubc) ? supports debugging by means of user break interrupts ? two break channels ? address, data value, access type, and data size can all be set as break conditions ? supports sequential break function bus state controller (bsc) ? supports external memory access ? 32/16/8-bit external data bus ? external memory space divided into seven areas, each of up to 64 mbytes, with the following parameters settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (hardware wait function also supported) ? direct connection of dram, synchronous dram, and burst rom possible by setting space type ? supports fast page mode and dram edo ? supports pcmcia interface ? chip select signals ( cs0 to cs6 ) output for relevant areas ? dram/synchronous dram refresh functions ? programmable refresh interval ? supports cas-before-ras refresh mode and self-refresh mode ? dram/synchronous dram burst access function ? big endian or little endian mode can be set
1. overview rev.4.00 oct. 10, 2008 page 7 of 1122 rej09b0370-0400 item features direct memory access controller (dmac) ? physical address dma controller ? sh7751: 4-channel ? sh7751r: 8-channel ? transfer data size: 8, 16, 32, or 64 bits, or 32 bytes ? address modes: ? single address mode ? dual address mode ? transfer requests: external, on-chip peripheral module, or auto-requests ? bus modes: cycle-steal or burst mode ? supports on-demand data transfer mode (external bus 32 bit) timer unit (tmu) ? 5-channel auto-reload 32-bit timer input-capture function on one channel ? selection from 7 counter input clocks in 3 of 5 channels and from 5 counter input clocks on remaining 2 of 5 channels realtime clock (rtc) ? on-chip clock and calendar functions ? built-in 32 khz crystal oscillation circuit with maximum 1/256 second resolution (cycle interrupts) serial communication interface (sci, scif) ? two full-duplex communication channels (sci, scif) ? channel 1 (sci): ? choice of asynchronous mode or synchronous mode ? supports smart card interface ? channel 2 (scif): ? supports asynchronous mode ? separate 16-byte fifos provided for transmitter and receiver
1. overview rev.4.00 oct. 10, 2008 page 8 of 1122 rej09b0370-0400 item features pci bus controller (pcic) ? pci bus controller (supports a subset of pci revision 2.1) * ? 32-bit bus ? 33 mhz/66 mhz support ? pci master/slave support ? pci host function support ? built-in bus arbiter ? 4 built-in pci-dedicated dmac (direct memory access controller) channels ? each channel equipped with 64-byte fifo ? selection of built-in clock or external pci-dedicated clock ? interrupt requests can be sent to cpu product lineup abbreviation voltage operating frequency model no. package sh7751 1.8 v 167 mhz hd6417751bp167 256-pin bga hd6417751f167 256-pin qfp sh7751r 1.5 v 240 mhz hd6417751rbp240 256-pin bga hd6417751rf240 256-pin qfp hd6417751rbg240 292-pin bga 200 mhz hd6417751rbp200 256-pin bga hd6417751rf200 256-pin qfp hd6417751rbg200 292-pin bga note: * some items are not compatible with pci 2.1. for more information, s ee section 22.1.1, features.
1. overview rev.4.00 oct. 10, 2008 page 9 of 1122 rej09b0370-0400 1.2 block diagram figure 1.1 shows an internal block diagram of the sh7751/sh7751r group. lower 32-bit data 64-bit data (store) cpg intc sci (scif) rtc tmu external (sh) bus interface dmac 32-bit data 29-bit address 32-bit data address 32-bit data 32-bit data upper 32-bit data 32-bit address (instructions) 32-bit data (instructions) 32-bit address (data) peripheral address bus 26-bit sh bus address 32-bit pci address/ data 32-bit sh bus data peripheral data bus ubc 32-bit data (store) 32-bit data (load) cpu i cache o cache itlb utlb cache and tlb controller fpu le g end: bsc: bus state controller cpg: clock pulse g enerator dmac: direct memory access controller fpu: floatin g -point unit intc: interrupt controller itlb: instruction tlb (translation lookaside buffer) utlb: unified tlb (translation lookaside buffer) rtc: realtime clock sci: serial communication interface scif: serial communication interface with fifo tmu: timer unit ubc: user break controller pcic: pci bus controller 32-bit data pcic bsc address (pci)dmac sh-4 core figure 1.1 block diagram of sh7751/sh7751r group functions
1. overview rev.4.00 oct. 10, 2008 page 10 of 1122 rej09b0370-0400 1.3 pin arrangement 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 xtal2 extal2 vdd-rtc vss-rtc ca reset trst mreset nmi back / bsreq breq / bsack md6/ iois16 rdy txd md2/rxd2 rxd tclk md8/ rts2 sck md1/txd2 md0/sck2 md7/ cts2 audsync audck audata0 audata1 audata2 audata3 reserved md3/ ce2a md4/ ce2b md5 dack0 dack1 drak0 drak1 status0 status1 dreq0 dreq1 asebrk /brkack tdo vdd-pll2 vss-pll2 vdd-pll1 vss-pll1 vdd-cpg vss-cpg xtal extal 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 serr pcireq1 / gntin pcignt1 / reqout pciclk pcirst inta idsel pcireq2 /md9 pcireq3 /md10 pcireq4 pcignt2 pcignt3 pcignt4 sleep we3 / iciowr we2 / iciord a25 a24 a23 a22 a21 a20 a19 a18 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 cas3 /dqm3 cas2 /dqm2 a17 a16 a15 a14 a13 a12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 tms tck tdi cs0 cs1 cs4 cs5 cs6 bs we0 / reg we1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 cas0 /dqm0 cas1 /dqm1 rd/ wr ckio reserved reserved rd / cass / frame cke ras cs2 cs3 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 irl3 irl2 irl1 irl0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 c/ be0 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 c/ be1 par perr pcilock pcistop devsel trdy irdy pciframe c/ be2 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 c/ be3 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 qfp256 (top view) vdd (internal) vss (internal) vddq (io) vssq (io) note: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. figure 1.2 pin arrangement (256-pin qfp)
1. overview rev.4.00 oct. 10, 2008 page 11 of 1122 rej09b0370-0400 a b c d e f g h 1234567891011121314151617 1920 18 j k l m n p r t u v w y extal vdd-pll2 vdd-pll1 tdo drak1 drak0 dack1 dack0 audata2 audata1 xtal audata0 audck tclk rxd txd audsync md1/txd2 md2/rxd2 md0/sck2 md6/ iois16 md8/ rts2 sck md7/ cts2 audata3 nc md5 md4/ ce2b md3/ ce2a tck tms tdi status0 status1 cs0 cs1 cs6 cs5 we1 dreq1 dreq0 rdy mreset trst nmi ca reset * breq / bsack back / bsreq asebrk / brkack we0 / reg cs4 bs d0 d7 d11 d14 cas0 /dqm0 cas1 /dqm1 cas2 /dqm2 cas3 /dqm3 nc nc cke rd/ wr d3 d1 d2 d4 d8 d6 d5 d12 d10 d9 d15 d13 ckio ras rd / cass / frame a0 a3 a7 a9 a13 a1 a5 a16 d17 d16 d19 d20 d18 d21 d29 a19 a12 a17 ad22 ad24 ad27 ad25 ad21 ad18 ad14 par ad10 ad4 ad1 ad29 ad28 ad30 ad31 ad20 ad23 ad17 ad19 ad26 a20 a21 a22 a24 ad16 ad12 ad13 ad9 ad6 ad7 ad2 ad5 ad3 ad0 xtal2 extal2 ad11 ad15 ad8 idsel c/ be3 c/ be1 c/ be0 trdy c/ be2 inta pcirst pciclk serr a25 we2 / iciord pcignt4 pcignt1 / reqout pcireq1 / gntin pcignt2 devsel perr irl0 irl2 irl1 irl3 pcilock pciframe pcistop irdy pcireq4 pcireq3 /md10 pcireq2 /md9 pcignt3 we3 / iciowr a23 sleep d22 d23 d24 d25 d30 d31 d26 d27 a18 d28 a15 a14 a6 a2 cs3 cs2 a4 a8 a10 a11 bga256 (top view) vddq(io) vssq(io) vdd (internal) vss (internal) nc vss-pll1/2 vdd-pll1/2 vdd-cpg/rtc vss-cpg/rtc notes: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd- pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. * may be connected to v ss q. figure 1.3 pin arrangement (256-pin bga)
1. overview rev.4.00 oct. 10, 2008 page 12 of 1122 rej09b0370-0400 a b c d e f g h 1234567891011121314151617 1920 18 j k l m n p r t u v w y bga292 (top view) vddq(io) vdd (internal) vss-pll1/2 vdd-pll1/2 vdd-cpg/rtc vss-cpg/rtc extal vdd-pll2 vdd-pll1 vss-cpg vdd-cpg vss-pll1 vss-pll2 vss-rtc vdd-rtc tck drak0 drak1 asebrk / brkack md5 dack0 audata1 md3/ ce2a audata0 xtal audata2 ca audsync md8/ rts2 md2/rxd2 md0/sck2 rxd audck md7/ cts2 txd mreset tclk sck md1/txd2 md4/ ce2b dack1 audata3 tdo dreq0 status1 tms cs0 cs4 cs5 we0 / reg dreq1 status0 md6/ iois16 back / bsreq breq / bsack trst reset rdy nmi tdi cs1 bs d5 d8 d11 d14 a17 cas1 /dqm1 cke rd/ wr we1 cs6 d1 ad6 d2 c/ be0 d4 d6 d7 d9 d10 d12 c/ be1 cas0 / dqm0 ckio rd / cass / frame cs3 a3 a6 a9 a14 cas3 /dqm3 d17 d23 d18 d21 d19 d16 d22 d27 a18 a24 a13 cas2 /dqm2 a12 d20 ad19 a0 ad23 ad24 ad22 ad17 cs2 ras ad13 par ad10 ad3 ad0 ad27 ad28 ad30 ad31 ad21 c/ be3 ad16 ad18 ad26 a23 a22 pciframe ad12 ad8 d3 ad7 ad5 d0 ad1 ad4 ad2 irl0 xtal2 extal2 ad11 ad14 ad9 ad25 ad15 devsel c/ be2 pcirst inta pcignt3 idsel vss serr we2 / iciord a25 ad29 pcignt2 pcireq1 / gntin pcignt1 / reqout irl2 irl1 irl3 pcilock d15 d13 irdy pcistop perr trdy pcireq2 /md9 pcireq3 /md10 pcireq4 pcignt4 a21 pciclk we3 / iciowr sleep d26 d25 d24 d31 d30 d29 a20 d28 a19 a15 a16 a7 a4 a1 ad20 a2 a5 a8 a10 a11 note: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. figure 1.4 pin arrangement (292-pin bga)
1. overview rev.4.00 oct. 10, 2008 page 13 of 1122 rej09b0370-0400 1.4 pin functions 1.4.1 pin functions (256-pin qfp) table 1.2 pin functions memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 1 tms i mode (h-udi) 2 tck i clock (h-udi) 3 vddq power io vdd 4 vssq power io gnd 5 tdi i data in (h-udi) 6 cs0 o chip select 0 cs0 cs0 7 cs1 o chip select 1 cs1 cs1 8 cs4 o chip select 4 cs4 cs4 9 cs5 o chip select 5 cs5 ce1a cs5 10 cs6 o chip select 6 cs6 ce1b cs6 11 bs o bus start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 12 we0 / reg o d7?d0 select signal we0 reg 13 we1 o d15-d8 select signal we1 we1 14 d0 i/o data a0 15 vddq power io vdd 16 vssq power io gnd 17 vdd power internal vdd 18 vss power internal gnd 19 d1 i/o data a1 20 d2 i/o data a2 21 d3 i/o data a3 22 d4 i/o data a4 23 d5 i/o data a5 24 d6 i/o data a6 25 d7 i/o data a7
1. overview rev.4.00 oct. 10, 2008 page 14 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 26 d8 i/o data a8 27 d9 i/o data a9 28 d10 i/o data a10 29 vddq power io vdd 30 vssq power io gnd 31 d11 i/o data a11 32 d12 i/o data a12 33 d13 i/o data a13 34 d14 i/o data a14 35 d15 i/o data a15 36 cas0 / dqm0 o d7?d0 select signal cas0 dqm0 37 cas1 / dqm1 o d15?d8 select signal cas1 dqm1 38 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 39 ckio o clock output ckio ckio ckio ckio 40 reserved do not connect 41 vddq power io vdd 42 vssq power io gnd 43 reserved do not connect 44 rd / cass / frame o read/ cas / frame oe cas oe frame 45 cke o clock output enable cke 46 ras o ras ras ras 47 vdd power internal vdd 48 vss power internal gnd 49 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 50 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 51 a0 o address 52 a1 o address 53 a2 o address 54 a3 o address 55 vddq power io vdd
1. overview rev.4.00 oct. 10, 2008 page 15 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 56 vssq power io gnd 57 a4 o address 58 a5 o address 59 a6 o address 60 a7 o address 61 a8 o address 62 a9 o address 63 a10 o address 64 a11 o address 65 a12 o address 66 a13 o address 67 vddq power io vdd 68 vssq power io gnd 69 a14 o address 70 a15 o address 71 a16 o address 72 a17 o address 73 cas2 / dqm2 o d23?d16 select signal cas2 dqm2 74 cas3 / dqm3 o d31?d24 select signal cas3 dqm3 75 d16 i/o data a16 76 d17 i/o data a17 77 d18 i/o data a18 78 d19 i/o data a19 79 vddq power io vdd 80 vssq power io gnd 81 vdd power internal vdd 82 vss power internal gnd 83 d20 i/o data a20 84 d21 i/o data a21 85 d22 i/o data a22 86 d23 i/o data a23
1. overview rev.4.00 oct. 10, 2008 page 16 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 87 d24 i/o data a24 88 d25 i/o data a25 89 d26 i/o data 90 d27 i/o data 91 d28 i/o data 92 d29 i/o data accsize0 93 vddq power io vdd 94 vssq power io gnd 95 d30 i/o data accsize1 96 d31 i/o data accsize2 97 vdd power internal vdd 98 vss power internal gnd 99 a18 o address 100 a19 o address 101 a20 o address 102 a21 o address 103 a22 o address 104 a23 o address 105 vddq power io vdd 106 vssq power io gnd 107 a24 o address 108 a25 o address 109 we2 / iciord o d23?d16 select signal we2 iciord 110 we3 / iciowr o d31?d24 select signal we3 iciowr 111 vdd power internal vdd 112 vss power internal gnd 113 sleep i sleep 114 pcignt4 o bus grant (host function) 115 pcignt3 o bus grant (host function)
1. overview rev.4.00 oct. 10, 2008 page 17 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 116 pcignt2 o bus grant (host function) 117 pcireq4 i * bus request (host function) 118 pcireq3 / md10 i * bus request (host function)/ mode md10 119 vddq power io vdd 120 vssq power io gnd 121 pcireq2 / md9 i * bus request (host function)/ mode md9 122 idsel i configuration device select 123 inta o interrupt (async) 124 pcirst o reset output 125 pciclk i pci input clock 126 pcignt1 / reqout o bus grant (host function)/ bus request 127 pcireq1 / gntin i bus request (host function) /bus grant 128 serr i/o system error 129 ad31 i/o pci address/ data/port (port) (port) (port) (port) (port) 130 ad30 i/o pci address/ data/port (port) (port) (port) (port) (port) 131 vddq power io vdd 132 vssq power io gnd 133 ad29 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 18 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 134 ad28 i/o pci address/ data/port (port) (port) (port) (port) (port) 135 ad27 i/o pci address/ data/port (port) (port) (port) (port) (port) 136 ad26 i/o pci address/ data/port (port) (port) (port) (port) (port) 137 ad25 i/o pci address/ data/port (port) (port) (port) (port) (port) 138 ad24 i/o pci address/ data/port (port) (port) (port) (port) (port) 139 c/ be3 i/o command/byte enable 140 ad23 i/o pci address/ data/port (port) (port) (port) (port) (port) 141 ad22 i/o pci address/ data/port (port) (port) (port) (port) (port) 142 ad21 i/o pci address/ data/port (port) (port) (port) (port) (port) 143 vddq power io vdd 144 vssq power io gnd 145 vdd power internal vdd 146 vss power internal gnd 147 ad20 i/o pci address/ data/port (port) (port) (port) (port) (port) 148 ad19 i/o pci address/ data/port (port) (port) (port) (port) (port) 149 ad18 i/o pci address/ data/port (port) (port) (port) (port) (port) 150 ad17 i/o pci address/ data/port (port) (port) (port) (port) (port) 151 ad16 i/o pci address/ data/port (port) (port) (port) (port) (port) 152 c/ be2 i/o command/ byte enable 153 pciframe i/o bus cycle 154 irdy i/o initiator ready 155 trdy i/o target ready
1. overview rev.4.00 oct. 10, 2008 page 19 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 156 devsel i/o device select 157 vddq power io vdd 158 vssq power io gnd 159 pcistop i/o transaction stop 160 pcilock i/o exclusive access 161 perr i/o parity error 162 par i/o parity 163 c/ be1 i/o command/ byte enable 164 ad15 i/o pci address/ data/port (port) (port) (port) (port) (port) 165 ad14 i/o pci address/ data/port (port) (port) (port) (port) (port) 166 ad13 i/o pci address/ data/port (port) (port) (port) (port) (port) 167 ad12 i/o pci address/ data/port (port) (port) (port) (port) (port) 168 ad11 i/o pci address/ data/port (port) (port) (port) (port) (port) 169 vddq power io vdd 170 vssq power io gnd 171 ad10 i/o pci address/ data/port (port) (port) (port) (port) (port) 172 ad9 i/o pci address/ data/port (port) (port) (port) (port) (port) 173 ad8 i/o pci address/ data/port (port) (port) (port) (port) (port) 174 c/ be0 i/o command/ byte enable 175 vdd power internal vdd 176 vss power internal gnd 177 ad7 i/o pci address/ data/port (port) (port) (port) (port) (port) 178 ad6 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 20 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 179 ad5 i/o pci address/ data/port (port) (port) (port) (port) (port) 180 ad4 i/o pci address/ data/port (port) (port) (port) (port) (port) 181 ad3 i/o pci address/ data/port (port) (port) (port) (port) (port) 182 ad2 i/o pci address/ data/port (port) (port) (port) (port) (port) 183 vddq power i/o vdd 184 vssq power i/o gnd 185 ad1 i/o pci address/ data/port (port) (port) (port) (port) (port) 186 ad0 i/o pci address/ data/port (port) (port) (port) (port) (port) 187 irl0 i interrupt 0 188 irl1 i interrupt 1 189 irl2 i interrupt 2 190 irl3 i interrupt 3 191 vssq power i/o gnd 192 vddq power i/o vdd 193 xtal2 o rtc crystal resonator pin 194 extal2 i rtc crystal resonator pin 195 vdd-rtc power rtc vdd 196 vss-rtc power rtc gnd 197 ca * 2 i hardware standby 198 reset i reset reset 199 trst i reset (h-udi) 200 mreset i manual reset 201 nmi i nonmaskable interrupt
1. overview rev.4.00 oct. 10, 2008 page 21 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 202 back / bsreq o bus acknowledge/ bus request 203 breq / bsack i bus request/bus acknowledge 204 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 205 rdy i bus ready rdy rdy rdy 206 txd o sci data output 207 vddq power io vdd 208 vssq power io gnd 209 vdd power internal vdd 210 vss power internal gnd 211 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 212 rxd i sci data input 213 tclk i/o rtc/tmu clock 214 md8/ rts2 i/o mode/scif data control (rts) md8 rts2 rts2 rts2 rts2 rts2 215 sck i/o scif clock 216 md1/txd2 i/o mode/scif data output md1 txd2 txd2 txd2 txd2 txd2 217 md0/sck2 i/o mode/scif clock md0 sck2 sck2 sck2 sck2 sck2 218 md7/ cts2 i/o mode/scif data control (cts) md7 cts2 cts2 cts2 cts2 cts2 219 audsync aud sync 220 audck aud clock 221 vddq power io vdd 222 vssq power io gnd 223 audata0 aud data 224 audata1 aud data
1. overview rev.4.00 oct. 10, 2008 page 22 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 225 vdd power internal vdd 226 vss power internal gnd 227 audata2 aud data 228 audata3 aud data 229 reserved do not connect 230 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 231 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 232 md5 i mode md5 233 vddq power io vdd 234 vssq power io gnd 235 dack0 o dmac0 bus acknowledge 236 dack1 o dmac1 bus acknowledge 237 drak0 o dmac0 request acknowledge 238 drak1 o dmac1 request acknowledge 239 vdd power internal vdd 240 vss power internal gnd 241 status0 o status 242 status1 o status 243 dreq0 i request from dmac0 244 dreq1 i request from dmac1 245 asebrk / brkack i/o pin break/ acknowledge (h-udi) 246 tdo o data out (h-udi)
1. overview rev.4.00 oct. 10, 2008 page 23 of 1122 rej09b0370-0400 memory interface no. pin name i/o function reset sram dram sdram pcmcia mpx 247 vddq power io vdd 248 vssq power io gnd 249 vdd-pll2 power pll2 vdd 250 vss-pll2 power pll2 gnd 251 vdd-pll1 power pll1 vdd 252 vss-pll1 power pll1 gnd 253 vdd-cpg power cpg vdd 254 vss-cpg power cpg gnd 255 xtal o crystal resonator 256 extal i external input clock/crystal resonator legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. however, on the sh7751 in hardware standby mode, supply power to rtc at the minimum. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. for the handling of the pci bus pins in pci- disabled mode, see table d.4 in appendix d. * i/o attribute is i/o when used as a port.
1. overview rev.4.00 oct. 10, 2008 page 24 of 1122 rej09b0370-0400 1.4.2 pin functions (256-pin bga) table 1.3 pin functions memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 1 b3 tms i mode (h-udi) 2 c4 tck i clock (h-udi) 3 g3 vddq power io vdd 4 f2 vssq power io gnd 5 d4 tdi i data in (h-udi) 6 b1 cs0 o chip select 0 cs0 cs0 7 c2 cs1 o chip select 1 cs1 cs1 8 c1 cs4 o chip select 4 cs4 cs4 9 d3 cs5 o chip select 5 cs5 ce1a cs5 10 d2 cs6 o chip select 6 cs6 ce1b cs6 11 d1 bs o bus start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 12 e4 we0 / reg o d7?d0 select signal we0 reg 13 e3 we1 o d15?d8 select signal we1 we1 14 e2 d0 i/o data a0 15 g2 vddq power io vdd 16 l4 vssq power io gnd 17 g4 vdd power internal vdd 18 f4 vss power internal gnd 19 e1 d1 i/o data a1 20 f3 d2 i/o data a2 21 f1 d3 i/o data a3 22 g1 d4 i/o data a4 23 h4 d5 i/o data a5 24 h3 d6 i/o data a6 25 h2 d7 i/o data a7 26 h1 d8 i/o data a8
1. overview rev.4.00 oct. 10, 2008 page 25 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 27 j4 d9 i/o data a9 28 j3 d10 i/o data a10 29 k3 vddq power io vdd 30 l3 vssq power io gnd 31 j2 d11 i/o data a11 32 j1 d12 i/o data a12 33 k4 d13 i/o data a13 34 k2 d14 i/o data a14 35 k1 d15 i/o data a15 36 l2 cas0 / dqm0 o d7?d0 select signal cas0 dqm0 37 m4 cas1 / dqm1 o d15?d8 select signal cas1 dqm1 38 m3 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 39 m1 ckio o clock output ckio ckio ckio ckio 40 m2 nc do not connect 41 p3 vddq power io vdd 42 l1 vssq power io gnd 43 n3 nc do not connect 44 p1 rd / cass / frame o read/ cas / frame oe cas oe frame 45 n2 cke o clock output enable cke 46 n1 ras o ras ras ras 47 p4 vdd power internal vdd 48 r4 vss power internal gnd 49 n4 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 50 r3 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 51 r1 a0 o address 52 t4 a1 o address 53 t3 a2 o address 54 t2 a3 o address 55 p2 vddq power io vdd
1. overview rev.4.00 oct. 10, 2008 page 26 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 56 r2 vssq power io gnd 57 t1 a4 o address 58 u4 a5 o address 59 u3 a6 o address 60 u2 a7 o address 61 u1 a8 o address 62 v2 a9 o address 63 v1 a10 o address 64 w1 a11 o address 65 y1 a12 o address 66 y2 a13 o address 67 v7 vddq power io vdd 68 v3 vssq power io gnd 69 w3 a14 o address 70 y3 a15 o address 71 v4 a16 o address 72 w4 a17 o address 73 y4 cas2 / dqm2 o d23?d16 select signal cas2 dqm2 74 u5 cas3 / dqm3 o d31?d24 select signal cas3 dqm3 75 v5 d16 i/o data a16 76 w5 d17 i/o data a17 77 y5 d18 i/o data a18 78 v6 d19 i/o data a19 79 w7 vddq power io vdd 80 w2 vssq power io gnd 81 u7 vdd power internal vdd 82 u6 vss power internal gnd 83 y6 d20 i/o data a20 84 y7 d21 i/o data a21 85 u8 d22 i/o data a22 86 v8 d23 i/o data a23
1. overview rev.4.00 oct. 10, 2008 page 27 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 87 w8 d24 i/o data a24 88 y8 d25 i/o data a25 89 u9 d26 i/o data 90 v9 d27 i/o data 91 w9 d28 i/o data 92 y9 d29 i/o data accsize0 93 v10 vddq power io vdd 94 w6 vssq power io gnd 95 w10 d30 i/o data accsize1 96 y10 d31 i/o data accsize2 97 u10 vdd power internal vdd 98 u11 vss power internal gnd 99 v11 a18 o address 100 y11 a19 o address 101 u12 a20 o address 102 v12 a21 o address 103 w12 a22 o address 104 y12 a23 o address 105 v14 vddq power io vdd 106 w11 vssq power io gnd 107 u13 a24 o address 108 v13 a25 o address 109 w13 we2 / iciord o d23?d16 select signal we2 iciord 110 y13 we3 / iciowr o d31?d24 select signal we3 iciowr 111 u14 vdd power internal vdd 112 u15 vss power internal gnd 113 y14 sleep i sleep 114 v15 pcignt4 o bus grant (host function) 115 y15 pcignt3 o bus grant (host function)
1. overview rev.4.00 oct. 10, 2008 page 28 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 116 u16 pcignt2 o bus grant (host function) 117 v16 pcireq4 i * 1 bus request (host function) 118 w16 pcireq3 / md10 i * 1 bus request (host function)/ mode md10 119 w14 vddq power io vdd 120 w15 vssq power io gnd 121 y16 pcireq2 / md9 i * 1 bus request (host function)/ mode md9 122 u17 idsel i configuration device select 123 v17 inta o interrupt (async) 124 w17 pcirst o reset output 125 y17 pciclk i pci input clock 126 w18 pcignt1 / reqout o bus grant (host function)/ bus request 127 y18 pcireq1 / gntin i bus request (host function)/ bus grant 128 y19 serr i/o system error 129 y20 ad31 i/o pci address/ data/port (port) (port) (port) (port) (port) 130 w20 ad30 i/o pci address/ data/port (port) (port) (port) (port) (port) 131 p18 vddq power io vdd 132 v18 vssq power io gnd 133 v19 ad29 i/o pci address/ data/port (port) (port) (port) (port) (port) 134 v20 ad28 i/o pci address/ data/port (port) (port) (port) (port) (port) 135 u18 ad27 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 29 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 136 u20 ad26 i/o pci address/ data/port (port) (port) (port) (port) (port) 137 t17 ad25 i/o pci address/ data/port (port) (port) (port) (port) (port) 138 t18 ad24 i/o pci address/ data/port (port) (port) (port) (port) (port) 139 u19 c/ be3 i/o pci address/ data/port 140 t20 ad23 i/o pci address/ data/port (port) (port) (port) (port) (port) 141 r18 ad22 i/o pci address/ data/port (port) (port) (port) (port) (port) 142 t19 ad21 i/o pci address/ data/port (port) (port) (port) (port) (port) 143 n19 vddq power io vdd 144 w19 vssq power io gnd 145 p17 vdd power internal vdd 146 r17 vss power internal gnd 147 r20 ad20 i/o pci address/ data/port (port) (port) (port) (port) (port) 148 p20 ad19 i/o pci address/ data/port (port) (port) (port) (port) (port) 149 p19 ad18 i/o pci address/ data/port (port) (port) (port) (port) (port) 150 n20 ad17 i/o pci address/ data/port (port) (port) (port) (port) (port) 151 n17 ad16 i/o pci address/ data/port (port) (port) (port) (port) (port) 152 n18 c/ be2 i/o command/ byte enable 153 m20 pciframe i/o bus cycle 154 m19 irdy i/o initiator ready 155 m18 trdy i/o target ready 156 m17 devsel i/o device select 157 l18 vddq power io vdd
1. overview rev.4.00 oct. 10, 2008 page 30 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 158 r19 vssq power io gnd 159 l20 pcistop i/o transaction stop 160 l19 pcilock i/o exclusive access 161 l17 perr i/o parity error 162 k20 par i/o parity 163 k18 c/ be1 i/o command/ byte enable 164 j20 ad15 i/o pci address/ data/port (port) (port) (port) (port) (port) 165 j19 ad14 i/o pci address/ data/port (port) (port) (port) (port) (port) 166 j18 ad13 i/o pci address/ data/port (port) (port) (port) (port) (port) 167 j17 ad12 i/o pci address/ data/port (port) (port) (port) (port) (port) 168 h20 ad11 i/o pci address/ data/port (port) (port) (port) (port) (port) 169 g18 vddq power io vdd 170 k17 vssq power io gnd 171 h19 ad10 i/o pci address/ data/port (port) (port) (port) (port) (port) 172 g20 ad9 i/o pci address/ data/port (port) (port) (port) (port) (port) 173 h18 ad8 i/o pci address/ data/port (port) (port) (port) (port) (port) 174 h17 c/ be0 i/o command/ byte enable 175 g17 vdd power internal vdd 176 f17 vss power internal gnd 177 f18 ad7 i/o pci address/ data/port (port) (port) (port) (port) (port) 178 f20 ad6 i/o pci address/ data/port (port) (port) (port) (port) (port) 179 e20 ad5 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 31 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 180 e19 ad4 i/o pci address/ data/port (port) (port) (port) (port) (port) 181 e18 ad3 i/o pci address/ data/port (port) (port) (port) (port) (port) 182 d20 ad2 i/o pci address/ data/port (port) (port) (port) (port) (port) 183 g19 vddq power i/o vdd 184 k19 vssq power i/o gnd 185 d19 ad1 i/o pci address/ data/port (port) (port) (port) (port) (port) 186 d18 ad0 i/o pci address/ data/port (port) (port) (port) (port) (port) 187 e17 irl0 i interrupt 0 188 c20 irl1 i interrupt 1 189 c19 irl2 i interrupt 2 190 b20 irl3 i interrupt 3 191 b18 nc do not connect * 2 192 d17 vddq power i/o vdd 193 a20 xtal2 o rtc crystal resonator pin 194 a19 extal2 i rtc crystal resonator pin 195 a18 vdd-rtc power rtc vdd 196 b19 vss-rtc power rtc gnd 197 b17 ca i hardware standby 198 a17 reset i reset reset 199 c16 trst i reset (h-udi) 200 b16 mreset i manual reset 201 d16 nmi i nonmaskable interrupt 202 a16 back / bsreq o bus acknowledge/ bus request
1. overview rev.4.00 oct. 10, 2008 page 32 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 203 b15 breq / bsack i bus request/bus acknowledge 204 c15 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 205 a15 rdy i bus ready rdy rdy rdy 206 a14 txd o sci data output 207 b14 vddq power io vdd 208 f19 vssq power io gnd 209 d14 vdd power internal vdd 210 d15 vss power internal gnd 211 d13 md2/ rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 212 c13 rxd i sci data input 213 b13 tclk i/o rtc/tmu clock 214 a13 md8/ rts2 i/o mode/scif data control (rts) md8 rts2 rts2 rts2 rts2 rts2 215 d12 sck i/o scif clock 216 b11 md1/ txd2 i/o mode/scif data output md1 txd2 txd2 txd2 txd2 txd2 217 c12 md0/ sck2 i/o mode/scif clock md0 sck2 sck2 sck2 sck2 sck2 218 a12 md7/ cts2 i/o mode/scif data control (cts) md7 cts2 cts2 cts2 cts2 cts2 219 b12 audsync aud sync 220 a11 audck aud clock 221 c14 vddq power io vdd 222 c18 vssq power io gnd 223 c10 audata0 aud data 224 a10 audata1 aud data 225 d11 vdd power internal vdd 226 d10 vss power internal gnd
1. overview rev.4.00 oct. 10, 2008 page 33 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 227 b9 audata2 aud data 228 d9 audata3 aud data 229 c9 nc do not connect 230 a9 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 231 d8 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 232 c8 md5 i mode md5 233 c11 vddq power io vdd 234 c17 vssq power io gnd 235 b8 dack0 o dmac0 bus acknowledge 236 a8 dack1 o dmac1 bus acknowledge 237 b7 drak0 o dmac0 request acknowledge 238 a7 drak1 o dmac1 request acknowledge 239 d7 vdd power internal vdd 240 d6 vss power internal gnd 241 c6 status0 o status 242 b6 status1 o status 243 a6 dreq0 i request from dmac0 244 c5 dreq1 i request from dmac1 245 d5 asebrk / brkack i/o pin break/ acknowledge (h-udi) 246 b4 tdo o data out (h-udi) 247 c7 vddq power io vdd 248 b10 vssq power io gnd 249 a5 vdd-pll2 power pll2 vdd
1. overview rev.4.00 oct. 10, 2008 page 34 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 250 b5 vss-pll2 power pll2 gnd 251 a4 vdd-pll1 power pll1 vdd 252 c3 vss-pll1 power pll1 gnd 253 a3 vdd-cpg power cpg vdd 254 b2 vss-cpg power cpg gnd 255 a2 xtal o crystal resonator 256 a1 extal i external input clock/crystal resonator legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. however, on the sh7751 in hardware standby mode, supply power to rtc at the minimum. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. for the handling of the pci bus pins in pci- disabled mode, see table d.4 in appendix d. 1. i/o attribute is i/o when used as a port. 2. may be connected to v ss q.
1. overview rev.4.00 oct. 10, 2008 page 35 of 1122 rej09b0370-0400 1.4.3 pin functions (292-pin bga) table 1.4 pin functions memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 1 b1 tms i mode (h-udi) 2 b2 tck i clock (h-udi) 3 f4 vddq power io vdd 4 e4 vss power gnd 5 c1 tdi i data in (h-udi) 6 c2 cs0 o chip select 0 cs0 cs0 7 d1 cs1 o chip select 1 cs1 cs1 8 d2 cs4 o chip select 4 cs4 cs4 9 d3 cs5 o chip select 5 cs5 ce1a cs5 10 e1 cs6 o chip select 6 cs6 ce1b cs6 11 e2 bs o bus start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 12 e3 we0 / reg o d7?d0 select signal we0 reg 13 f1 we1 o d15?d8 select signal we1 we1 14 f2 d0 i/o data a0 15 g3 vddq power io vdd 16 d4 vss power gnd 17 g4 vdd power internal vdd 18 h4 vss power gnd 19 f3 d1 i/o data a1 20 g1 d2 i/o data a2 21 g2 d3 i/o data a3 22 h1 d4 i/o data a4 23 h2 d5 i/o data a5 24 h3 d6 i/o data a6 25 j1 d7 i/o data a7 26 j2 d8 i/o data a8
1. overview rev.4.00 oct. 10, 2008 page 36 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 27 j3 d9 i/o data a9 28 k1 d10 i/o data a10 29 j4 vddq power io vdd 30 d5 vss power gnd 31 k2 d11 i/o data a11 32 k3 d12 i/o data a12 33 l1 d13 i/o data a13 34 l2 d14 i/o data a14 35 l3 d15 i/o data a15 36 m1 cas0 / dqm0 o d7?d0 select signal cas0 dqm0 37 m2 cas1 / dqm1 o d15?d8 select signal cas1 dqm1 38 m3 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 39 n1 ckio o clock output ckio ckio ckio ckio ckio 40 k4 vdd power internal vdd 41 r4 vddq power io vdd 42 l4 vss power io gnd 43 m4 vddq power i/o vdd 44 n2 rd / cass / frame o read/ cas / frame oe cas oe frame 45 n3 cke o clock output enable cke 46 p1 ras o ras ras ras 47 p4 vdd power internal vdd 48 n4 vss power gnd 49 p2 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 50 r1 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 51 r2 a0 o address 52 r3 a1 o address 53 t1 a2 o address 54 t2 a3 o address 55 p3 vddq power io vdd 56 t4 vss power gnd 57 t3 a4 o address
1. overview rev.4.00 oct. 10, 2008 page 37 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 58 u1 a5 o address 59 u2 a6 o address 60 u3 a7 o address 61 v1 a8 o address 62 v2 a9 o address 63 v3 a10 o address 64 w1 a11 o address 65 w2 a12 o address 66 y1 a13 o address 67 v7 vddq power io vdd 68 u4 vss power gnd 69 y2 a14 o address 70 y3 a15 o address 71 w3 a16 o address 72 y4 a17 o address 73 w4 cas2 / dqm2 o d23?d16 select signal cas2 dqm2 74 v4 cas3 / dqm3 o d31?d24 select signal cas3 dqm3 75 y5 d16 i/o data a16 76 w5 d17 i/o data a17 77 v5 d18 i/o data a18 78 y6 d19 i/o data a19 79 u6 vddq power io vdd 80 u5 vss power gnd 81 u7 vdd power internal vdd 82 u8 vss power gnd 83 w6 d20 i/o data a20 84 v6 d21 i/o data a21 85 y7 d22 i/o data a22 86 w7 d23 i/o data a23 87 y8 d24 i/o data a24 88 w8 d25 i/o data a25 89 v8 d26 i/o data
1. overview rev.4.00 oct. 10, 2008 page 38 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 90 y9 d27 i/o data 91 w9 d28 i/o data 92 v9 d29 i/o data accsize0 93 u9 vddq power io vdd 94 v10 vss power gnd 95 y10 d30 i/o data accsize1 96 w10 d31 i/o data accsize2 97 u10 vdd power internal vdd 98 u11 vss power gnd 99 y11 a18 o address 100 w11 a19 o address 101 v11 a20 o address 102 y12 a21 o address 103 w12 a22 o address 104 v12 a23 o address 105 u15 vddq power io vdd 106 u17 vss power gnd 107 y13 a24 o address 108 w13 a25 o address 109 v13 we2 / iciord o d23?d16 select signal we2 iciord 110 y14 we3 / iciowr o d31?d24 select signal we3 iciowr 111 u14 vdd power internal vdd 112 u13 vss power gnd 113 w14 sleep i sleep 114 y15 pcignt4 o bus grant (host function) 115 w15 pcignt3 o bus grant (host function) 116 v15 pcignt2 o bus grant (host function) 117 y16 pcireq4 i * bus grant (host function) 118 w16 pcireq3 / md10 i * bus request (host function)/ mode md10
1. overview rev.4.00 oct. 10, 2008 page 39 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 119 v14 vddq power io vdd 120 u16 vss power gnd 121 v16 pcireq2 / md9 i * bus request (host function)/ mode md9 122 y17 idsel i configuration device select 123 w17 inta o interrupt (async) 124 v17 pcirst o reset output 125 y18 pciclk i pci input clock 126 w18 pcignt1 / reqout o bus grant (host function)/ bus request 127 v18 pcireq1 / gntin i bus grant (host function)/ bus request 128 y19 serr i/o system error 129 y20 ad31 i/o pci address/ data/port (port) (port) (port) (port) (port) 130 w20 ad30 i/o pci address/ data/port (port) (port) (port) (port) (port) 131 r17 vddq power io vdd 132 t17 vss power gnd 133 w19 ad29 i/o pci address/ data/port (port) (port) (port) (port) (port) 134 v20 ad28 i/o pci address/ data/port (port) (port) (port) (port) (port) 135 v19 ad27 i/o pci address/ data/port (port) (port) (port) (port) (port) 136 u20 ad26 i/o pci address/ data/port (port) (port) (port) (port) (port) 137 u19 ad25 i/o pci address/ data/port (port) (port) (port) (port) (port) 138 u18 ad24 i/o pci address/ data/port (port) (port) (port) (port) (port) 139 t20 c/ be3 i/o pci address/ data/port
1. overview rev.4.00 oct. 10, 2008 page 40 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 140 t18 ad23 i/o pci address/ data/port (port) (port) (port) (port) (port) 141 t19 ad22 i/o pci address/ data/port (port) (port) (port) (port) (port) 142 r20 ad21 i/o pci address/ data/port (port) (port) (port) (port) (port) 143 p18 vddq power io vdd 144 u12 vddq power i/o vdd 145 p17 vdd power internal vdd 146 n17 vss power gnd 147 r19 ad20 i/o pci address/ data/port (port) (port) (port) (port) (port) 148 r18 ad19 i/o pci address/ data/port (port) (port) (port) (port) (port) 149 p20 ad18 i/o pci address/ data/port (port) (port) (port) (port) (port) 150 p19 ad17 i/o pci address/ data/port (port) (port) (port) (port) (port) 151 n20 ad16 i/o pci address/ data/port (port) (port) (port) (port) (port) 152 n18 c/ be2 i/o command/ byte enable 153 n19 pciframe i/o bus cycle 154 m20 irdy i/o initiator ready 155 m19 trdy i/o target ready 156 m18 devsel i/o device select 157 m17 vddq power io vdd 158 l17 vdd power internal vdd 159 l20 pcistop i/o transaction stop 160 l19 pcilock i/o exclusive access 161 l18 perr i/o parity error 162 k20 par i/o parity 163 k19 c/ be1 i/o command/ byte enable 164 k18 ad15 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 41 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 165 j20 ad14 i/o pci address/ data/port (port) (port) (port) (port) (port) 166 j19 ad13 i/o pci address/ data/port (port) (port) (port) (port) (port) 167 j18 ad12 i/o pci address/ data/port (port) (port) (port) (port) (port) 168 h20 ad11 i/o pci address/ data/port (port) (port) (port) (port) (port) 169 f17 vddq power io vdd 170 k17 vss power gnd 171 h19 ad10 i/o pci address/ data/port (port) (port) (port) (port) (port) 172 h18 ad9 i/o pci address/ data/port (port) (port) (port) (port) (port) 173 g20 ad8 i/o pci address/ data/port (port) (port) (port) (port) (port) 174 g19 c/ be0 i/o command/ byte enable 175 g17 vdd power internal vdd 176 h17 vss power gnd 177 f20 ad7 i/o pci address/ data/port (port) (port) (port) (port) (port) 178 f19 ad6 i/o pci address/ data/port (port) (port) (port) (port) (port) 179 f18 ad5 i/o pci address/ data/port (port) (port) (port) (port) (port) 180 e20 ad4 i/o pci address/ data/port (port) (port) (port) (port) (port) 181 e19 ad3 i/o pci address/ data/port (port) (port) (port) (port) (port) 182 e18 ad2 i/o pci address/ data/port (port) (port) (port) (port) (port) 183 g18 vddq power i/o vdd 184 j17 vddq power i/o vdd 185 d20 ad1 i/o pci address/ data/port (port) (port) (port) (port) (port) 186 d19 ad0 i/o pci address/ data/port (port) (port) (port) (port) (port)
1. overview rev.4.00 oct. 10, 2008 page 42 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 187 d18 irl0 i interrupt 0 188 c20 irl1 i interrupt 1 189 c19 irl2 i interrupt 2 190 b20 irl3 i interrupt 3 191 b18 vss-rtc power rtc gnd 192 e17 vss power gnd 193 a20 xtal2 o rtc crystal resonator pin 194 a19 extal2 i rtc crystal resonator pin 195 a18 vdd-rtc power rtc vdd 196 b19 vddq power io vdd 197 c18 ca i hardware standby 198 a17 reset i reset reset 199 b17 trst i reset (h-udi) 200 c17 mreset i manual reset 201 a16 nmi i nonmaskable interrupt 202 b16 back / bsreq o bus acknowledge/ bus request 203 c16 breq / bsack i bus request/bus acknowledge 204 a15 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 205 b15 rdy i bus ready rdy rdy rdy 206 c15 txd o sci data output 207 c14 vddq power io vdd 208 c11 vss power gnd 209 d14 vdd power internal vdd 210 d16 vss power gnd 211 a14 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 212 b14 rxd i sci data input
1. overview rev.4.00 oct. 10, 2008 page 43 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 213 a13 tclk i/o rtc/tmu clock 214 b13 md8/ rts2 i/o mode/scif data control (rts) md8 rts2 rts2 rts2 rts2 rts2 215 c13 sck i/o scif clock 216 a12 md1/txd2 i/o mode/scif data output md1 txd2 txd2 txd2 txd2 txd2 217 b12 md0/sck2 i/o mode/scif clock md0 sck2 sck2 sck2 sck2 sck2 218 c12 md7/ cts2 i/o mode/scif data control (rts) md7 cts2 cts2 cts2 cts2 cts2 219 a11 audsync aud sync 220 b11 audck aud clock 221 d15 vddq power io vdd 222 d10 vss power gnd 223 a10 audata0 aud data 224 b10 audata1 aud data 225 d11 vdd power internal vdd 226 d17 vss power gnd 227 c10 audata2 aud data 228 a9 audata3 aud data 229 d8 vss gnd 230 b9 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 231 c9 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 232 a8 md5 i mode md5 233 d12 vddq power io vdd 234 d9 vddq power i/o vdd 235 b8 dack0 o dmac0 bus acknowledge 236 c8 dack1 o dmac1 bus acknowledge 237 a7 drak0 o dmac0 request acknowledge
1. overview rev.4.00 oct. 10, 2008 page 44 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 238 b7 drak1 o dmac1 request acknowledge 239 d7 vdd power internal vdd 240 d6 vddq power i/o vdd 241 a6 status0 o status 242 b6 status1 o status 243 c6 dreq0 i request from dmac0 244 c5 dreq1 i request from dmac1 245 b5 asebrk / brkack i/o pin break/ acknowledge (h-udi) 246 c4 tdo o data out (h-udi) 247 c7 vddq power io vdd 248 d13 vss power gnd 249 a5 vdd-pll2 power pll2 vdd 250 b4 vss-pll2 power pll2 gnd 251 a4 vdd-pll1 power pll1 vdd 252 c3 vss-pll1 power pll1 gnd 253 b3 vdd-cpg power cpg vdd 254 a3 vss-cpg power cpg gnd 255 a2 xtal o crystal resonator 256 a1 extal i external input clock/crystal resonator 257 h8 vss power gnd 258 j8 vss power gnd 259 k8 vss power gnd 260 l8 vss power gnd 261 m8 vss power gnd 262 n8 vss power gnd 263 n9 vss power gnd 264 n10 vss power gnd 265 n11 vss power gnd
1. overview rev.4.00 oct. 10, 2008 page 45 of 1122 rej09b0370-0400 memory interface no. pin number pin name i/o function reset sram dram sdram pcmcia mpx 266 n12 vss power gnd 267 n13 vss power gnd 268 m13 vss power gnd 269 l13 vss power gnd 270 k13 vss power gnd 271 j13 vss power gnd 272 h13 vss power gnd 273 h12 vss power gnd 274 h11 vss power gnd 275 h10 vss power gnd 276 h9 vss power gnd 277 j9 vss power gnd 278 k9 vss power gnd 279 l9 vss power gnd 280 m9 vss power gnd 281 m10 vss power gnd 282 m11 vss power gnd 283 m12 vss power gnd 284 l12 vss power gnd 285 k12 vss power gnd 286 j12 vss power gnd 287 j11 vss power gnd 288 j10 vss power gnd 289 k10 vss power gnd 290 l10 vss power gnd 291 l11 vss power gnd 292 k11 vss power gnd legend: i: input o: output i/o: input/output power: power supply
1. overview rev.4.00 oct. 10, 2008 page 46 of 1122 rej09b0370-0400 notes: supply power to all power pins. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. for the handling of the pci bus pins in pci- disabled mode, see table d.4 in appendix d. * i/o attribute is i/o when used as a port.
2. programming model rev.4.00 oct. 10, 2008 page 47 of 1122 rej09b0370-0400 section 2 programming model 2.1 data formats the data formats handled by the sh-4 are shown in figure 2.1. byte (8 bits) word (16 bits) lon g word (32 bits) sin g le-precision floatin g -point (32 bits) double-precision floatin g -point (64 bits) 0 7 0 15 0 31 0 31 30 22 fraction exp s 0 63 62 51 exp s fraction figure 2.1 data formats
2. programming model rev.4.00 oct. 10, 2008 page 48 of 1122 rej09b0370-0400 2.2 register configuration 2.2.1 privileged mode and banks processor modes: the sh-4 has two processor modes, user mode and privileged mode. the sh-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. there are fo ur kinds of registers?general registers, system registers, control registers, and floating- point registers?and the registers th at can be accessed differ in the two processor modes. general registers: there are 16 general registers, designated r0 to r15. general registers r0 to r7 are banked registers which are switched by a processor mode change. in privileged mode, the register bank bit (rb) in the status register (sr) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (ldc) and store control register (stc) instructions. when the rb bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers r0_bank1 to r7_bank1 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. in this case, the eight registers comprising bank 0 general registers r0_bank0 to r7_bank0 are accessed by the ldc/ stc instructions. when the rb bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers r0_bank0 to r7_bank0 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. in this case, the eight registers comprising bank 1 general registers r0_bank1 to r7_bank1 are accessed by the ldc/stc instructions. in user mode, the 16 registers comprising bank 0 general registers r0_bank0 to r7_bank0 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. the eight registers comprising bank 1 general registers r0_bank1 to r7_bank1 cannot be accessed. control registers: control registers comprise the global ba se register (gbr) an d status register (sr), which can be accessed in both processor modes, and the saved status register (ssr), saved program counter (spc), vector base register (vbr), saved general register 15 (sgr), and debug base register (dbr), which can only be accessed in privileged mode. some bits of the status register (such as the rb bit) can only be accessed in privileged mode. system registers: system registers comprise the multiply-and-accumulate registers (mach/macl), the procedure register (pr), the program counter (pc), the floating-point status/control register (fpscr), and the floating- point communication regist er (fpul). access to these registers does not depend on the processor mode.
2. programming model rev.4.00 oct. 10, 2008 page 49 of 1122 rej09b0370-0400 floating-point registers: there are thirty-two floating-point registers, fr0?fr15 and xf0? xf15. fr0?fr15 and xf0?xf15 can be assigned to either of two banks (fpr0_bank0? fpr15_bank0 or fpr0_bank1?fpr15_bank1). fr0?fr15 can be used as the eight registers dr0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers fv0/4/8/12 (register vectors), while xf0? xf15 can be used as the eight registers xd0/2/4/6/8/10/12/14 (register pairs) or register matrix xmtrx. register values after a reset are shown in table 2.1. table 2.1 initial register values type registers initial value * general registers r0_bank0?r7_bank0, r0_bank1?r7_bank1, r8?r15 undefined sr md bit = 1, rb bit = 1, bl bit = 1, fd bit = 0, imask = 1111 (h'f), reserved bits = 0, others undefined gbr, ssr, spc, sgr, dbr undefined control registers vbr h'00000000 mach, macl, pr, fpul undefined pc h'a0000000 system registers fpscr h'00040001 floating-point registers fr0?fr15, xf0?xf15 undefined note: * initialized by a power-on reset and manual reset. the register configuration in each pro cessor mode is show n in figure 2.2. switching between user mode and privileged mode is controlled by the processor mode bit (md) in the status register.
2. programming model rev.4.00 oct. 10, 2008 page 50 of 1122 rej09b0370-0400 31 0 r0 _ bank0 * 1 * 2 r1 _ bank0 * 2 r2 _ bank0 * 2 r3 _ bank0 * 2 r4 _ bank0 * 2 r5 _ bank0 * 2 r6 _ bank0 * 2 r7 _ bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc (a) re g ister confi g uration in user mode 31 0 r0 _ bank1 * 1 * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1 * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (b) re g ister confi g uration in privile g ed mode (rb = 1) gbr mach macl vbr pr sr ssr pc spc 31 0 r0 _ bank1 * 1 * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1 * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (c) re g ister confi g uration in privile g ed mode (rb = 0) gbr mach macl vbr pr sr ssr pc spc sgr dbr sgr dbr notes: 1. the r0 re g ister is used as the index re g ister in indexed re g ister-indirect addressin g mode and indexed gbr indirect addressin g mode. 2. banked re g isters 3. banked re g isters accessed as g eneral re g isters when the rb bit is set to 1 in the sr re g ister. accessed only by ldc/stc instructions when the rb bit is cleared to 0. 4. banked re g isters accessed as g eneral re g isters when the rb bit is cleared to 0 in the sr re g ister. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.2 cpu register configuration in each processor mode
2. programming model rev.4.00 oct. 10, 2008 page 51 of 1122 rej09b0370-0400 2.2.2 general registers figure 2.3 shows the relationship between the processor modes and general registers. the sh-4 has twenty-four 32-bit general registers (r0_bank0?r7_bank0, r0_bank1?r7_bank1, and r8?r15). however, only 16 of these can be accessed as general registers r0?r15 in one processor mode. the sh-4 has two processor modes, user mode and privileged mode, in which r0?r7 are assigned as shown below. ? r0_bank0?r7_bank0 in user mode (sr.md = 0), r0?r7 are always assigned to r0_bank0?r7_bank0. in privileged mode (sr.md = 1), r0?r7 are assigned to r0_bank0?r7_bank0 only when sr.rb = 0. ? r0_bank1?r7_bank1 in user mode, r0_bank1?r7_bank1 cannot be accessed. in privileged mode, r0?r7 are assigned to r0_bank1?r7_bank1 only when sr.rb = 1.
2. programming model rev.4.00 oct. 10, 2008 page 52 of 1122 rej09b0370-0400 sr.md = 0 or (sr.md = 1, sr.rb = 0) r0_bank0 r1_bank0 r2_bank0 r3_bank0 r4_bank0 r5_bank0 r6_bank0 r7_bank0 r0_bank0 r1_bank0 r2_bank0 r3_bank0 r4_bank0 r5_bank0 r6_bank0 r7_bank0 r0_bank1 r1_bank1 r2_bank1 r3_bank1 r4_bank1 r5_bank1 r6_bank1 r7_bank1 r0_bank1 r1_bank1 r2_bank1 r3_bank1 r4_bank1 r5_bank1 r6_bank1 r7_bank1 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 (sr.md = 1, sr.rb = 1) figure 2.3 general registers programming note: as the user's r0?r7 are assigned to r0_bank0?r7_bank0, and after an exception or interrupt r0?r7 are assigned to r0_bank1?r7_bank1, it is not necessary for the interrupt handler to save and restore the user's r0?r7 (r0_bank0?r7_bank0). after a reset, the values of r0_bank0?r7_bank0, r0_bank1?r7_bank1, and r8?r15 are undefined.
2. programming model rev.4.00 oct. 10, 2008 page 53 of 1122 rej09b0370-0400 2.2.3 floating-point registers figure 2.4 shows the floating-point registers. there are thirty-two 32-bit floating-point registers, divided into two banks (fpr0_bank0?fpr15_bank0 and fpr0_bank1?fpr15_bank1). these 32 registers are referenced as fr0?fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0?xf15, xd0/2/4/6/8/10/12/14, or xmtrx. the correspondence between fprn_banki and the reference name is determined by the fr bit in fpscr (see figure 2.4). ? floating-point registers, fprn_banki (32 registers) fpr0_bank0, fpr1_bank0, fpr2_b ank0, fpr3_bank0, fpr4_bank0, fpr5_bank0, fpr6_bank0, fpr7_b ank0, fpr8_bank0, fpr9_bank0, fpr10_bank0, fpr11_bank0, fpr12_ba nk0, fpr13_bank0, fpr14_bank0, fpr15_bank0 fpr0_bank1, fpr1_bank1, fpr2_b ank1, fpr3_bank1, fpr4_bank1, fpr5_bank1, fpr6_bank1, fpr7_b ank1, fpr8_bank1, fpr9_bank1, fpr10_bank1, fpr11_bank1, fpr12_ba nk1, fpr13_bank1, fpr14_bank1, fpr15_bank1 ? single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0?fr15 are assigned to fpr0_bank0?fpr15_bank0. when fpscr.fr = 1, fr0?fr15 are assigned to fpr0_bank1?fpr15_bank1. ? double-precision floating-point registers or single-precision floating-point register pairs, dri (8 registers): a dr register comprises two fr registers. dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} ? single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} ? single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0?xf15 are a ssigned to fpr0_bank1?fpr15_bank1. when fpscr.fr = 1, xf0?xf15 are a ssigned to fpr0_bank0?fpr15_bank0. ? single-precision floating-point extended register pairs, xdi (8 registers): an xd register comprises two xf registers xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15}
2. programming model rev.4.00 oct. 10, 2008 page 54 of 1122 rej09b0370-0400 ? single-precision floating-point extended register matrix, xmtrx: xmtrx comprises all 16 xf registers xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 fpr0_bank0 fpr1_bank0 fpr2_bank0 fpr3_bank0 fpr4_bank0 fpr5_bank0 fpr6_bank0 fpr7_bank0 fpr8_bank0 fpr9_bank0 fpr10_bank0 fpr11_bank0 fpr12_bank0 fpr13_bank0 fpr14_bank0 fpr15_bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0_bank1 fpr1_bank1 fpr2_bank1 fpr3_bank1 fpr4_bank1 fpr5_bank1 fpr6_bank1 fpr7_bank1 fpr8_bank1 fpr9_bank1 fpr10_bank1 fpr11_bank1 fpr12_bank1 fpr13_bank1 fpr14_bank1 fpr15_bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr = 0 fpscr.fr = 1 figure 2.4 floating-point registers
2. programming model rev.4.00 oct. 10, 2008 page 55 of 1122 rej09b0370-0400 programming note: after a reset, the values of fpr0_bank0?fpr15_bank0 and fpr0_bank1?fpr15_bank1 are undefined. 2.2.4 control registers status register, sr (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00xx 1111 00xx (x = undefined)) 31 30 29 28 27 16 15 14 10 9 8 7 4 3 2 1 0 ? md rb bl ? fd ? m q imask ? s t note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? md: processor mode md = 0: user mode (some instructions canno t be executed, and some resources cannot be accessed) md = 1: privileged mode ? rb: general register specification bit in privileged mode (set to 1 by a reset, exception, or interrupt) rb = 0: r0_bank0?r7_bank0 are accessed as general registers r0?r7. (r0_bank1? r7_bank1 can be accessed usin g ldc/stc instructions.) rb = 1: r0_bank1?r7_bank1 are accessed as general registers r0?r7. (r0_bank0? r7_bank0 can be accessed usin g ldc/stc instructions.) ? bl: exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) bl = 1: interrupt requests are masked. if a ge neral exception other than a user break occurs while bl = 1, the processor sw itches to the reset state. ? fd: fpu disable bit (cleared to 0 by a reset) fd = 1: an fpu instruction causes a general fpu disable exception, and if the fpu instruction is in a delay slot, a slot fpu disable exception is generated. (fpu instructions: h'f*** instructions, ldc(.l)/sts(.l) instructions for fpul/fpscr) ? m, q: used by the div0s, div0u, and div1 instructions. ? imask: interrupt mask level interrupts of a lower level than imask are masked. imask does not change when an interrupt is generated. ? s: specifies a saturation operation for a mac instruction.
2. programming model rev.4.00 oct. 10, 2008 page 56 of 1122 rej09b0370-0400 ? t: true/false condition or carry/borrow bit saved status register, ssr (32 bits, privile ge protection, initial value undefined): the current contents of sr are saved to ssr in the event of an exception or interrupt. saved program counter, spc (32 bits, privilege protection, initial value undefined): the address of an instruction at which an interrupt or exception occurs is saved to spc. global base register, gbr (32 bits, initial value undefined): gbr is referenced as the base address in a gbr-referencing mov instruction. vector base register, vbr (3 2 bits, privilege protection, initial value = h'0000 0000): vbr is referenced as the branch destination base addres s in the event of an exception or interrupt. for details, see section 5, exceptions. saved general register 15, sgr (32 bits, priv ilege protection, initial value undefined): the contents of r15 are saved to sgr in the event of an exception or interrupt. debug base register, dbr (32 bits, privile ge protection, initial value undefined): when the user break debug function is enabled (brcr.ubde = 1), dbr is referenced as the user break handler branch destination address instead of vbr. 2.2.5 system registers multiply-and-accumulate register high, ma ch (32 bits, initial value undefined) multiply-and-accumulate re gister low, macl (32 bits, initial value undefined) mach/macl is used for the added value in a ma c instruction, and to store a mac instruction or mul instruction operation result. procedure register, pr (32 bits, initial value undefined): the return address is stored in pr in a subroutine call using a bsr, bsrf, or jsr instruction, and pr is referenced by the subroutine return instruction (rts). program counter, pc (32 bits, initial value = h'a000 0000): pc indicates the executing instruction address.
2. programming model rev.4.00 oct. 10, 2008 page 57 of 1122 rej09b0370-0400 floating-point status/control register, fpscr (32 bits, initial value = h'0004 0001) 31 22 21 20 19 18 17 12 11 7 6 2 1 0 ? fr sz pr dn cause enable flag rm note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? fr: floating-point register bank fr = 0: fpr0_bank0?fpr15_bank0 are assigned to fr0?fr15; fpr0_bank1? fpr15_bank1 are assigned to xf0?xf15. fr = 1: fpr0_bank0?fpr15_bank0 are assigned to xf0?xf15; fpr0_bank1? fpr15_bank1 are assigned to fr0?fr15. ? sz: transfer size mode sz = 0: the data size of the fmov instruction is 32 bits. sz = 1: the data size of the fmov instruc tion is a 32-bit register pair (64 bits). ? pr: precision mode pr = 0: floating-point instructions are executed as single-precision operations. pr = 1: floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). do not set sz and pr to 1 simultaneously; this setting is reserved. [sz, pr = 11]: reserved (fpu operation instruction is undefined.) ? dn: denormalization mode dn = 0: a denormalized number is treated as such. dn = 1: a denormalized nu mber is treated as zero. ? cause: fpu exception cause field ? enable: fpu exception enable field ? flag: fpu exception flag field fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2
2. programming model rev.4.00 oct. 10, 2008 page 58 of 1122 rej09b0370-0400 when an fpu operation instruction is executed, the fpu exception cause field is cleared to zero first. when the next fpu exception is occured, the corresponding bits in the fpu exception cause field and fpu excep tion flag field are set to 1. the fpu exception flag field holds the status of the exception gene rated after the field was last cleared. ? rm: rounding mode rm = 00: round to nearest rm = 01: round to zero rm = 10: reserved rm = 11: reserved ? bits 22 to 31: reserved floating-point communication register, fp ul (32 bits, initial value undefined): data transfer between fpu registers and cpu registers is carried out via the fpul register. programming note: when sz = 1 and big endian mode is selected, fmov can be used for double-precision floating-point data load or store operations. in little endian mode, two 32-bit data size moves must be executed, with sz = 0, to load or store a double-precision floating-point data. 2.3 memory-mapped registers appendix a shows the control registers mapped to memory. the control registers are double- mapped to the following two memory areas. all registers have two addresses. h'1c00 0000?h'1fff ffff h'fc00 0000?h'ffff ffff these two areas are used as follows. ? h'1c00 0000?h'1fff ffff this area must be accessed using the address tr anslation function of the mmu. setting the page number of this area to the corresponding filed of the tlb enables access to a memory- mapped register. accessing this area without us ing the address translation function of the mmu is not guaranteed. ? h'fc00 0000?h'ffff ffff access to area h'fc00 0000?h'ffff ffff in user mode will cause an address error. memory- mapped registers can be referenced in user mode by means of access that involves address translation.
2. programming model rev.4.00 oct. 10, 2008 page 59 of 1122 rej09b0370-0400 note: do not access undefined locations in e ither area the operation of an access to an undefined location is undefined. also, memo ry-mapped registers must be accessed using a fixed data size. the operatio n of an access using an invali d data size is undefined. 2.4 data format in registers register operands are always longwords (32 bits). when a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 lon g word 2.5 data formats in memory memory data formats are classifi ed into bytes, words, and longwords. memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. a memory operand less than 32 bits in length is sign-extended before being loaded into a register. a word operand must be accessed starting from a word boundary (e ven address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). an address error will result if this rule is not observed. a byte operand can be accessed from any address. big endian or little endian byte order can be selected for the data format. the endian should be set with the md5 external pin in a power-on reset. big endian is selected when the md5 pin is low, and little endian when high. the endian cannot be changed dynamically. bit positions are numbered left to right from most-significant to least-significant. thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit an d the rightmost bit, bit 0, is the least significant bit.
2. programming model rev.4.00 oct. 10, 2008 page 60 of 1122 rej09b0370-0400 the data format in memory is shown in figure 2.5. address a a 70707070 31 15 0 15 0 31 0 15 0 31 0 23 15 7 0 a + 1 a + 2 a + 3 byte 0 word 0 lon g word word 1 byte 1 byte 2 byte 3 a + 11 70707070 31 15 0 23 15 7 0 a + 10 a + 9 a + 8 byte 3 word 1 lon g word word 0 byte 2 byte 1 byte 0 address a + 4 address a + 8 address a + 8 address a + 4 address a bi g endian little endian figure 2.5 data formats in memory note: the sh-4 does not support endian conversion for the 64-bit data format. therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 processor states the sh-4 has five processor states: the reset stat e, exception-handling stat e, bus-released state, program execution state, and power-down state. reset state: in this state the cpu is reset. the po wer-on reset state is entered when the reset pin goes low. the cpu enters the manual reset state if the reset pin is high and the mreset pin is low. for more information on resets, see section 5, exceptions. in the power-on reset state, th e internal state of the cpu and the on-chip peripheral module registers are initialized. in the manual reset state, the internal state of the cpu and registers of on- chip peripheral modules other th an the bus state controller (bsc ) are initialized. since the bus state controller (bsc) is not initialized in the ma nual reset state, refreshing operations continue. refer to the register configurations in the relevant sections for further details. exception-handling state: this is a transient state during wh ich the cpu's processor state flow is altered by a reset, general exception, or interrupt exception source. in the case of a reset, the cpu branches to addr ess h'a000 0000 and star ts executing the user- coded exception handling program. in the case of a general exception or interrupt, the program counter (pc) contents are saved in the saved program counter (spc), the status register (sr) contents are saved in the saved status register (ssr), and the r15 contents are saved in saved general register 15 (sgr). the cpu
2. programming model rev.4.00 oct. 10, 2008 page 61 of 1122 rej09b0370-0400 branches to the start address of the user-coded ex ception service routine fo und from the sum of the contents of the vector base address and the v ector offset. see section 5, exceptions, for more information on resets, general exceptions, and interrupts. program execution state: in this state the cpu executes pr ogram instructions in sequence. power-down state: in the power-down state, cpu operation halts and power consumption is reduced. the power-down state is entered by executing a sleep instru ction. there are three modes in the power-down state: sleep mode, deep sleep mode, and standby mode. for details, see section 9, power-down modes. bus-released state: in this state the cpu has released th e bus to a device that requested it. transitions between the states are shown in figure 2.6. reset = 0 reset = 1, mreset = 1 reset = 1 power-on reset state manual reset state program execution state bus-released state exception-handling state interrupt interrupt end of exception transition processing bus request clearance exception interrupt bus request clearance bus request bus request clearance sleep instruction with stby bit cleared sleep instruction with stby bit set from any state when reset = 0 reset = 1 and mreset = 0 reset state power-down state bus request bus request standby mode sleep mode figure 2.6 processor state transitions
2. programming model rev.4.00 oct. 10, 2008 page 62 of 1122 rej09b0370-0400 2.7 processor modes there are two processor modes: user mode and privileged mode. the processor mode is determined by the processor mode bit (md) in the status register (sr). user mode is selected when the md bit is cleared to 0, and privileged mode when the md bit is set to 1. when the reset state or exception state is entered, the md bit is set to 1. there are certain registers and bits which can only be accessed in privileged mode.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 63 of 1122 rej09b0370-0400 section 3 memory management unit (mmu) 3.1 overview 3.1.1 features the sh-4 can handle 29-bit extern al memory space from an 8-bit address space identifier and 32- bit logical (virtual) address space. address translation from virtua l address to physical address is performed using the memory management unit (mmu) built into the sh-4. the mmu performs high-speed address translation by caching user-cr eated address translation table information in an address translation buffer (translation lookaside bu ffer: tlb). the sh-4 has four instruction tlb (itlb) entries and 64 unified tlb (utlb) entries. utlb copies are stored in the itlb by hardware. a paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 mbyte). it is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 role of the mmu the mmu was conceived as a means of making ef ficient use of physical memory. as shown in figure 3.1, when a process is sm aller in size than the physical me mory, the entire process can be mapped onto physical memory, but if the process in creases in size to the po int where it does not fit into physical memory, it becomes necessary to divi de the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). having this mapping onto physical memory executed consciously by th e process itself imposes a heavy burden on the process. the virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). with a vi rtual memory system, th e size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally managed by the os, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. physical memory switching is performed via secondary storage, etc. the virtual memory system that cam e into being in this way works to best effect in a time sharing system (tss) that allows a number of processes to run simultaneously ((3)). running a number of processes in a tss did not increase efficiency sin ce each process had to take account of physical memory mapping. efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). in this system, virtual memory is allocated to each process. the task of the mmu is to map a number of virtual memo ry areas onto physical me mory in an efficient
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 64 of 1122 rej09b0370-0400 manner. it is also provided with memory protection functions to prevent a process from inadvertently accessing anothe r process's physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may happen that the translation information has not been recorded in the mmu, or the virtual memory of a different process is accessed by mist ake. in such cases, the mmu will generate an exception, change the physical memory mapping, and reco rd the new address translation information. although the functions of the mmu could be implemented by software alone, having address translation performed by software each time a pr ocess accessed physical memory would be very inefficient. for this reason, a buffer for address translation (the translation lookaside buffer: tlb) is provided in hardware, and frequently used address translation information is placed here. the tlb can be described as a cache for address transl ation information. however, unlike a cache, if address translation fails?that is, if an excep tion occurs?switching of the address translation information is normally performed by software. thus memory management can be performed in a flexible manner by software. there are two methods by which the mmu can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space called a page (usu ally from 1 to 64 kbytes in size). in the following descriptions, the address space in virtual memory in the sh-4 is referred to as virtual address space, and the ad dress space in physical memory as physical address space.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 65 of 1122 rej09b0370-0400 (2) process 1 process 1 physical memory process 1 process 2 process 3 virtual memory process 1 process 1 process 2 process 3 mmu mmu (4) (3) (1) physical memory physical memory physical memory physical memory virtual memory figure 3.1 role of the mmu
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 66 of 1122 rej09b0370-0400 3.1.3 register configuration the mmu registers are shown in table 3.1. table 3.1 mmu registers name abbrevia- tion r/w initial value * 1 p4 address * 2 area 7 address * 2 access size page table entry high register pteh r/w undefined h'ff00 0000 h'1f00 0000 32 page table entry low register ptel r/w undefined h'ff00 0004 h'1f00 0004 32 page table entry assistance register ptea r/w undefined h 'ff00 0034 h'1f00 0034 32 translation table base register ttb r/w undefined h 'ff00 0008 h'1f00 0008 32 tlb exception address register tea r/w undefined h'ff 00 000c h'1f00 000c 32 mmu control register mmucr r/w h'0000 0000 h'ff00 0010 h'1f00 0010 32 notes: 1. the initial value is the valu e after a power-on reset or manual reset. 2. p4 address is the address when using the virtual/physical address space p4 area. the area 7 address is the address used when making an access from physical address space area 7 using the tlb. 3.1.4 caution operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 67 of 1122 rej09b0370-0400 3.2 register descriptions there are six mmu-related registers. 31 10 9 8 70 vpn ppn ? ? asid 1. pteh 31 30 29 28 10 9 8 7 65 4 3 2 1 0 ??? ?vszprszcdsh wt 2. ptel 31 4 3 20 tc sa 3. ptea 31 0 0 ttb 4. ttb 31 virtual address at which mmu exception or address error occurred 5. tea 31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 lrui ? ? ? ? urc sqmd sv?????ti?at 6. mmucr note: ? indicates a reserved bit: the write value must be 0, and a read will return 0. urb 25 figure 3.2 mmu-related registers
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 68 of 1122 rej09b0370-0400 1. page table entry high register (pteh): longword access to pteh can be performed from h'ff00 0000 in the p4 area and h'1f00 0000 in area 7. pteh consists of the virtual page number (vpn) and address space identifier (asid). when an mmu exception or address error exception occurs, the vpn of the virtual ad dress at which the exception occu rred is set in the vpn field by hardware. vpn varies according to the page size, but the vpn set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. vpn setting can also be carried out by softwa re. the number of the currently executing process is set in the asid field by software. asid is not updated by hardware. vpn and asid are recorded in the utlb by means of the ldltb instruction. a bran ch to the p0, p3, or v0 area which uses the updated asid after the asid field in pteh is rewritten should be made at least 6 instructions after the pteh update instruction. 2. page table entr y low register (ptel): longword access to ptel can be performed from h'ff00 0004 in the p4 area and h'1f00 0004 in area 7. ptel is used to hold the physical page number and page management information to be recorded in the utlb by means of the ldtlb instruction. the contents of this register are not changed unless a softwa re directive is issued. 3. page table entry assistance register (ptea): longword access to ptea can be performed from h'ff00 0034 in the p4 area and h'1f00 0034 in area 7. ptea is used to store assistance bits for pcmcia access to the utlb by means of the ldtlb instruction. when performing pcmcia access with the mmu off, access is always performed using the values of the sa and tc bits in this register. acces s to a pcmcia interface area by the dmac is always performed using the dmac's chcrn.ssan, chcrn.dsan, chcrn.stc, and chcrn.dtc values. the contents of this register are not changed unless a software directive is issued. 4. translation table base register (ttb): longword access to ttb can be performed from h'ff00 0008 in the p4 area and h'1f00 0008 in area 7. ttb is used, for example, to hold the base address of the cu rrently used page table. the contents of ttb are not changed unless a software directive is issued. this register can be freely used by software. 5. tlb exception address register (tea): longword access to tea can be performed from h'ff00 000c in the p4 area and h'1f00 000c in area 7. after an mmu exception or address error exception occurs, the virtual addr ess at which the exception occurr ed is set in tea by hardware. the contents of this register can be changed by software. 6. mmu control register (mmucr): mmucr contains the following bits: lrui: least recently used itlb urb: utlb replace boundary urc: utlb replace counter sqmd: store queue mode bit sv: single virtual mode bit
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 69 of 1122 rej09b0370-0400 ti: tlb invalidate at: address translation bit longword access to mmucr can be performed fro m h'ff00 0010 in the p4 area and h'1f00 0010 in area 7. the individual bits perform mmu settings as shown below. therefore, mmucr rewriting should be performed by a program in the p1 or p2 area. after mmucr is updated, an instruction that performs data access to the p0, p3 , u0, or store queue area should be located at least four instructions after th e mmucr update instructio n. also, a branch instruction to the p0, p3, or u0 area should be located at least eight instructions after the mmucr update instruction. mmucr contents can be changed by software. the lrui bits and urc bits may also be updated by hardware. ? lrui: lru bits that indicate the itlb entry fo r which replacement is to be performed. the lru (least recently used) method is used to deci de the itlb entry to be replaced in the event of an itlb miss. the entry to be purged from the itlb can be confirmed using the lrui bits. lrui is updated by means of the algorithm shown below. a dash in this table means that updating is not performed. lrui [5] [4] [3] [2] [1] [0] when itlb entry 0 is used 0 0 0 ? ? ? when itlb entry 1 is used 1 ? ? 0 0 ? when itlb entry 2 is used ? 1 ? 1 ? 0 when itlb entry 3 is used ? ? 1 ? 1 1 other than the above ? ? ? ? ? ? when the lrui bit settings are as shown below, the corresponding itlb entry is updated by an itlb miss. an asterisk in this table means ?don't care?. lrui [5] [4] [3] [2] [1] [0] itlb entry 0 is updated 1 1 1 * * * itlb entry 1 is updated 0 * * 1 1 * itlb entry 2 is updated * 0 * 0 * 1 itlb entry 3 is updated * * 0 * 0 0 other than the above setting prohibited
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 70 of 1122 rej09b0370-0400 ensure that values for which ?setting prohibited? is indicated in the above table are not set at the discretion of software. after a power-on or ma nual reset the lrui bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. ? urb: bits that indicate the u tlb entry boundary at which re placement is to be performed. valid only when urb > 0. ? urc: random counter for indicating the utlb entry for which replacement is to be performed with an ldtlb instruction. urc is incremented each time the utlb is accessed. when urb > 0, urc is reset to 0 when the condition urc = urb occurs. also note that, if a value is written to urc by software which results in the condition urc > urb, incrementing is first performed in excess of urb until urc = h'3f. urc is not incremented by an ldtlb instruction. ? sqmd: store queue mode bit. specifies th e right of access to the store queues. 0: user/privileged access possible 1: privileged access possible (address er ror exception in case of user access) ? sv: bit that switches between single virtual memory mode and multiple virtual memory mode. 0: multiple virtual memory mode 1: single virtual memory mode when this bit is changed, ensure th at 1 is also written to the ti bit. ? ti: tlb invalidation bit. writing 1 to this bit invalidates (clears to 0) all valid utlb/itlb bits. this bit always returns 0 when read. ? at: address translation enable bit. specifies mmu enabling or disabling. 0: mmu disabled 1: mmu enabled mmu exceptions are not generated when the at bit is 0. in the case of software that does not use the mmu, therefore, the at bit should be cleared to 0.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 71 of 1122 rej09b0370-0400 3.3 address space 3.3.1 physical address space the sh-4 supports a 32-bit physi cal address space, and can access a 4-gbyte address space. when the mmucr.at bit is cleared to 0 and the mmu is disabled, the ad dress space is this physical address space. the physical address space is divide d into a number of areas, as shown in figure 3.3. the physical address space is permanently mapped onto 29-b it external memory space; this correspondence can be im plemented by ignoring the upper 3 b its of the physical address space addresses. in privileged mode, th e 4-gbyte space from the p0 area to the p4 area can be accessed. in user mode, a 2-gbyte space in the u0 area can be accessed. accessing the p1 to p4 areas (except the store queue area) in user mode will cause an address error. area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external memory space address error address error store queue area user mode privileged mode p1 area cacheable p0 area cacheable p2 area non-cacheable p3 area cacheable p4 area non-cacheable u0 area cacheable h'0000 0000 h'8000 0000 h'e000 0000 h'e400 0000 h'ffff ffff h'0000 0000 h'8000 0000 h'ffff ffff h'a000 0000 h'c000 0000 h'e000 0000 figure 3.3 physical address space (mmucr.at = 0) when performing access fr om the cpu to a pcmcia interface ar ea in the sh-4, access is always performed using the values of the sa and tc bits set in the ptea regist er. access to a pcmcia interface area by the dmac is always pe rformed using the dmac's chcrn.ssan,
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 72 of 1122 rej09b0370-0400 chcrn.dsan, chcrn.stc, and chcrn.dtc values. for details, see section 14, direct memory access co ntroller (dmac). p0, p1, p3, u0 areas: the p0, p1, p3, and u0 areas can be accessed using the cache. whether or not the cache is used is determined by the cach e control register (ccr). when the cache is used, with the exception of the p1 area, switching be tween the copy-back method and the write-through method for write accesses is specifi ed by the ccr.wt bit. for the p1 area, switching is specified by the ccr.cb bit. zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. however, since ar ea 7 in the external memory space is a reserved area, a reserved area also appears in these areas. p2 area: the p2 area cannot be accessed using the cache . in the p2 area, zeroizing the upper 3 bits of an address gives the corresponding exte rnal memory space address. however, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. p4 area: the p4 area is mapped onto sh-4 on-chip i/o channels. this ar ea cannot be accessed using the cache. the p4 area is shown in detail in figure 3.4. h'e000 0000 h'e400 0000 h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'f500 0000 h'f600 0000 h'f700 0000 h'f800 0000 h'fc00 0000 h'ffff ffff store queue reserved area instruction cache address array instruction cache data array instruction tlb address array instruction tlb data arrays 1 and 2 operand cache address array operand cache data array unified tlb address array unified tlb data arrays 1 and 2 reserved area control register area figure 3.4 p4 area
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 73 of 1122 rej09b0370-0400 the area from h'e000 0000 to h'e3ff ffff comp rises addresses for acce ssing the store queues (sqs). when the mmu is disabled (mmucr.at = 0), the sq access right is specified by the mmucr.sqmd bit. for details, see section 4.7, store queues. the area from h'f000 0000 to h'f0ff ffff is used for dir ect access to the instruction cache address array. for details, see s ection 4.5.1, ic address array. the area from h'f100 0000 to h' f1ff ffff is used for direct access to the instruction cache data array. for details, see section 4.5.2, ic data array. the area from h'f200 0000 to h'f2ff ffff is used for dir ect access to the instruction tlb address array. for details, see sec tion 3.7.1, itlb address array. the area from h'f300 0000 to h' f3ff ffff is used for direct access to instruction tlb data arrays 1 and 2. for details, see sections 3.7.2, i tlb data array 1, and 3.7.3, itlb data array 2. the area from h'f400 0000 to h' f4ff ffff is used for direct access to the operand cache address array. for details, see section 4.5.3, oc address array. the area from h'f500 0000 to h' f5ff ffff is used for direct access to the operand cache data array. for details, see section 4.5.4, oc data array. the area from h'f600 0000 to h' f6ff ffff is used for direct access to the unified tlb address array. for details, see section 3.7.4, utlb address array. the area from h'f700 0000 to h'f7ff ffff is used for direct access to unified tlb data arrays 1 and 2. for details, see sections 3.7.5, utlb data array 1, and 3.7.6, utlb data array 2. the area from h'fc00 0000 to h'ffff ffff is the on-chip peripheral module control register area. for details, see ap pendix a, address list.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 74 of 1122 rej09b0370-0400 3.3.2 external memory space the sh-4 supports a 29-bit extern al memory space. the external memory space is divided into eight areas as shown in figure 3.5. areas 0 to 6 relate to memory, such as sram, synchronous dram, dram, and pcmcia. area 7 is a reserved area. for details, see section 13, bus state controller (bsc). h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'1fff ffff area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 (reserved area) figure 3.5 external memory space
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 75 of 1122 rej09b0370-0400 3.3.3 virtual address space setting the mmucr.at bit to 1 enab les the p0, p3, and u0 areas of the physical address space in the sh-4 to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-mbyte, page units. by using an 8-b it address space identifier, the p0, u0, p3, and store queue areas can be increased to a maximum of 256. this is called the virtual address space. mapping from virtual address space to 29-bit ex ternal memory space is carried out using the tlb. only when area 7 in external memory space is accessed using virtual address space, addresses h'1c00 0000 to h'1fff ffff of area 7 are not designated as a reserved area, but are equivalent to the p4 area control register area in the physical address space. virt ual address space is illustrated in figure 3.6. area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external memory space 256 256 u0 area cacheable address translation possible address error address error store queue area p0 area cacheable address translation possible user mode privileged mode p1 area cacheable address translation not possible p2 area non-cacheable address translation not possible p3 area cacheable address translation possible p4 area non-cacheable address translation not possible figure 3.6 virtual add ress space (mmucr.at = 1) in the state of cache enabling, wh en the areas of p0, p3, and u0 are mapped onto the area of the pcmcia interface by means of the tlb, it is necessa ry either to specify 1 for the wt bit or to specify 0 for the c bit on that pa ge. at that time, the regions are accessed by the values of sa and tc set in page units of the tlb.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 76 of 1122 rej09b0370-0400 here, access to an area of the pcmcia interface by accessing an area of p1, p2, or p4 from the cpu is disabled. in addition, the pcmcia inte rface is always accessed by the dmac with the values of chcrn, ssan, chcrn.dsan, chcrn.stc and chcrn.dtc in the dmac. for details, see section 14, direct memory access co ntroller (dmac). p0, p3, u0 areas: the p0 area (excluding addresses h'7c 00 0000 to h'7fff ffff), p3 area, and u0 area (excluding addresses h'7c00 0000 to h'7fff ffff) allow access using the cache and address translation using the tlb. these areas can be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-mbyt e, page units. when ccr is in the cache-enabled state and the cacheability bit (c bit) in the tlb is 1, accesses can be performed using the cache. in write accesses to the cache, switching be tween the copy-back method and the write-throug h method is indicated by the tlb write-through bit (wt bit), and is specified in page units. only when the p0, p3, and u0 areas are mapped onto external memory space by means of the tlb, addresses h'1c00 0000 to h'1fff ffff of area 7 in external memory space are allocated to the control register area. this enables control registers to be accessed from the u0 area in user mode. in this case, the c bit for the corresponding page must be cleared to 0. p1, p2, p4 areas: address translation using the tlb cannot be performed for the p1, p2, or p4 area (except for the store queue area). accesses to these areas are the same as for physical address space. the store queue area can be mapped on to any external memory space by the mmu. however, operation in the case of an exception di ffers from that for norma l p0, u0, and p3 spaces. for details, see section 4.7, store queues. 3.3.4 on-chip ram space in the sh-4, half of the operand cache can be used as on-chip ram. this can be done by changing the ccr settings. when the operand cache is used as on-chip ra m (ccr.ora = 1), p0, u0 area addresses h'7c00 0000 to h'7fff ffff are an on-chip ram area. data accesses (byte/word/longword/quadword) can be used in this area. this area can only be used in ram mode. 3.3.5 address translation when the mmu is used, the virtual address space is divided into units called pages, and translation to physical ad dresses is carried out in these page units. the address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. fast address translation is achieved by caching the contents of the address translation table located in external memory into the tlb. in the sh-4, basically, the itlb is used for instruction accesse s and the utlb for data accesses. in the event
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 77 of 1122 rej09b0370-0400 of an access to an area other than the p4 area, the accessed virtual address is translated to a physical address. if the virtual address belongs to the p1 or p2 area, the physical address is uniquely determined without accessing the tlb. if th e virtual address belongs to the p0, u0, or p3 area, the tlb is searched using the virtual address, and if the virtual address is recorded in the tlb, a tlb hit is made and the corresponding physical address is read from the tlb. if the accessed virtual address is not recorded in th e tlb, a tlb miss exception is generated and processing switches to the tlb miss exception handling routine. in the tlb miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the tlb. after the return from the exception handling routine, the instruction which caused the tlb miss exception is re-executed. 3.3.6 single virtual memory mode and multiple virtual memory mode there are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the mmucr.sv bit. in the single vi rtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. in the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. the only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the tlb address comparison method (see section 3.4.3, address translation method). 3.3.7 address space identifier (asid) in multiple virtual memory mode, the 8-bit address space identifier (asid) is used to distinguish between processes running simulta neously while sharing the virtua l address space. software can set the asid of the currently executing process in pteh in the mmu. the tlb does not have to be purged when processes are switched by means of asid. in single virtual memory mode, asid is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. notes: 1. in single virtual memory mode of the sh-4, entries with the same virtual page number (vpn) but different asids cannot be set in the tlb simultaneously. 2. when the sh7751 is operating in single virtual memory mode and user mode, the lsi may hang during hardware itlb miss handling (see section 3.5.4, hardware itlb miss handling), or an itlb multiple hit excep tion may occur, if an itlb miss occurs and the utlb contains address translation information including an itlb miss address
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 78 of 1122 rej09b0370-0400 with a different asid and unshared state (sh bit is 0). to avoid this, use workaround (1) or (2) below. (1) purge the utlb when switching the asid values (pteh and asid) of the current processing. (2) manage the behavior of program instruction addresses in user mode so that no instruction is executed in an address area (including overrun prefetch of an instruction) that is registered in the utlb with a different asid and unshared address translation information. note th at accessing a different asid in single virtual memory mode can only be used to trigger an exception during data access. 3.4 tlb functions 3.4.1 unified tlb (utlb) configuration the unified tlb (utlb) is so called because of its use for the following two purposes: 1. to translate a virtual address to a physical address in a data access 2. as a table of address translation information to be recorded in the inst ruction tlb in the event of an itlb miss information in the address translation table located in external memory is cached into the utlb. the address translation table contains virtual page numbers and addre ss space identifiers, and corresponding physical page numbers and page management information. figure 3.7 shows the overall configuration of the utlb. the utlb consis ts of 64 fully-associative type entries. figure 3.8 shows the relationship between the address format and page size. ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc sa [2:0] tc asid [7:0] vpn [31:10] v entry 63 d wt figure 3.7 utlb configuration
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 79 of 1122 rej09b0370-0400 31 ? 1-kbyte pa g e 10 9 0 virtual address 31 ? 4-kbyte pa g e 12 11 0 virtual address 31 ? 64-kbyte pa g e 16 15 0 virtual address 31 ? 1-mbyte pa g e 20 19 0 virtual address vpn offset vpn offset vpn offset vpn offset 28 10 9 0 physical address 28 12 11 0 physical address 28 16 15 0 physical address 28 20 19 0 physical address ppn offset ppn offset ppn offset ppn offset figure 3.8 relationship between page size and address format ? vpn: virtual page number for 1-kbyte page: upper 22 bits of virtual address for 4-kbyte page: upper 20 bits of virtual address for 64-kbyte page: upper 16 bits of virtual address for 1-mbyte page: upper 12 bits of virtual address ? asid: address space identifier indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, this identifier is compared with th e asid in pteh when address comparison is performed.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 80 of 1122 rej09b0370-0400 ? sh: share status bit when 0, pages are not shared by processes. when 1, pages are shared by processes. ? sz: page size bits specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-mbyte page ? v: validity bit indicates whether the entry is valid. 0: invalid 1: valid cleared to 0 by a power-on reset. not affected by a manual reset. ? ppn: physical page number upper 22 bits of the physical address. with a 1-kbyte page, ppn bits [28:10] are valid. with a 4-kbyte page, ppn bits [28:12] are valid. with a 64-kbyte page, ppn bits [28:16] are valid. with a 1-mbyte page, ppn bits [28:20] are valid. the synonym problem must be taken into account when setting the ppn (see section 3.5.5, avoiding synonym problems). ? pr: protection key data 2-bit data expressing the page access right as a code. 00: can be read only, in privileged mode 01: can be read and written in privileged mode 10: can be read only, in privileged or user mode 11: can be read and written in privileged mode or user mode
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 81 of 1122 rej09b0370-0400 ? c: cacheability bit indicates whether a page is cacheable. 0: not cacheable 1: cacheable when control register space is mapped , this bit must be cleared to 0. when performing pcmcia space mapping in the cach e enabled state, either clear this bit to 0 or set the wt bit to 1. ? d: dirty bit indicates whether a write has been performed to a page. 0: write has not been performed 1: write has been performed ? wt: write-through bit specifies the cache write mode. 0: copy-back mode 1: write-through mode when performing pcmcia space mapping in the cache enabled state, either set this bit to 1 or clear the c bit to 0. ? sa: space attribute bits valid only when the page is mapped onto pcmcia connected to area 5 or 6. 000: undefined 001: variable-size i/o space (base size according to iois16 signal) 010: 8-bit i/o space 011: 16-bit i/o space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space ? tc: timing control bit used to select wait control register bits in the bus control unit for areas 5 and 6. 0: wcr2 (a5w2?a5w0) and pcr (a5pcw1?a5pcw0, a5ted2?a5ted0, a5teh2? a5teh0) are used 1: wcr2 (a6w2?a6w0) and pcr (a6pcw1?a6pcw0, a6ted2?a6ted0, a6teh2? a6teh0) are used
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 82 of 1122 rej09b0370-0400 3.4.2 instruction tlb (itlb) configuration the itlb is used to translate a virtual address to a physical ad dress in an instruction access. information in the address translation table located in the utlb is cached into the itlb. figure 3.9 shows the overall configuration of the itlb. th e itlb consists of 4 fully-associative type entries. the address translation information is almo st the same as that in the utlb, but with the following differences: 1. d and wt bits are not supported. 2. there is only one pr bit, corresponding to the upper of the pr bits in the utlb. ppn [28:10] ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sz [1:0] sh sh sh sh c c c c pr pr pr pr asid [7:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] vpn [31:10] v v v v entry 0 entry 1 entry 2 entry 3 sa [2:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc tc figure 3.9 itlb configuration 3.4.3 address translation method figures 3.10 and 3.11 show flowcharts of memory accesses using the utlb and itlb.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 83 of 1122 rej09b0370-0400 mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match and asids match and v = 1 only one entry matches sr.md? ccr.oce? ccr.cb? ccr.wt? vpns match and v = 1 cache access in write-through mode memory access pr? data tlb multiple hit exception data tlb protection violation exception data tlb miss exception initial page write exception data tlb protection violation exception cache access in copy-back mode data access to virtual address (va) on-chip i/o access r/w? r/w? va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area yes no 1 0 yes yes no no yes yes yes no no 1 (privileged) 1 0 0 pr? 0 (user) d? r/w? w w w r r rr w r/w? (non-cacheable) wt? c = 1 and ccr.oce = 1 no 1 1 0 0 00 or 01 10 11 01 or 11 00 or 10 figure 3.10 flowchart of memory access using utlb
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 84 of 1122 rej09b0370-0400 mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match and asids match and v = 1 only one entry matches sr.md? ccr.ice? vpns match and v = 1 memory access instruction tlb multiple hit exception instruction tlb miss exception instruction access to virtual address (va) va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area yes no 1 0 yes yes no no yes yes no (non-cacheable) c = 1 and ccr.ice = 1 no pr? instruction tlb protection violation exception match? record in itlb access prohibited 0 1 no yes yes no hardware itlb miss handling 0 (user) 1 (privileged) search utlb cache access figure 3.11 flowchart of memory access using itlb
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 85 of 1122 rej09b0370-0400 3.5 mmu functions 3.5.1 mmu hardware management the sh-4 supports the following mmu functions. 1. the mmu decodes the virtual address to be accessed by software, and performs address translation by controlling the utlb/itlb in accordance with the mmucr settings. 2. the mmu determines the cache access status on the basis of the page management information read during address translation (c, wt, sa, and tc bits). 3. if address translation cannot be performed normally in a data access or instruction access, the mmu notifies software by m eans of an mmu exception. 4. if address translation information is not recorded in the itlb in an instruction access, the mmu searches the utlb, and if the necessary address translati on information is recorded in the utlb, the mmu copies this informa tion into the itlb in accordance with mmucr.lrui. 3.5.2 mmu software management software processing for the mm u consists of the following: 1. setting of mmu-related registers. some registers are also partially updated by hardware automatically. 2. recording, deletion, and reading of tlb entries. there are two methods of recording utlb entries: by using the ldtlb instruction, or by writing directly to the memory-mapped utlb. itlb entries can only be recorded by writing directly to the memory-mapped itlb. for deleting or reading utlb/itlb entries, it is possible to access the memory-mapped utlb/itlb. 3. mmu exception handling. when an mmu exception occurs, processing is performed based on information set by hardware. 3.5.3 mmu instruction (ldtlb) a tlb load instruction (ldtlb) is provided for recording utlb entries. when an ldtlb instruction is issued, the sh-4 copies the contents of pteh, p tel, and ptea to the utlb entry indicated by mmucr.urc. itlb entries are not upd ated by the ldtlb instruction, and therefore address translation information purged from the utlb entry may still remain in the itlb entry. as the ldtlb instruction changes address translation information, ensure that it is
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 86 of 1122 rej09b0370-0400 issued by a program in the p1 or p2 area. the operation of the ldtlb instruction is shown in figure 3.12. ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc sa [2:0] tc asid [7:0] vpn [31:10] v entry 63 d wt 31 29 28 9 8 7 65 4 3 2 1 0 ??vszprszcdsh wt ptel write utlb 31 10 98 70 ? asid pteh 31 26 25 24 23 18 17 16 15 10 9 8 73 2 1 0 lrui ? urb ? urc sv sqmd ?ti?at mmucr vpn 10 ppn 31 4 32 0 ?sa tc ptea entry specification figure 3.12 operation of ldtlb instruction 3.5.4 hardware itlb miss handling in an instruction access, the sh-4 searches the itlb. if it cannot find the necessary address translation information (i.e. in the event of an i tlb miss), the utlb is searched by hardware, and if the necessary address translation information is present, it is recorded in the itlb. this procedure is known as hardware itlb miss handling. if the necessary address translation
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 87 of 1122 rej09b0370-0400 information is not found in the utlb search, an instruction tlb miss exception is generated and processing passes to software. 3.5.5 avoiding synonym problems when 1- or 4-kbyte pages are recorded in tl b entries, a synonym pr oblem may arise. the problem is that, when a number of virtual addres ses are mapped onto a single physical address, the same physical address data is r ecorded in a number of cache entr ies, and it becomes impossible to guarantee data integrity. this problem does not occur with the instruction tlb or instruction cache. in the sh-4 , entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operatio n. however, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4-kbyte page, are subject to address translation. as a result, bits [13:10] of the physical ad dress after translation may differ from bits [13:10] of the virtual address. consequently, the following restrictions apply to the recording of address translation information in utlb entries. 1. when address translation information whereby a number of 1-kbyte page utlb entries are translated into the same physical address is recorded in the u tlb, ensure that the vpn [13:10] values are the same. 2. when address translation information whereby a number of 4-kbyte page utlb entries are translated into the same physical address is recorded in the u tlb, ensure that the vpn [13:12] values are the same. 3. do not use 1-kbyte page utlb entry physical addresses with utlb entries of a different page size. 4. do not use 4-kbyte page utlb entry physical addresses with utlb entries of a different page size. the above restrictions apply only when performing accesses us ing the cache. when cache index mode is used, vpn [25] is used for the entry ad dress instead of vpn [13] , and therefore the above restrictions apply to vpn [25]. note: when multiple items of address translation information use the same physical memory to provide for future superh risc engine family expansion, ensure that the vpn [20:10] values are the same. also, do not use the sa me physical address for address translation information of different page sizes.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 88 of 1122 rej09b0370-0400 3.6 mmu exceptions there are seven mmu exceptions: the instruction tlb multiple hit exception, instruction tlb miss exception, instruction tlb protection violation exception, data tlb multiple hit exception, data tlb miss exception, data tlb protection violation exception, and initial page write exception. refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 instruction tlb mu ltiple hit exception an instruction tlb multiple hit exception occurs when more than one itlb entry matches the virtual address to which an inst ruction access has been made. if multiple hits occur when the utlb is searched by hardware in hardware itlb miss handling, a data tlb multiple hit exception will result. when an instruction tlb multiple hit exception occu rs a reset is executed, and cache coherency is not guaranteed. hardware processing: in the event of an instruction tlb mu ltiple hit exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000). software processing (reset routine): the itlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated. 3.6.2 instruction tlb miss exception an instruction tlb miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in th e utlb entries by the hardware itlb miss handling procedure. the instruction tlb miss exceptio n processing carried out by hardware and software is shown below. this is the same as the processing for a data tlb miss exception.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 89 of 1122 rej09b0370-0400 hardware processing: in the event of an instruction tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in expevt. 4. sets the pc value indicating the address of th e instruction at which the exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the instruction tlb miss exception handling routine. software processi ng (instruction tlb miss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following pro cessing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address tr anslation table. if necessary, the values of the sa and tc bits should be written to ptea. 2. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 3. execute the ldtlb instruction and write the contents of pteh, ptel, and ptea to the tlb. 4. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.3 instruction tlb protection violation exception an instruction tlb protection violation exception occurs when, even though an itlb entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitte d by the access right speci fied by the pr bit.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 90 of 1122 rej09b0370-0400 the instruction tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of an instruction tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in expevt. 4. sets the pc value indicating the address of the instruction at which the exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. set the current r15 value in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the instruction tlb protection violation exception handling routine. software processing (instruc tion tlb protection violation exception handling routine): resolve the instruction tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, an d return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.4 data tlb multiple hit exception a data tlb multiple hit exception occurs when more than one utlb entry matches the virtual address to which a data access has been made. a da ta tlb multiple hit exception is also generated if multiple hits occur when the utlb is searched in hardware itlb miss handling. when a data tlb multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. the contents of ppn in the utlb prior to the exception may also be corrupted. hardware processing: in the event of a data tlb multiple hit exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000).
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 91 of 1122 rej09b0370-0400 software processing (reset routine): the utlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated. 3.6.5 data tlb miss exception a data tlb miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the utlb entries. the data tlb miss exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in the case of a re ad, or h'060 in the case of a write, in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the excep tion in ssr, and sets the r15 contents at the time in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the data tlb miss exception handling routine. software processing (data tlb miss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following processing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address tr anslation table. if necessary, the values of the sa and tc bits should be written to ptea. 2. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 92 of 1122 rej09b0370-0400 3. execute the ldtlb instruction and write th e contents of pteh, ptel, and ptea to the utlb. 4. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.6 data tlb protection violation exception a data tlb protection violation exception occurs when, even though a utlb entry contains address translation information ma tching the virtual address to which a data access is made, the actual access type is not permitted by the access ri ght specified by the pr bit. the data tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in the case of a re ad, or h'0c0 in the case of a write, in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of the instruction at which the exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the data tlb protection violation exception handling routine. software processing (data tlb protection violation exception handling routine): resolve the data tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 93 of 1122 rej09b0370-0400 3.6.7 initial page write exception an initial page write exception occurs when the d bit is 0 even though a utlb entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. the initial pa ge write exception pro cessing carried out by hardware and software is shown below. hardware processing: in the event of an initial page write exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'080 in expevt. 4. sets the pc value indicating the address of th e instruction at which the exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the initial page write exception handling routine. software processing (initial page write exception handling routine): the following processing should be carried out as the responsibility of software: 1. retrieve the necessary page table entry from external memory. 2. write 1 to the d bit in the external memory page table entry. 3. write to ptel the values of the ppn, pr, sz, c, d, wt, sh, and v bits in the page table entry recorded in external memo ry. if necessary, the values of the sa and tc bits should be written to ptea. 4. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 5. execute the ldtlb instruction and write th e contents of pteh, ptel, and ptea to the utlb.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 94 of 1122 rej09b0370-0400 6. finally, execute the exception handling retu rn instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.7 memory-mapped tlb configuration to enable the itlb and utlb to be managed by software, their contents can be read and written by a p2 area program with a mov instruction in privileged mode. operation is not guaranteed if access is made from a program in the other area. a br anch to an area other than the p2 area should be made at least 8 instructions after this mov instruction. the itlb and utlb are allocated to the p4 area in physical address space. vpn, v, and asid in the itlb can be accessed as an address array, ppn, v, sz, pr, c, and sh as data array 1, and sa and tc as data array 2. vpn, d, v, and asid in the utlb can be accessed as an address array, ppn, v, sz, pr, c, d, wt, and sh as data array 1, and sa and tc as data arra y 2. v and d can be accessed from both the address array side and the data array side. only longword access is possible. instruction fetches cannot be performed in these areas. for reserved bits, a write value of 0 should be sp ecified; their read value is undefined. 3.7.1 itlb address array the itlb address array is allocated to addresses h'f200 0000 to h'f2ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). information for selecting the entry to be accessed is specified in the address field, and vpn, v, an d asid to be written to the address array are specified in the data field. in the address field, bits [31:24] have the valu e h'f2 indicating the itlb address array, and the entry is selected by bits [9:8]. as longword acce ss is used, 0 should be specified for address field bits [1:0]. in the data field, vpn is indicated by bits [31:10], v by bit [8], and asid by bits [7:0]. the following two kinds of operation can be used on the itlb address array: 1. itlb address array read vpn, v, and asid are read into the data field from the itlb entry corr esponding to the entry set in the address field. 2. itlb address array write vpn, v, and asid specified in the data field are written to the itlb entry corresponding to the entry set in the address field.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 95 of 1122 rej09b0370-0400 address field 31 23 0 11110010 e data field 31 10 9 0 v vpn legend: vpn: v: e: 24 virtual page number validity bit entry 10 987 987 asid asid: : address space identifier reserved bits (0 write value, undefined read value) figure 3.13 memory-mapped itlb address array 3.7.2 itlb data array 1 itlb data array 1 is allocated to addresses h'f3 00 0000 to h'f37f ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, and sh to be written to the data array are specified in the data field. in the address field, bits [31:23] have the value h'f30 indicating itlb data array 1, and the entry is selected by bits [9:8]. in the data field, ppn is indicated by bits [28:10], v by bit [8], sz by bits [7] and [4], pr by bit [6], c by bit [3], and sh by bit [1]. the following two kinds of operation can be used on itlb data array 1: 1. itlb data array 1 read ppn, v, sz, pr, c, and sh are read into the data field from the itlb entry corresponding to the entry set in the address field. 2. itlb data array 1 write ppn, v, sz, pr, c, and sh specified in the data field are written to the itlb entry corresponding to the entry set in the address field.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 96 of 1122 rej09b0370-0400 address field 31 23 0 111100 0 11 e data field legend: ppn: v: e: sz: 24 physical page number validity bit entry page size bits 10 987 pr: c: sh: : protection key data cacheability bit share status bit reserved bits (0 write value, undefined read value) 31 210 v 10 9 8 7 30 29 28 43 65 sz sh pr c ppn figure 3.14 memory-mapped itlb data array 1 3.7.3 itlb data array 2 itlb data array 2 is allocated to addresses h'f3 80 0000 to h'f3ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, and sa and tc to be written to data array 2 are specified in the data field. in the address field, bits [31:23] have the value h'f38 indicating itlb data array 2, and the entry is selected by bits [9:8]. in the data field, sa is indicated by bits [2:0], and tc by bit [3]. the following two kinds of operation can be used on itlb data array 2: 1. itlb data array 2 read sa and tc are read into the data field from the itlb entry corresponding to the entry set in the address field. 2. itlb data array 2 write sa and tc specified in the data field are writte n to the itlb entry corresponding to the entry set in the address field.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 97 of 1122 rej09b0370-0400 address field 31 23 0 11110011 1e data field 31 4 0 legend: tc: e: 24 timing control bit entry 8 9 7 32 sa: : space attribute bits reserved bits (0 write value, undefined read value) 10 sa tc figure 3.15 memory-mapped itlb data array 2 3.7.4 utlb address array the utlb address array is allocated to addresses h'f600 0000 to h'f6ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). information for selecting the entry to be accessed is specified in the address field, an d vpn, d, v, and asid to be written to the address array are specified in the data field. in the address field, bits [31:24] have the valu e h'f6 indicating the utlb address arra y, and the entry is selected by bits [13:8]. the address array bit [7] association bit (a bit) specifies whether or not address comparison is performed when writing to the utlb address array. in the data field, vpn is indicated by bits [31:10], d by bit [9], v by bit [8], and asid by bits [7:0]. the following three kinds of operation can be used on the utlb address array: 1. utlb address array read vpn, d, v, and asid are read into the data field from the utlb entry corresponding to the entry set in the address field. in a read, asso ciative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. utlb address array write (non-associative) vpn, d, v, and asid specified in the data field are written to the utlb entry corresponding to the entry set in the address field. the a bi t in the address field should be cleared to 0. 3. utlb address array write (associative)
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 98 of 1122 rej09b0370-0400 when a write is performed with the a bit in the address field set to 1, comparison of all the utlb entries is carried out us ing the vpn specified in the da ta field and pteh.asid. the usual address comparison rules are followed, but if a utlb miss occurs, the result is no operation, and an exception is not generated. if the comparison identifies a utlb entry corresponding to the vpn specified in the data field, d and v specified in the data field are written to that entry. if there is more than one matching entry, a data tlb multiple hit exception results. this asso ciative operation is simultaneously carried out on the itlb, and if a matching entry is found in the itlb, v is written to that entry. even if the utlb comparison results in no operation, a write to the itlb side only is performed as long as there is an itlb match. if there is a match in both the utlb and itlb, the utlb information is also written to the itlb. address field data field legend: vpn: v: e: d: virtual page number validity bit entry dirty bit asid: a: : address space identifier association bit reserved bits (0 write value, undefined read value) 31 0 v d 10 987 30 29 28 a 87 asid vpn 31 23 2 1 0 11110110 e 24 14 13 figure 3.16 memory-mapped utlb address array 3.7.5 utlb data array 1 utlb data array 1 is allocated to addresses h'f700 0000 to h'f77f ffff in the p4 area. a data array access requires a 32-bit address field speci fication (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, d, sh, and wt to be written to the data array are specified in the data field. in the address field, bits [31:23] have the value h'f70 indicating utlb data array 1, and the entry is selected by bits [13:8]. in the data field, ppn is indicated by bits [28:10], v by bit [8], sz by bits [7] and [4], pr by bits [6:5], c by bit [3], d by bit [2], sh by bit [1], and wt by bit [0]. the following two kinds of operation can be used on utlb data array 1:
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 99 of 1122 rej09b0370-0400 1. utlb data array 1 read ppn, v, sz, pr, c, d, sh, and wt are read into the data field from the utlb entry corresponding to the entry set in the address field. 2. utlb data array 1 write ppn, v, sz, pr, c, d, sh, and wt specified in the data field are written to the utlb entry corresponding to the entry set in the address field. address field data field legend: ppn: v: e: sz: d: physical page number validity bit entry page size bits dirty bit pr: c: sh: wt: : protection key data cacheability bit share status bit write-through bit reserved bits (0 write value, undefined read value) 31 210 v 10987 30 29 28 43 65 pr c ppn 31 23 0 11110111 0 e 24 87 14 13 d sz sh wt figure 3.17 memory-mapped utlb data array 1 3.7.6 utlb data array 2 utlb data array 2 is allocated to addresses h'f780 0000 to h'f7ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, and sa and tc to be written to data array 2 are specified in the data field. in the address field, bits [31:23] have the value h'f78 indicating utlb data array 2, and the entry is selected by bits [13:8]. in the data field, tc is indicated by bit [3], and sa by bits [2:0]. the following two kinds of operation can be used on utlb data array 2: 1. utlb data array 2 read sa and tc are read into the data field from the utlb entry corresponding to the entry set in the address field.
3. memory management unit (mmu) rev.4.00 oct. 10, 2008 page 100 of 1122 rej09b0370-0400 2. utlb data array 2 write sa and tc specified in the data field are writte n to the utlb entry corresponding to the entry set in the address field. address field 31 23 0 11110111 1e data field 31 4 0 tc 24 8 13 7 32 14 sa legend: tc: e: timing control bit entry sa: : space attribute bits reserved bits (0 write value, undefined read value) figure 3.18 memory-mapped utlb data array 2 3.8 usage notes 1. address space identifier (asid) in single virtual memory mode refer to the note in 3.3.7, address space iden tifier (asid).
4. caches rev.4.00 oct. 10, 2008 page 101 of 1122 rej09b0370-0400 section 4 caches 4.1 overview 4.1.1 features the sh7751 has an on-chip 8-kbyte instruction cache (ic) for instructions and 16-kbyte operand cache (oc) for data. half of the memory of the ope rand cache (8 kbytes) can also be used as on- chip ram. the features of these cach es are summarized in table 4.1. the sh7751 has an on-chip 16-kbyte instruction cache (ic) for instructions and 32-kbyte operand cache (oc) for data. half of the operand cache memory (16 kbytes) can also be used as on-chip ram. when the emode bit in the ccr register is cleared to 0 in the sh7751r, both the ic and oc are set to sh7751 compatible mode. when the emode bit in the ccr register is set to 1, the cache charact eristics are as shown in table 4.2. afte r a power-on reset or manual reset, the initial value of the emode bit is 0. this lsi supports two 32-byte store queues (sqs) for performing high-speed writes to external memory. sq features are shown in table 4.3. table 4.1 cache features (sh7751) item instruction cache operand cache capacity 8-kbyte cache 16-kbyt e cache or 8-kbyte cache + 8-kbyte ram type direct mapping direct mapping line size 32 bytes 32 bytes entries 256 entry 512 entry write method copy-back/write-through selectable
4. caches rev.4.00 oct. 10, 2008 page 102 of 1122 rej09b0370-0400 table 4.2 cache features (sh7751r) item instruction cache operand cache capacity 16-kbyte cache 32-kbyt e cache or 16-kbyte cache + 16-kbyte ram type 2-way set-associative 2-way set-associative line size 32 bytes 32 bytes entries 256 entry/way 512 entry/way write method copy-back/write-through selectable replace method lru (least recently used) algorithm lru (least recently used) algorithm table 4.3 store queue features item store queues capacity 2 32 bytes addresses h'e000 0000 to h'e3ff ffff write store instruct ion (1-cycle write) write-back prefetch instru ction (pref instruction) access right mmu off: a ccording to mmucr.sqmd mmu on: according to individual page pr 4.1.2 register configuration table 4.4 shows the cache control registers. table 4.4 cache control registers name abbreviation r/w initial value * 1 p4 address * 2 area 7 address * 2 access size cache control register ccr r/w h'0000 0000 h'ff 00 001c h'1f00 001c 32 queue address control register 0 qacr0 r/w undefined h'ff00 0038 h'1f00 0038 32 queue address control register 1 qacr1 r/w undefined h 'ff00 003c h'1f00 003c 32 notes: 1. the initial value is the value after a power-on or manual reset. 2. p4 address is the address when using the virtual/physical address space p4 area. the area 7 address is the address used when making an access from physical address space area 7 using the tlb.
4. caches rev.4.00 oct. 10, 2008 page 103 of 1122 rej09b0370-0400 4.2 register descriptions there are three cache and store queue related co ntrol registers, as shown in figure 4.1. ccr 31 14 16 30 15 12111098765432 cb 10 ici ice ora oix oci area notes: indicates reserved bits: 0 must be specified in a write; the read value is 0. * sh7751r only wt oce iix emode * qacr0 31 54 210 area qacr1 31 54 210 figure 4.1 cache and store queue control registers (ccr) (1) cache control register (ccr): ccr contains the following bits: emode: cache-double-mode (sh7751r only. reserved bit in sh7751.) iix: ic index enable ici: ic invalidation ice: ic enable oix: oc index enable ora: oc ram enable oci: oc invalidation cb: copy-back enable wt: write-through enable oce: oc enable ccr can be accessed by longword-size access from h'ff00001c in the p4 area and h'1f00001c in area 7. the ccr bits are used for the cache settings described below. consequently, ccr modifications must only be made by a program in the non-cached p2 area. after ccr is updated, an instruction that performs data access to the p0 , p1, p3, or u0 area shou ld be located at least
4. caches rev.4.00 oct. 10, 2008 page 104 of 1122 rej09b0370-0400 four instructions after the ccr update instruction. also, a branch instruction to the p0, p1, p3, or u0 area should be located at least eight in structions after the ccr update instruction. ? emode: cache-do uble-mode bit indicates whether or not cache-double-mode is used in the sh7751r. this bit is reserved in the sh7751. the emode bit cannot be modi fied while the cache is in use. 0: sh7751-compatible-mode* 1 (initial value) 1: cache-double-mode note: 1. address allocation in oc index mode and ram mode is not compatible with that in ram mode. ? iix: ic index enable bit 0: effective address bits [12:5] used for ic entry selection 1: effective address bits [25] and [11:5] used for ic entry selection ? ici: ic invalidation bit when 1 is written to this bit, the v bits of all ic entries are cleared to 0. this bit always returns 0 when read. ? ice: ic enable bit indicates whether or not the ic is to be used. when address translation is performed, the ic cannot be used unless the c bit in the page management information is also 1. 0: ic not used 1: ic used ? oix: oc index enable bit* 2 0: effective address bits [13:5] used for oc entry selection 1: effective address bits [25] and [12:5] used for oc entry selection note: 2. in the sh7751r, clear the oix bit to 0 when the ora bit is 1. ? ora: oc ram enable bit* 3 when the oc is enabled (oce = 1), the ora bit sp ecifies whether the half of the oc are to be used as ram. when the oc is not enabled (oce = 0), the ora bit should be cleared to 0. 0: normal mode (the entire oc is used as a cache) 1: ram mode (half of the oc is used as a cache and the other half is used as ram) note: 3. in the sh7751r, clear the ora bit to 0 when the oix bit is 1.
4. caches rev.4.00 oct. 10, 2008 page 105 of 1122 rej09b0370-0400 ? oci: oc invalidation bit when 1 is written to this bit, the v and u bits of all oc entries are cleared to 0. this bit always returns 0 when read. ? cb: copy-back bit indicates the p1 area cache write mode. 0: write-through mode 1: copy-back mode ? wt: write-through bit indicates the p0, u0, and p3 area cache write mode. when address tran slation is performed, the value of the wt bit in the page management information has priority. 0: copy-back mode 1: write-through mode ? oce: oc enable bit indicates whether or not the oc is to be used. when address translation is performed, the oc cannot be used unless the c bit in the page management information is also 1. 0: oc not used 1: oc used (2) queue address control register 0 (qacr0): qacr0 can be accessed by longword-size access from h'ff000038 in the p4 area and h'1f000038 in area 7. qacr0 specifies the area onto which store queue 0 (sq0) is mapped when the mmu is off. (3) queue address control register 1 (qacr1): qacr1 can be accessed by longword-size access from h'ff00003c in the p4 area and h'1f000 03c in area 7. qacr1 sp ecifies the area onto which store queue 1 (sq1) is mapped when the mmu is off. 4.3 operand cache (oc) 4.3.1 configuration the operand cache in th e sh7751 adopts the direct-mapping method, and consists of 512 cache lines. each cache line is composed of a 19-bit tag, v bit, u bit, and 32-byte data. the operand cache in the sh7751r adopts the 2-way set-asso ciative method, and each way consists of 512 cache lines.
4. caches rev.4.00 oct. 10, 2008 page 106 of 1122 rej09b0370-0400 figure 4.2 shows the configuration of the operand cache in the sh7751. figure 4.3 shows the configuration of the operand cache in the sh7751r. 31 26 25 5 4 3 2 1 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits mmu ram area determination ora oix [13] [12] [11:5] 511 19 bits 1 bit 1 bit ta g uv address array data array entry selection lon g word (lw) selection effective address 3 9 22 19 0 write data read data hit si g nal compare 13 12 11 10 9 0 figure 4.2 configuratio n of operand cache (sh7751)
4. caches rev.4.00 oct. 10, 2008 page 107 of 1122 rej09b0370-0400 31 26 25 5 4 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 1 bit mmu ram area determination oix ora [13] [12:5] 511 19 bits 1 bit 1 bit ta g uv address array (way 0, way 1) data array (way 0, way 1) lru entry selection lon g word (lw) selection effective address 3 9 22 19 0 write data read data hit si g nal compare way-0 compare way-1 13 12 10 0 figure 4.3 configuration of operand cache (sh7751r) ? tag stores the upper 19 bits of the 29-bit external ad dress of the data line to be cached. the tag is not initialized by a power-on or manual reset. ? v bit (validity bit) indicates that valid data is stored in the cache lin e. when this bit is 1, the cache line data is valid. the v bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
4. caches rev.4.00 oct. 10, 2008 page 108 of 1122 rej09b0370-0400 ? u bit (dirty bit) the u bit is set to 1 if data is written to the cache line while the cache is being used in copy- back mode. that is, the u bit i ndicates a mismatch between the data in the cache line and the data in external memory. the u bit is never set to 1 while the cache is being used in write- through mode, unless it is modified by accessi ng the memory-mapped cache (see section 4.5, memory-mapped cache configuration (sh7 751) and 4.6, memory-mapped cache configuration (sh7751r)). the u bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. ? data field the data field holds 32 bytes (256 bits) of data per cache line. the data array is not initialized by a power-on or manual reset. ? lru (sh7751r only) in a 2-way set-associative system, up to two en try addresses can register the same data in cache. the lru bit indicates to which way the en try is to be register ed among the two ways. there is one lru bit in each entry, and it is controlled by hardware. the lru (last recently used) algorithm that selects the most recentl y accessed way is used for way selection. the lru bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. the lru bit cannot be read from or written to by software. 4.3.2 read operation when the oc is enabled (ccr.oce = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. the tag, v bit, and u bit are read from the cache line indexed by effective address bits [13:5]. 2. the tag is compared with bits [28:10] of the address resulting fr om effective address translation by the mmu: ? if the tag matches and the v bit is 1 (3a) ? if the tag matches and the v bit is 0 (3b) ? if the tag does not match and the v bit is 0 (3b) ? if the tag does not match, the v bit is 1, and the u bit is 0 (3b) ? if the tag does not match, the v bit is 1, and the u bit is 1 (3c) 3a. cache hit the data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13: 5] in accordance with the access size (quadword/longword/word/byte).
4. caches rev.4.00 oct. 10, 2008 page 109 of 1122 rej09b0370-0400 3b. cache miss (no write-back) data is read into the cache line from the extern al memory space corresp onding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the cpu. while the remaining one cache line of data is being read, the cpu can execute the next processing. wh en reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the v bit. 3c. cache miss (with write-back) the tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. then data is read into the cache line from the external memory space corresponding to the effective address. data reading is pe rformed, using the wraparound method, in order from the longword data correspo nding to the effective address, and when the corresponding data arrives in the cache, the read data is re turned to the cpu. while the remaining one cache line of data is being read, the cpu can execute the next processing. when reading of one line of data is completed, th e tag corresponding to th e effective address is recorded in the cache, 1 is writte n to the v bit, and 0 to the u bi t. the data in the write-back buffer is then written back to external memory. 4.3.3 write operation when the oc is enabled (ccr.oce = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. the tag, v bit, and u bit are read from the cache line indexed by effective address bits [13:5]. 2. the tag is compared with bits [28:10] of the address resulting fr om effective address translation by the mmu: copy-back write-through ? if the tag matches and the v bit is 1 (3a) (3b) ? if the tag matches and the v bit is 0 (3c) (3d) ? if the tag does not match and the v bit is 0 (3c) (3d) ? if the tag does not match, the v bit is 1, and the u bit is 0 (3c) (3d) ? if the tag does not match, the v bit is 1, and the u bit is 1 (3e) (3d) 3a. cache hit (copy-back) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data indexed by bits [4:0] of the effect ive address and the data field of the cache line indexed by effective address bits [13:5]. then 1 is set in the u bit.
4. caches rev.4.00 oct. 10, 2008 page 110 of 1122 rej09b0370-0400 3b. cache hit (write-through) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. a write is also performed to th e corresponding external memory using the specified access size. 3c. cache miss (copy-back/no write-back) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data field indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. then, data is read into the cache line from th e external memory space corresponding to the effective address. data reading is pe rformed, using the wraparound method, in order from th e longword data corresponding to the effective address, and one cache line of data is read excluding the written data. during this time, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the v bit and u bit. 3d. cache miss (write-through) a write of the specified access size is performed to the external memory corresponding to the effective address. in this case, a write to cache is not performed. 3e. cache miss (copy- back/with write-back) the tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective addr ess bits [13:5]. then, data is read into the cache line from the external memory space co rresponding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. during this time, the cpu can execute the next processing. when reading of one line of data is completed, the tag correspondin g to the effective addre ss is recorded in the cache, and 1 is written to the v bit and u bit. the data in the write-back buffer is then written back to external memory.
4. caches rev.4.00 oct. 10, 2008 page 111 of 1122 rej09b0370-0400 4.3.4 write-back buffer in order to give priority to da ta reads to the cache and improve pe rformance, this lsi has a write- back buffer which holds the releva nt cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. the write -back buffer contains one cache line of data and the physical ad dress of the purge destination. lw7 physical address bits [28:5] lw6 lw5 lw4 lw3 lw2 lw1 lw0 figure 4.4 configuration of write-back buffer 4.3.5 write-through buffer this lsi has a 64-bit buffer for holding write da ta when writing data in write-through mode or writing to a non-cacheable area. this allows the cp u to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. physical address bits [28:0] lw1 lw0 figure 4.5 configuration of write-through buffer 4.3.6 ram mode setting ccr.ora to 1 enables 8 kbytes of the opera nd cache to be used as ram. the operand cache entries used as ram are the 8 kbytes of entries 128 to 255 and 384 to 511. in sh7751- compatible-mode in the sh7751r, the 8 kbytes of operand cache en tries 256 to 51 1 are used as ram. in cache-double-mode in th e sh7751r, the total 16 kbytes of entries 256 to 511 in each way of the operand cache are used as ram. othe r entries can still be used as cache. ram can be accessed using addresses h'7c00 0000 to h'7fff f fff. byte-, word-, long word-, and quadword- size data reads and writes can be performed in the operand cache ram area. instruction fetches cannot be performed in this area. note that in the sh7751r, oc index mode cannot be used when ram mode is used. an example of ram use is shown below. here, the 4 kbytes comprising oc entries 128 to 256 are designated as ram area 1, and the 4 kbytes comprising oc entries 384 to 511 as ram area 2.
4. caches rev.4.00 oct. 10, 2008 page 112 of 1122 rej09b0370-0400 ? when oc index mode is off (ccr.oix = 0) h'7c00 0000 to h'7c00 0fff (4 kb): corresponds to ram area 1 h'7c00 1000 to h'7c00 1fff (4 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 2fff (4 kb): corresponds to ram area 2 h'7c00 3000 to h'7c00 3fff (4 kb): corresponds to ram area 2 h'7c00 4000 to h'7c00 4fff (4 kb): corresponds to ram area 1 : : : ram areas 1 and 2 then repeat ever y 8 kbytes up to h'7fff ffff. thus, to secure a continuous 8-kbyte ram ar ea, the area from h'7c00 1000 to h'7c00 2fff can be used, for example. ? when oc index mode is on (ccr.oix = 1) h'7c00 0000 to h'7c00 0fff (4 kb): corresponds to ram area 1 h'7c00 1000 to h'7c00 1fff (4 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 2fff (4 kb): corresponds to ram area 1 : : : h'7dff f000 to h'7dff ffff (4 kb): corresponds to ram area 1 h'7e00 0000 to h'7e00 0fff (4 kb): corresponds to ram area 2 h'7e00 1000 to h'7e00 1fff (4 kb): corresponds to ram area 2 : : : h'7fff f000 to h'7fff ffff (4 kb): corresponds to ram area 2 as the distinction between ram areas 1 and 2 is indicated by address bit [25], the area from h'7dff f000 to h'7e00 0fff should be used to secure a continuous 8-kbyte ram area. an example of ram use in the sh7751r is shown below. ? sh7751-compatible-mode (ccr.emode = 0) h'7c00 0000 to h'7c00 1fff (8 kb): corresponds to ram area (entries 256 to 511) h'7c00 2000 to h'7c00 3fff (8 kb): corresponds to ram area (entries 256 to 511) : : : a shadow of the ram area occurs every 8 kbytes up to h'7fff ffff. ? cache-double-mode (ccr.emode = 1) the 8 kbytes of entries 256 to 511 in oc way 0 are used as ram area 1, and the 8 kbytes of entries 256 to 511 in oc way 1 are used as ram area 2. h'7c00 0000 to h'7c00 1fff (8 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 3fff (8 kb): corresponds to ram area 2
4. caches rev.4.00 oct. 10, 2008 page 113 of 1122 rej09b0370-0400 h'7c00 4000 to h'7c00 5fff (8 kb): corresponds to ram area 1 h'7c00 6000 to h'7c00 7fff (8 kb): corresponds to ram area 2 : : : a shadow of the ram area occurs every 16 kbytes up to h'7fff ffff. 4.3.7 oc index mode setting ccr.oix to 1 enables oc indexing to be performed using bit [25] of the effective address. this is called oc index mode. in normal mode, with ccr.oix cleared to 0, oc indexing is performed using bits [13:5] of the effective address. using index mode allows the oc to be handled as two areas by means of effective address bit [25], providing effici ent use of the cache. note that in the sh7751r, ram mode cannot be used when oc index mode is used. 4.3.8 coherency between ca che and external memory coherency between cache and external memory should be assured by software. in this lsi, the following four new instructions are supported for cache operations. details of these instructions are given in the programming manual. invalidate instruction: ocbi @rn cache invalidation (no write-back) purge instruction: ocbp @rn cache invalidation (with write-back) write-back instruction: ocbwb @rn cache write-back allocate instruction: movca. l r0,@rn cache allocation 4.3.9 prefetch operation this lsi supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. if it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data before hand by means of the prefetch in struction to prevent a cache miss due to the read or write operation, and so improve software performance. if a prefetch instruction is executed for data already held in the cache, or if the prefetch address re sults in a utlb miss or a protection violation, the result is no operation, and an exception is not generated. details of the prefetch instruction are given in the programming manual. prefetch instruction: pref @rn
4. caches rev.4.00 oct. 10, 2008 page 114 of 1122 rej09b0370-0400 4.3.10 notes on using oc ram mode (sh7751r only) when in cache enhanced mode when in cache enhanced mode (ccr.emode = 1) on the sh7751r, and the oc ram mode, in which half of the operand cache is used as internal ram, is selected (ccr.ora = 1), data in ram may be updated incorrectly. conditions under which problem occurs: incorrect data may be written to ram when the following four conditions are satisfied. condition 1: cache enhanced mode (ccr.emode = 1) is specified. condition 2: the ram m ode (ccr.ora = 1) in which half of the operand cache is used as ram is specified. condition 3: an exception or an interrupt occurs. note: this includes a break triggered by a debugging tool swapping an instruction (a break occurring when a trapa instruction or undefined instruction code h'fffd is swapped for an instruction). condition 4: a store instruction (mov, fmov, and.b, or.b, xor.b, movca.l, stc.l, or sts.l) that accesses internal ram (h'7c000 000 to h'7fffffff) exists within four words after the instruction associated with the exception or interrupt described in condition 3. this incl udes cases where the store inst ruction that accesses internal ram itself generates an exception. description: when the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary that includes an addres s that differs by h'2000 from the address accessed by the store instruction that accesses internal ram mentione d in condition 4. for ex ample, when a long word is stored at address h'7c000204, the 8 bytes of data in the internal ram mapped to addresses h'7c002200 to h'7c002207 becomes corrupted.
4. caches rev.4.00 oct. 10, 2008 page 115 of 1122 rej09b0370-0400 examples example 1 a store instruction accessing internal ram occurs with in four instructions after an instruction generating a tlb miss exception. mov.l #h'0c400000, r0 r0 is an address causing a tlb miss. mov.l #h'7c000204, r1 r1 is an address mapped to internal ram. mov.l @r0, r2 tlb miss exception occurs. nop 1st word nop 2nd word nop 3rd word mov.l r3, @r1 store instruction accessing internal ram example 2 a store instruction accessing internal ram occurs with in four instructions after an instruction causing an in terrupt to be accepted. mov.l #h'7c002000, r1 r1 is an address mapped to internal ram. mov.l #h'12345678, r0 an interrupt is accepted after this instruction. nop 1st word nop 2nd word nop 3rd word mov.l r0, @r1 store instruction accessing internal ram example 3 a debugging tool generates a break to swap an instruction. original instruction string a fter instruction swap break mov.l #h'7c000000, r0 mov.l #h'7c000000, r0 contains address corresponding to r0. add r0, r0 trapa #h'01 r0 address is not a problem in original instruction string. mov.l r1, @r0 mov.l r1, @r0 internal ram is accessed by a store operation because add is not executed. the store is cancelled, but 2lw starting at h'7c002000 is corrupted.
4. caches rev.4.00 oct. 10, 2008 page 116 of 1122 rej09b0370-0400 workarounds: when ram mode is specified in cache en hanced mode, either of the following workarounds can be used to avoid the problem. workaround 1: use only 8 kbytes of the 16-kbyte internal ram area. in this case, ram areas for which address bits [12:0] are identical and only bit [13] differs must not be used. for example, the 8-kbyte ram area from h'7c000000 to h'7c001fff or from h'7c001000 to h'7c002fff may be used. note: when a break is used to swap instru ctions by a debugging t ool, etc., a memory access address may be changed when an instruction following the instruction generating the break is swapped for another instruction, causing the unused 8-kbyte ram area to be accessed. this will result in the problem de scribed above. however, this phenomenon only occurs during debugging when a break is used to swap instructions. using a break with no instruction swapping will not cause the problem. workaround 2: ensure that there are no instructions that ge nerate an interrupt or exception within four instructions after an instruct ion that accesses internal ram. for example, the internal ram area can be used as a data table that is accessed only by load instructions, with writes to the internal ram area only being perf ormed when the table is generated. in this case, set sr.bl to 1 to disable interrupts while writing to the table. also take measures to ensure that no exceptions du e to tlb misses, etc., occur while writing to the table. note: the problem still may occur when a break is used to swap instructions by a debugging tool. this phenomenon only occurs during debugging when a break is used to swap instructions. using a break with no instruction swapping will not cause the problem. 4.4 instruction cache (ic) 4.4.1 configuration the instruction cache consists of 256 cache lines, each composed of a 19-bit tag, v bit, and 32- byte data (16 instructions). the instruction cache in the sh7751r a dopts the 2-way set-associative method, and each way consists of 256 cache lines.
4. caches rev.4.00 oct. 10, 2008 page 117 of 1122 rej09b0370-0400 figure 4.6 shows the configuration of the instruction cache in the sh7751. figure 4.7 shows the configuration of the instruction cache in the sh7751r. lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 255 19 bits 1 bit ta g v address array lon g word (lw) selection data array 0 read data hit si g nal compare 31 26 25 5 4 3 2 1 mmu iix [12] [11:5] entry selection effective address 8 3 22 19 13 12 11 10 9 0 figure 4.6 configuration of instruction cache (sh7751)
4. caches rev.4.00 oct. 10, 2008 page 118 of 1122 rej09b0370-0400 31 25 5 4 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 1 bit mmu iix [12] [11:5] 255 19 bits 1 bit ta g v address array (way 0, way 1) data array (way 0, way 1) lru entry selection lon g word (lw) selection effective address 3 8 22 19 0 read data hit si g nal compare way-0 compare way-1 13 12 11 10 0 figure 4.7 configuration of instruction cache (sh7751r) ? tag stores the upper 19 bits of the 29-bit external ad dress of the data line to be cached. the tag is not initialized by a power-on or manual reset. ? v bit (validity bit) indicates that valid data is stored in the cache line. when this bit is 1, the cache line data is valid. the v bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
4. caches rev.4.00 oct. 10, 2008 page 119 of 1122 rej09b0370-0400 ? data array the data field holds 32 bytes (256 bits) of data per cache line. the data array is not initialized by a power-on or manual reset. ? lru (sh7751r only) in a 2-way set-associative system, up to two en try addresses can register the same data in cache. the lru bit indicates to which way the en try is to be register ed among the two ways. there is one lru bit in each entry, and it is c ontrolled by hardware. the lru (last recently used) algorithm that selects the most recentl y accessed way is used for way selection. the lru bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. the lru bit cannot be read from or written to by software. 4.4.2 read operation when the ic is enabled (ccr.ice = 1) and inst ruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. the tag and v bit are read from the cache line indexed by effective address bits [12:5]. 2. the tag is compared with bits [28:10] of the address resulting fr om effective address translation by the mmu: ? if the tag matches and the v bit is 1 (3a) ? if the tag matches and the v bit is 0 (3b) ? if the tag does not match and the v bit is 0 (3b) ? if the tag does not match and the v bit is 1 (3b) 3a. cache hit the data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effe ctive address bits [12:5]. 3b. cache miss data is read into the cache line from the extern al memory space corresp onding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the cpu as an instruction. when readin g of one line of data is completed, the tag corresponding to the effec tive address is recorded in the cache, and 1 is written to the v bit.
4. caches rev.4.00 oct. 10, 2008 page 120 of 1122 rej09b0370-0400 4.4.3 ic index mode setting ccr.iix to 1 enables ic indexing to be perf ormed using bit [25] of the effective address. this is called ic index mode. in normal mode , with ccr.iix cleared to 0, ic indexing is performed using bits [12:5] of the effective address. using index mode allows the ic to be handled as two areas by means of effective address b it [25], providing efficient use of the cache. 4.5 memory-mapped cache configuration (sh7751) to enable the ic and oc to be managed by software, the ic contents can be read and written by a p2 area program with a mov instru ction in privileged mode. operation is not guaranteed if access is made from a program in another area. in this cas e, a branch to the p0, u0 , p1, or p3 area should be made at least 8 instructions after this mov instruction. th e oc contents can be read and written by a p1 or p2 area program with a mov instruction in privileged mode. operation is not guaranteed if access is made from a program in anot her area. in this case, a branch to the p0, u0, or p3 area should be made at least 8 instructions after this mov instruction. the ic and oc are allocated to the p4 area in phys ical memory space. only data accesses can be used on both the ic address array and data array and the oc address ar ray and data array, and the access size is always longword. instruction fetches cannot be performed in these areas. for reserved bits, a write value of 0 should be specified, and read values are undefined. 4.5.1 ic address array the ic address array is allocated to addresses h' f000 0000 to h'f0ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e entry to be accessed is specified in the address field, and the write tag and v bit are speci fied in the data field. in the address field, bits [31:24] have the value h'f0 indicating the ic address array, and the entry is specified by bits [12:5]. ccr.iix has no effect on this entry specification. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the ic address array. as only longword acces s is used, 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [ 31:10], and the v bit by bit [0]. as the ic address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [3 1:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the ic address array:
4. caches rev.4.00 oct. 10, 2008 page 121 of 1122 rej09b0370-0400 1. ic address array read the tag and v bit are read into the data field from the ic entry corresponding to the entry set in the address field. in a read, associative opera tion is not performed regardless of whether the association bit specified in th e address field is 1 or 0. 2. ic address array write (non-associative) the tag and v bit specified in the data field are written to the ic entry corresponding to the entry set in the address field. the a bit in the address field shoul d be cleared to 0. 3. ic address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. if the mmu is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the itlb. if the addresses match and the v bit is 1, the v bit specified in the data field is written into the ic entry. in other cases, no operation is performed. this operation is used to invalidate a specific ic entry. if an itlb miss occurs during addr ess translation, or the comp arison shows a mismatch, an interrupt is not generated, no operation is pe rformed, and the write is not executed. if an instruction tlb multiple hit exception occurs during address translation, processing switches to the instruction tlb multiple hit exception handling routine. address field 31 23 12 543210 11110000 entry a data field 31 10 9 1 0 v ta g le g end: v: a: 24 13 validity bit association bit : reserved bits (0 write value, undefined read value) figure 4.8 memory-mapped ic address array
4. caches rev.4.00 oct. 10, 2008 page 122 of 1122 rej09b0370-0400 4.5.2 ic data array the ic data array is allocated to addresses h'f1 00 0000 to h'f1ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the entry to be accessed is specified in the address field, an d the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f1 indicating the ic data array, and the entry is specified by bits [12:5]. ccr.iix ha s no effect on this entry specifi cation. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the ic data array: 1. ic data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the ic entry corre sponding to the entry set in the address field. 2. ic data array write the longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the ic entry corresponding to the entry set in the address field. address field 31 23 12 5 4 2 1 0 11110001 entry l data field 31 0 lon g word data le g end: l: 24 13 lon g word specification bits : reserved bits (0 write value, undefined read value) figure 4.9 memory-mapped ic data array
4. caches rev.4.00 oct. 10, 2008 page 123 of 1122 rej09b0370-0400 4.5.3 oc address array the oc address array is allocated to addresses h'f400 0000 to h'f4ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. the entry to be acce ssed is specified in the address field, and the write tag, u bit, and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f4 indicating the oc address array, and the entry is specified by bits [13:5]. ccr.oix and ccr.ora have no effect on this entry specification. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the oc address arra y. as only longword acce ss is used, 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [31:10], the u bit by bit [1], and the v bit by bit [0]. as the oc address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the oc address array: 1. oc address array read the tag, u bit, and v bit are read into the data field from the oc entry corresponding to the entry set in the address field. in a read, asso ciative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. oc address array write (non-associative) the tag, u bit, and v bit specified in the data field are written to the oc entry corresponding to the entry set in the address field. the a bit in the address field shou ld be cleared to 0. when a write is performed to a cache line for which the u bit and v bit are both 1, after write- back of that cache line, the ta g, u bit, and v bit specified in the data field are written. 3. oc address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag stored in the entry specified in the address fiel d is compared with the tag specified in the data field. if the mmu is enabled at this time, comparison is pe rformed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the utlb. if the addresses match and the v bit is 1, the u bit an d v bit specified in the data field are written into the oc entry. this operation is used to invalidate a specific oc entry. in other cases, no operation is performed. if the oc entry u bit is 1, and 0 is written to the v bit or to the u bit, write-back is performed. if a u tlb miss occurs during address tr anslation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is
4. caches rev.4.00 oct. 10, 2008 page 124 of 1122 rej09b0370-0400 not executed. if a data tlb multiple hit exception occurs during address translation, processing switches to the data tlb multiple hit exception handling routine. address field 31 23 543210 11110100 entry a data field 31 10 9 1 0 v ta g 24 13 14 2 u le g end: v: u: a: validity bit dirty bit association bit : reserved bits (0 write value, undefined read value) figure 4.10 memory-mapped oc address array 4.5.4 oc data array the oc data array is allocated to addresses h'f5 00 0000 to h'f5ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the entry to be accessed is specified in the address field, an d the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f5 indicating the oc data array, and the entry is specified by bits [13:5]. ccr.oix and ccr.ora have no effect on this entry specification. address field bits [4:2] are used for the longword da ta specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the oc data array: 1. oc data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the oc entry corresp onding to the entry set in the address field. 2. oc data array write the longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the oc entry corresponding the en try set in the address field. this write does not set the u bit to 1 on the address array side.
4. caches rev.4.00 oct. 10, 2008 page 125 of 1122 rej09b0370-0400 address field 31 23 54 210 11110101 entry l data field 31 0 lon g word data 24 13 14 le g end: l: lon g word specification bits : reserved bits (0 write value, undefined read value) figure 4.11 memory-mapped oc data array 4.6 memory-mapped cache configuration (sh7751r) to enable the ic and oc to be managed by software, ic contents can be read and written by a p2 area program with a mov instructio n in privileged mode. operation is not guaranteed if access is made from a program in another ar ea. in this case, a branch to th e p0, u0, p1, or p3 area should be made at least 8 instructions after this mov instru ction. the oc contents can be read and written by a p1 or p2 area program with a mov inst ruction in privileged mode. operation is not guaranteed if access is made from a program in anot her area. in this case, a branch to the p0, u0, or p3 area should be made at least 8 instructions after this mov instruction. the ic and oc are allocated to the p4 area in phys ical memory space. only data accesses can be used on both the ic address array and data array and the oc address ar ray and data array, and the access size is always longword. instruction fetches cannot be performed in these areas. for reserved bits, a write value of 0 should be specified, and r ead values are undefined. note that the memory-mapped cache configuration in sh7751-compatible-mode of the sh7751r is the same as that in the sh7751. 4.6.1 ic address array the ic address array is allocated to addresses h' f000 0000 to h'f0ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the write tag and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f0 indicating the ic address array, the way is specified by bit [13], and the entry is specified by bits [12:5]. ccr.iix has no effect on this entry specification. address field bit [3], that is the association bit (a bit), specifies whether or not association is performed when writing to the ic a ddress array. as only longword access is used, 0 should be specified for address field bits [1:0].
4. caches rev.4.00 oct. 10, 2008 page 126 of 1122 rej09b0370-0400 in the data field, the tag is indicated by bits [ 31:10], and the v bit by bit [0]. as the ic address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [3 1:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the ic address array: 1. ic address array read the tag and v bit are read into the data field from the ic entry corresponding to the way and entry set in the address field. in a read, associ ative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. ic address array write (non-associative) the tag and v bit specified in the data field ar e written to the ic entry corresponding to the way and entry set in the address field. the a bit in the address field should be cleared to 0. 3. ic address array write (associative) when a write is performed with the a bit in the address field set to 1, each way's tag stored in the entry specified in the address field is compared with the tag sp ecified in the data field. the way number set in bit [13] is ignored. if the mmu is enabled at this time, comparison is performed after the virtual address specified by da ta field bits [31:10] has been translated to a physical address using the itlb. if the addresses match and the v bit in that way is 1, the v bit specified in the data field is written into the ic entry. in other cases, no operation is performed. this operation is used to invalidate a specific ic entry. if an itlb miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. if an instruction tlb multiple hit exception occurs during address translation, processing switches to the instruction tlb multiple hit exception handling routine. address field 31 23 12 543210 11110000 entry a data field 31 10 9 1 0 v ta g way le g end: v: a: 24 13 validity bit association bit : reserved bits (0 write value, undefined read value) figure 4.12 memory-mapped ic address array
4. caches rev.4.00 oct. 10, 2008 page 127 of 1122 rej09b0370-0400 4.6.2 ic data array the ic data array is allocated to addresses h'f1 00 0000 to h'f1ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f1 indicating the ic data array, the way is specified by bit [13], and the entry is specified by bits [12:5]. ccr.iix has no effect on this entry specification. address field bits [4 :2] are used for the longword data specification in the entry. as only longword access is used, 0 should be sp ecified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the ic data array: 1. ic data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the ic entry corresponding to the way and entry set in the address field. 2. ic data array write the longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the ic entry corresponding to the way and entry set in the address field. address field 31 23 12 5 4 2 1 0 11110001 entry l data field 31 0 lon g word data le g end: l: 24 13 lon g word specification bits : reserved bits (0 write value, undefined read value) way figure 4.13 memory-mapped ic data array
4. caches rev.4.00 oct. 10, 2008 page 128 of 1122 rej09b0370-0400 4.6.3 oc address array the oc address array is allocated to addresses h'f400 0000 to h'f4ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e way and entry to be accessed are specified in the address field, and the write tag, u bit, and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f4 indicating the oc address array, the way is specified by bit [14], and the entry is specified by bits [13:5]. ccr.oix has no effect on this entry specification. the oc address array access in ra m mode (ccr.ora = 1) is performed only to cache, and bit [13] specifies the way. for details on address allocation, s ee section 4.6.5, summary of memory-mapped oc addresses. address field bit [3], that is the association bit (a bit), specifies whether or not association is performed when writing to the oc address array. as only longword access is used, 0 should be speci fied for address field bits [1:0]. in the data field, the tag is indicated by bits [31:10], the u bit by bit [1], and the v bit by bit [0]. as the oc address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the oc address array: 1. oc address array read the tag, u bit, and v bit are read into the data field from the oc entry corresponding to the way and entry set in the address field. in a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. oc address array write (non-associative) the tag, u bit, and v bit specified in the data field are written to the oc entry corresponding to the way and entry set in the address field. the a b it in the address field sh ould be cleared to 0. when a write is performed to a cache line for which the u bit and v bit are both 1, after write- back of that cache line, the ta g, u bit, and v bit specified in the data field are written. 3. oc address array write (associative) when a write is performed with the a bit in the address field set to 1, each way's tag stored in the entry specified in the address field is compared with the tag sp ecified in the data field. the way number set in bit [14] is ignored. if the mmu is enabled at this time, comparison is performed after the virtual address specified by da ta field bits [31:10] has been translated to a physical address using the utlb. if the addresses match and the v bit in that way is 1, the u bit and v bit specified in the data field are written into the oc entry. this operation is used to invalidate a specific oc entry. in other cases, no operation is performed. if the oc entry u bit is 1, and 0 is written to the v bit or to the u bit, write-back is performed. if a utlb miss
4. caches rev.4.00 oct. 10, 2008 page 129 of 1122 rej09b0370-0400 occurs during address tr anslation, or the comparison show s a mismatch, an exception is not generated, no operation is performed, and the wr ite is not executed. if a data tlb multiple hit exception occurs during address translation, processing switches to the data tlb multiple hit exception handling routine. address field 31 23 543210 11110100 entry a data field 31 10 9 1 0 v ta g 24 13 14 15 2 u le g end: v: u: a: validity bit dirty bit association bit : reserved bits (0 write value, undefined read value) way figure 4.14 memory-mapped oc address array 4.6.4 oc data array the oc data array is allocated to addresses h'f5 00 0000 to h'f5ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f5 indicating the oc data array, the way is specified by bit [14], and the entry is specified by bits [13:5]. ccr.oix has no effect on this entry specification. the oc address array access in ra m mode (ccr.ora = 1) is performed only to cache, and bit [13] specifies the way. for details on address allocation, s ee section 4.6.5, summary of memory-mapped oc addresses. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the oc data array:
4. caches rev.4.00 oct. 10, 2008 page 130 of 1122 rej09b0370-0400 1. oc data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the oc entry corresp onding to the way and entry set in the address field. 2. oc data array write the longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the oc entry corresponding to the way and entry set in the address field. this writ e does not set the u bit to 1 on the address array side. address field 31 23 54 210 11110101 entry l data field 31 0 lon g word data 24 13 14 le g end: l: lon g word specification bits : reserved bits (0 write value, undefined read value) 15 way figure 4.15 memory-mapped oc data array 4.6.5 summary of memory-mapped oc addresses the memory-mapped oc addresse s in cache-double-mode in the sh7751r are summ arized below using data area acce ss as an example. ? normal mode (ccr.ora = 0) h'f500 0000 to h'f500 3fff (16 kb): way 0 (entries 0 to 511) h'f500 4000 to h'f500 7fff (16 kb): way 1 (entries 0 to 511) : : : a shadow of the cache area occurs ever y 32 kbytes up to h'f5ff ffff. ? ram mode (ccr.ora = 1) h'f500 0000 to h'f500 1fff (8 kb): way 0 (entries 0 to 255) h'f500 2000 to h'f500 3fff (8 kb): way 1 (entries 0 to 255) : : : a shadow of the cache area occurs ever y 16 kbytes up to h'f5ff ffff.
4. caches rev.4.00 oct. 10, 2008 page 131 of 1122 rej09b0370-0400 4.7 store queues two 32-byte store queues (sqs) are supported to perform high-speed writes to external memory. when not using the sqs, the low power dissipation power-down modes, in which sq functions are stopped, can be used. the queue address control registers (qacr0 and qacr1) cannot be accessed while sq functions are stopped. see sec tion 9, power-down mode s, for the procedure for stopping sq functions. note that power-do wn modes (stbcr2.mstp6 = 1) that stop sq functions cannot be used on the sh7751 when using the operand cache for write-back operations.* note: * cases where write-back operations are performed: ? when the operand cache is used in copy -back mode (determined by the ccr.cb and ccr.wt bits and, if address translati on is performed, the wt bit in the page management information) ? when the memory allocation cache function is used to write to the oc address array, and an entry is generated when both the v and u bits are set to 1 4.7.1 sq configuration there are two 32-byte store queues, sq0 and sq1, as shown in figure 4.16. these two store queues can be set independently. sq0 sq0[0] sq0[1] sq0[2] sq0[3] sq0[4] sq0[5] sq0[6] sq0[7] sq1 sq1[0] sq1[1] sq1[2] sq1[3] sq1[4] sq1[5] sq1[6] sq1[7] 4b 4b 4b 4b 4b 4b 4b 4b figure 4.16 store queue configuration 4.7.2 sq writes a write to the sqs can be performed using a store instruction on p4 area h'e000 0000 to h'e3ff fffc. a longword or quadword acces s size can be used. the meaning of the address bits is as follows: [31:26]: 111000 store queue specification [25:6]: don't care used for exte rnal memory transfer/access right [5]: 0/1 0: sq0 specification 1: sq1 specification
4. caches rev.4.00 oct. 10, 2008 page 132 of 1122 rej09b0370-0400 [4:2]: lw specification specifies longword position in sq0/sq1 [1:0] 00 fixed at 0 4.7.3 transfer to external memory transfer from the sqs to external memory can be performed with a prefetch instruction (pref). issuing a pref instruction for p4 area h'e000 0000 to h'e3ff fffc starts a burst transfer from the sqs to external memory. the burst transfer lengt h is fixed at 32 bytes, and the start address is always at a 32-byte bound ary. while the contents of one sq are being transferred to external memory, the other sq can be written to without a penalty cycle, but writing to the sq involved in the transfer to external memory is de ferred until the transf er is completed. the sq transfer destination extern al address bit [28:0] specification is as shown below, according to whether the mmu is on or off. ? when mmu is on the sq area (h'e000 0000 to h'e3ff ffff) is set in vpn of the utlb, and the transfer destination external address in ppn. the asid, v, sz, sh, pr, and d bits have the same meaning as for normal address translation, but the c and wt bits have no meaning with regard to this page. since burst transfer is prohibited for pcmcia areas, the sa and tc bits also have no meaning. when a prefetch instruction is issued for the sq area, address translation is performed and external address bits [28:10] are generated in accordance with the sz bit specification. for external address bits [9:5], the address prior to address translation is generated in the same way as when the mmu is off. external address bits [4:0] are fixed at 0. transfer from the sqs to external is performed to this address. ? when mmu is off the sq area (h'e000 0000 to h'e3ff ffff) is specified as the address at which a pref instruction is issued. the meaning of address bits [31:0] is as follows: [31:26]: 111000 store queue specification [25:6]: address external address bits [25:6] [5]: 0/1 0: sq0 specification 1: sq1 specification and external address bit [5] [4:2]: don't care no meaning in a prefetch [1:0] 00 fixed at 0 external address bits [28:26], which cannot be generated from the above address, are generated from the qacr0/1 registers.
4. caches rev.4.00 oct. 10, 2008 page 133 of 1122 rej09b0370-0400 qacr0 [4:2]: external address bits [28:26] corresponding to sq0 qacr1 [4:2]: external address bits [28:26] corresponding to sq1 external address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. in this lsi, data transfer to a pcmcia inte rface area is always performed using the sa and tc bits in the ptea register. 4.7.4 determination of sq access exception determination of an exception in a write to an sq or transfer to external memory (pref instruction) is performed as follows. if an excep tion occurs in an sq write, the sq contents may be corrupted in the sh7751 (see section 4.7.6, sq usage notes), but the previous values of the sq contents are guaranteed in the sh7751r. if an excep tion occurs in transfer fr om an sq to external memory, the transfer to external memory will be aborted. ? when mmu is on operation is in accordance with the address tran slation information recorded in the utlb, and mmucr.sqmd. write type exception judgment is performed for writes to the sqs, and read type for transfer from the sqs to external memory (pref instruction), and a tlb miss exception, protection violation exception, or in itial page write exception is generated. however, if sq access is enab led, in privileged mode only , by mmucr.sqmd, an address error will be flagged in user mode even if address transl ation is successful. ? when mmu is off operation is in accordance with mmucr.sqmd. 0: privileged/user access possible 1: privileged access possible if the sq area is accessed in user mode when mmu cr.sqmd is set to 1, an address error will be flagged. 4.7.5 sq read (sh7751r only) in the sh7751r, the sq contents can be read by a load instruction for addresses h'ff001000 to h'ff00103c in the p4 area in privileged mode. the access size is always longword. [31:6]: h'ff001000 (store queue specification) [5]: 0/1 (0: sq0 specification, 1: sq1 specification) [4:2]: lw specification (specification of longword position in sq0 or sq1) [1:0]: 00 (fixed to 0)
4. caches rev.4.00 oct. 10, 2008 page 134 of 1122 rej09b0370-0400 4.7.6 sq usage notes (sh7751 only) if an exception occurs within the three instructions preceding an instruction that writes to an sq in the sh7751, a branch may be made to the excep tion handling routine after execution of the sq write that should be suppressed when an exception occurs. this may be due to the bug described in (1) or (2) below. (1) when sq data is transferred to ex ternal memory within a normal program if a pref instruction for transfer from an sq to external memory is included in the three instructions preceding an sq stor e instruction, the sq is updat ed because the sq write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the pref instruction and sq store instruction is reversed, so that erroneous data may be transferred to external memory. (2) when sq data is transferred to extern al memory in an exception handling routine if store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to ex ternal memory. example 1: when an sq store instruction is executed afte r a pref instruction for transfer from that same sq to external memory pref instruction ; pref instruction for transfer from sq to external memory ; address of this instruction is saved to spc when exception occurs. ; instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling ; routine. instruction 1 ; may be executed if an sq store instruction. instruction 2 ; may be executed if an sq store instruction. instruction 3 ; may be executed if an sq store instruction. instruction 4 ; not executed even if an sq store instruction.
4. caches rev.4.00 oct. 10, 2008 page 135 of 1122 rej09b0370-0400 example 2: when an instruction at which an exception occurs is a branch instruction and a branch is made instruction 1 (branch instruction) ; address of this instruction is saved to spc when exception occurs. instruction 2 ; may be executed if an instruction 1 delay slot instruction and an sq store instruction. instruction 3 instruction 4 instruction 5 instruction 6 instruction 7 (instructi on 1 branch destination) ; may be executed if an sq store instruction. instruction 8 ; may be executed if an sq store instruction. example 3: when an instruction at which an exception oc curs is a branch instruction but a branch is not made instruction 1 (branch instruction) ; address of this instruction is saved to spc when exception occurs. instruction 2 ; may be executed if an sq store instruction. instruction 3 ; may be executed if an sq store instruction. instruction 4 ; may be executed if an sq store instruction. instruction 5 both a and b below must be satisfied in order to prevent this bug. a: when a store queue store instru ction is executed after a pref in struction for transfer from that same store queue (sq0, sq1) to external me mory, (1) and (2) below must be satisfied. (1) insert three nop instructions * 1 between the two instructions. (2) do not place a pref instructio n for transfer from a store queu e to external memory in the delay slot of a branch instruction. b: do not execute a pref instruction for transfer from a store queue to external memory within an exception handling routine. if the above is executed and there is a stor e queue store instruction among the four instructions * 2 including the instruction at the address indicated by the spc, the state of the contents transferred to external memory by the pref instruction may be that when execution of this store instruction is completed. notes: 1. if there are other instructions between the two instructions, this bug can be prevented if the total number of other instructions plus nop instructions is at least three. 2. if the instruction at the ad dress indicated by the spc is a branch instruction, this also applies to two instructions at the branch destination.
4. caches rev.4.00 oct. 10, 2008 page 136 of 1122 rej09b0370-0400
5. exceptions rev.4.00 oct. 10, 2008 page 137 of 1122 rej09b0370-0400 section 5 exceptions 5.1 overview 5.1.1 features exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the cpu in case of abnormal events. for ex ample, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality befo re terminating the processing. the process of generating an exception handling request in response to abnormal termination, and passing control flow to an exception handling routine, etc., is given the generic name of exception handling. sh-4 exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 register configuration the registers used in exception handling are shown in table 5.1. table 5.1 exception-related registers name abbrevia- tion r/w initial value p4 address * 2 area 7 address * 2 access size trapa exception register tra r/w undefined h 'ff00 0020 h'1f00 0020 32 exception event register expevt r/w h'0000 0000/ h'0000 0020 * 1 h'ff00 0024 h'1f00 0024 32 interrupt event register intevt r/w undefined h'ff00 0028 h'1f00 0028 32 notes: 1. h'0000 0000 is set in a power-on reset, and h'0000 0020 in a manual reset. 2. p4 address is the address when using t he virtual/physical address space p4 area. when making an access from area 7 in the ph ysical address space using the tlb, the three high most bits of the address are ignored.
5. exceptions rev.4.00 oct. 10, 2008 page 138 of 1122 rej09b0370-0400 5.2 register descriptions there are three registers related to exception hand ling. addresses are alloca ted for these, and can be accessed by specifying the p4 address or area 7 address. 1. the exception event register (expevt) reside s at p4 address h'ff00 0024, and contains a 12- bit exception code. the exception code set in expevt is that for a reset or general exception event. the exception code is set automatically by hardware when an exception is accepted. expevt can also be modified by software. 2. the interrupt event register (intevt) resides at p4 address h'ff00 002 8, and contains a 14- bit exception code. the exception code set in intevt is that for an interrupt request. the exception code is set automatically by hardwa re when an exception is accepted. intevt can also be modified by software. 3. the trapa exception register (tra) resides at p4 address h'ff00 0020, and contains 8-bit immediate data (imm) for the tr apa instruction. tra is set automatically by hardware when a trapa instruction is executed. tra can also be modified by software. the bit configurations of expevt, intevt, and tra are shown in figure 5.1. 31 0 0 0 0 0 0 0 0 31 10 9 1 0 le g end: 0: imm: reserved bits. these bits are always read as 0, and should only be written with 0. 8-bit immediate data of the trapa instruction 12 11 2 expevt tra imm 0 14 13 0 31 intevt exception code exception code figure 5.1 register bit configurations
5. exceptions rev.4.00 oct. 10, 2008 page 139 of 1122 rej09b0370-0400 5.3 exception handling functions 5.3.1 exception handling flow in exception handling, the contents of the program counter (pc), status register (sr) and r15 are saved in the saved program counter (spc), saved status register (ssr), and saved general register 15 (sgr), and the cpu starts execution of the appropriate exception handling routine according to the vector address. an exceptio n handling routine is a program written by the user to handle a specific exception. the exception ha ndling routine is terminated and control returned to the original program by executing a return-from-exception instruction (rte). this instruction restores the pc and sr contents and returns control to the normal processing routine at the point at which the exception occurred. the sgr contents are not written back to r15 by an rte instruction. the basic processing flow is as follows. see section 2, programming model, for the meaning of the individual sr bits. 1. the pc, sr, and r15 contents are saved in spc, ssr, and sgr. 2. the block bit (bl) in sr is set to 1. 3. the mode bit (md) in sr is set to 1. 4. the register bank bit (rb) in sr is set to 1. 5. in a reset, the fpu disable b it (fd) in sr is cleared to 0. 6. the exception code is written to bits 11?0 of the exception event register (expevt) or to bits 13?0 of the interrupt event register (intevt). 7. the cpu branches to the determined excep tion handling vector address, and the exception handling routine begins. 5.3.2 exception handling vector addresses the reset vector address is fixed at h'a000 0000 . general exception and interrupt vector addresses are determined by adding the offset for the specifi c event to the vector base address, which is set by software in the vector base register (vbr). in the case of the tlb miss exception, for example, the offset is h'0000 0400, so if h'9c08 0000 is set in vbr, the exception handling vector address will be h'9c08 0400. if a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (p1, p2) should be specified for vector addresses.
5. exceptions rev.4.00 oct. 10, 2008 page 140 of 1122 rej09b0370-0400 5.4 exception types and priorities table 5.2 shows the types of exceptions, with thei r relative priorities, vector addresses, and exception/interrupt codes. table 5.2 exceptions exception category execution mode exception priority level priority order vector address offset exception code power-on reset 1 1 h'a000 0000 ? h'000 manual reset 1 2 h'a000 0000 ? h'020 h-udi reset 1 1 h'a000 0000 ? h'000 instruction tlb multiple-hit exception 1 3 h'a000 0000 ? h'140 reset abort type data tlb multiple-hit exception 1 4 h'a000 0000 ? h'140 user break before instruction execution * 1 2 0 (vbr/dbr) h'100/? h'1e0 instruction address error 2 1 (vbr) h'100 h'0e0 instruction tlb miss exception 2 2 (vbr) h'400 h'040 instruction tlb protection violation exception 2 3 (vbr) h'100 h'0a0 general illegal instruction exception 2 4 (vbr) h'100 h'180 slot illegal instruction exc eption 2 4 (vbr) h'100 h'1a0 general fpu disable exception 2 4 (vbr) h'100 h'800 slot fpu disable exception 2 4 (vbr) h'100 h'820 data address error (read) 2 5 (vbr) h'100 h'0e0 data address error (write) 2 5 (vbr) h'100 h'100 data tlb miss exception (read) 2 6 (vbr) h'400 h'040 data tlb miss exception (write) 2 6 (vbr) h'400 h'060 data tlb protection violation exception (read) 2 7 (vbr) h'100 h'0a0 data tlb protection violation exception (write) 2 7 (vbr) h'100 h'0c0 fpu exception 2 8 (vbr) h'100 h'120 re- execution type initial page write exception 2 9 (vbr) h'100 h'080 unconditional trap (trapa) 2 4 (vbr) h'100 h'160 general exception completion type user break after instruction execution * 1 2 10 (vbr/dbr) h'100/? h'1e0
5. exceptions rev.4.00 oct. 10, 2008 page 141 of 1122 rej09b0370-0400 exception category execution mode exception priority level priority order vector address offset exception code nonmaskable interrupt 3 ? (vbr) h'600 h'1c0 0 h'200 1 h'220 2 h'240 3 h'260 4 h'280 5 h'2a0 6 h'2c0 7 h'2e0 8 h'300 9 h'320 a h'340 b h'360 c h'380 d h'3a0 external interrupts irl3?irl0 e 4 * 2 (vbr) h'600 h'3c0 tmu0 tuni0 h'400 tmu1 tuni1 h'420 tuni2 h'440 tmu2 ticpi2 h'460 tmu3 tuni3 h'b00 tmu4 tuni4 h'b80 ati h'480 pri h'4a0 rtc cui h'4c0 sci eri h'4e0 rxi h'500 txi h'520 tei h'540 wdt iti h'560 rcmi h'580 interrupt completion type peripheral module interrupt (module/ source) ref rovi 4 * 2 (vbr) h'600 h'5a0
5. exceptions rev.4.00 oct. 10, 2008 page 142 of 1122 rej09b0370-0400 exception category execution mode exception priority level priority order vector address offset exception code h-udi h-udi h'600 gpio gpioi h'620 dmte0 h'640 dmte1 h'660 dmte2 h'680 dmte3 h'6a0 dmte4 * 3 h'780 dmte5 * 3 h'7a0 dmte6 * 3 h'7c0 dmte7 * 3 h'7e0 dmac dmae h'6c0 eri h'700 rxi h'720 bri h'740 scif txi h'760 pcic pciserr h'a00 pcierr h'ae0 pcipwdwn h'ac0 pcipwon h'aa0 pcidma0 h'a80 pcidma1 h'a60 pcidma2 h'a40 interrupt completion type peripheral module interrupt (module/ source) pcidma3 4 * 2 (vbr) h'600 h'a20 priority: priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). exception transition destination: control passes to h'a000 0000 in a reset, and to [vbr + offset] in other cases. exception code: stored in expevt for a reset or gener al exception, and in intevt for an interrupt. irl: interrupt request level (pins irl3?irl0). module/source: see the sections on the relevant peripheral modules. notes: 1. when brcr.ubde = 1, pc = db r. in other cases, pc = vbr + h'100. 2. the priority order of external interrupts and peripheral module interrupts can be set by software. 3. sh7751r only
5. exceptions rev.4.00 oct. 10, 2008 page 143 of 1122 rej09b0370-0400 5.5 exception flow 5.5.1 exception flow figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. for the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/gener al exception/interrupt). register settings in the event of an exception are shown only for ssr, spc, sgr, expevt/intevt, sr, and pc, but other registers may be set automatically by hardware, depending on the exception. for details, see section 5.6, description of exceptions. also, see section 5.6.4, priority order with multiple exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instru ctions in which two data accesses are performed. execute next instruction is hi g hest- priority exception re-exception type? cancel instruction execution result yes yes yes no no no no yes ssr sr spc pc sgr r15 expevt/intevt exception code sr.{md,rb,bl} 111 pc (brcr.ubde=1 && user_break? dbr: (vbr + offset)) expevt exception code sr. {md, rb, bl, fd, imask} 11101111 pc h'a000 0000 interrupt requested? general exception requested? reset requested? figure 5.2 instruction execution and exception handling
5. exceptions rev.4.00 oct. 10, 2008 page 144 of 1122 rej09b0370-0400 5.5.2 exception source acceptance a priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. five of the general exceptions?the general illegal instruction exception, slot illegal instruction exception, general fpu disable exception, slot fpu disable excep tion, and unconditional trap exception?are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. these exceptions theref ore all have the same priority. general ex ceptions are detected in the order of instruction execution. however, exception handling is performed in the order of instruction flow (program order). thus, an exceptio n for an earlier instruction is accepted before that for a later instruction. an example of the order of acceptance for general ex ceptions is shown in figure 5.3.
5. exceptions rev.4.00 oct. 10, 2008 page 145 of 1122 rej09b0370-0400 if if id id ex ex ma ma wb wb tlb miss (data access) pipeline flow: order of detection: instruction n instruction n+1 general ille g al instruction exception (instruction n+1) and tlb miss (instruction n+2) are detected simultaneously order of exception handlin g : tlb miss (instruction n) pro g ram order 1 instruction n+2 general ille g al instruction exception if id ex ma wb if id ex ma wb tlb miss (instruction access) 2 3 4 le g end: if: instruction fetch id: instruction decode ex: instruction execution ma: memory access wb: write-back instruction n+3 tlb miss (instruction n) re-execution of instruction n general ille g al instruction exception (instruction n+1) re-execution of instruction n+1 tlb miss (instruction n+2) re-execution of instruction n+2 execution of instruction n+3 figure 5.3 example of general exception acceptance order
5. exceptions rev.4.00 oct. 10, 2008 page 146 of 1122 rej09b0370-0400 5.5.3 exception requests and bl bit when the bl bit in sr is 0, genera l exceptions and interrupts are accepted. when the bl bit in sr is 1 and a general exception other than a user break is generated, the cpu's internal registers and the registers of the other mo dules are set to their po st-reset state, and the cpu branches to the same address as in a reset (h'a000 0000). for the oper ation in the event of a user break, see section 20, user break controller (ubc). if an ordinary interrupt occurs, the interrupt reque st is held pending and is accepted after the bl bit has been cleared to 0 by software. if a no nmaskable interrupt (nmi) occurs, it can be held pending or accepted according to the setting made by software. thus, normally, spc and ssr are saved and then th e bl bit in sr is cleared to 0, to enable multiple exception state acceptance. 5.5.4 return from exception handling the rte instruction is used to return from exception handling. when the rte instruction is executed, the spc contents are restored to pc and the ssr contents to sr, and the cpu returns from the exception handling routine by branching to the spc address. if spc and ssr were saved to external memory, set the bl bit in sr to 1 before restoring the spc and ssr contents and issuing the rte instruction. 5.6 description of exceptions the various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made.
5. exceptions rev.4.00 oct. 10, 2008 page 147 of 1122 rej09b0370-0400 5.6.1 resets (1) power-on reset ? sources: ? reset pin low level ? when the watchdog timer overflows while the wt/ it bit is set to 1 and the rsts bit is cleared to 0 in wtcsr. for details, see section 10, clock oscillation circuits. ? transition address: h'a000 0000 ? transition operations: exception code h'000 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. for some cpu functions, the trst pin and reset pin must be driven low. it is therefore essen tial to execute a power-on reset and drive the trst pin low when powering on. if the reset pin is driven high before the mreset pin while both these pins are low, a manual reset may occur after the power-on reset operation. the reset pin must be driven high at the same time as, or after, the mreset pin. power_on_reset() { expevt = h'00000000; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd=0; initialize_cpu(); initialize_module(poweron); pc = h'a0000000; }
5. exceptions rev.4.00 oct. 10, 2008 page 148 of 1122 rej09b0370-0400 (2) manual reset ? sources: ? mreset pin low level and reset pin high level ? when a general exception other than a user break occurs while the bl bit is set to 1 in sr ? when the watchdog timer overfl ows while the rsts bit is set to 1 in wtcsr. for details, see section 10, clock oscillation circuits. ? transition address: h'a000 0000 ? transition operations: exception code h'020 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. manual_reset() { expevt = h'00000020; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; } table 5.3 types of reset reset state transition conditions internal states type mreset reset cpu on-chip peripheral modules power-on reset ? low initialized manual reset low high initialized see register configuration in each section
5. exceptions rev.4.00 oct. 10, 2008 page 149 of 1122 rej09b0370-0400 (3) h-udi reset ? source: sdir.ti3?ti0 = b'0110 (negation) or b'0111 (assertion) ? transition address: h'a000 0000 ? transition operations: exception code h'000 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. h-udi_reset() { expevt = h'00000000; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(poweron); pc = h'a0000000; }
5. exceptions rev.4.00 oct. 10, 2008 page 150 of 1122 rej09b0370-0400 (4) instruction tlb multiple-hit exception ? source: multiple itlb address matches ? transition address: h'a000 0000 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. exception code h'140 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed in the same way as in a manual reset. for details, see the register de scriptions in the relevant sections. tlb_multi_hit() { tea = exception_address; pteh.vpn = page_number; expevt = h'00000140; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; }
5. exceptions rev.4.00 oct. 10, 2008 page 151 of 1122 rej09b0370-0400 (5) data tlb multiple-hit exception ? source: multiple utlb address matches ? transition address: h'a000 0000 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. exception code h'140 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed in the same way as in a manual reset. for details, see the register de scriptions in the relevant sections. tlb_multi_hit() { tea = exception_address; pteh.vpn = page_number; expevt = h'00000140; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; }
5. exceptions rev.4.00 oct. 10, 2008 page 152 of 1122 rej09b0370-0400 5.6.2 general exceptions (1) data tlb miss exception ? source: address mismatch in utlb address comparison ? transition address: vbr + h'0000 0400 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'040 (for a read access) or h' 060 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0400. to speed up tlb miss processing, the offset is separate from that of other exceptions. data_tlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'00000040 : h'00000060; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000400; }
5. exceptions rev.4.00 oct. 10, 2008 page 153 of 1122 rej09b0370-0400 (2) instruction tlb miss exception ? source: address mismatch in itlb address comparison ? transition address: vbr + h'0000 0400 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'040 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0400. to speed up tlb miss processing, the offset is separate from that of other exceptions. itlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'00000040; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000400; }
5. exceptions rev.4.00 oct. 10, 2008 page 154 of 1122 rej09b0370-0400 (3) initial page write exception ? source: tlb is hit in a store access, but dirty bit d = 0 ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'080 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. initial_write_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'00000080; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 155 of 1122 rej09b0370-0400 (4) data tlb protectio n violation exception ? source: the access does not a ccord with the utlb protection information (pr bits) shown below. pr privileged mo de user mode 00 only read access possible access not possible 01 read/write access possible access not possible 10 only read access possible only read access possible 11 read/write access possible read/write access possible ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'0a0 (for a read access) or h' 0c0 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. data_tlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'000000a0 : h'000000c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 156 of 1122 rej09b0370-0400 (5) instruction tlb protection violation exception ? source: the access does not a ccord with the itlb protection information (pr bits) shown below. pr privileged mo de user mode 0 access possible access not possible 1 access possibl e access possible ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'0a0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. itlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'000000a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 157 of 1122 rej09b0370-0400 (6) data address error ? sources: ? word data access from other than a word boundary (2n +1) ? longword data access from other than a longwor d data boundary (4n +1, 4n + 2, or 4n +3) ? quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ? access to area h'8000 0000?h'ffff ffff in user mode ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'0e0 (for a read access) or h'10 0 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. for details, see section 3, memory management unit (mmu). data_address_error() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access? h'000000e0: h'00000100; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 158 of 1122 rej09b0370-0400 (7) instruction address error ? sources: ? instruction fetch from other than a word boundary (2n +1) ? instruction fetch from area h'8000 0000?h'ffff ffff in user mode ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in the spc and ssr. the r15 contents at this time are saved in sgr. exception code h'0e0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. for details, see section 3, memory management unit (mmu). instruction_address_error() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'000000e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 159 of 1122 rej09b0370-0400 (8) unconditional trap ? source: execution of trapa instruction ? transition address: vbr + h'0000 0100 ? transition operations: as this is a processing-completion-type exception, the pc contents for the instruction following the trapa instruction are saved in spc. the value of sr and r15 when the trapa instruction is executed are saved in ssr and sgr. the 8-bit immediate value in the trapa instruction is multiplied by 4, and the result is set in tra [9:0]. exception code h'160 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. trapa_exception() { spc = pc + 2; ssr = sr; sgr = r15; tra = imm << 2; expevt = h'00000160; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 160 of 1122 rej09b0370-0400 (9) general illegal instruction exception ? sources: ? decoding of an undefined instruction not in a delay slot delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fffd ? decoding in user mode of a privileged instruction not in a delay slot privileged instructions: ldc, stc, rt e, ldtlb, sleep, but excluding ldc/stc instructions that access gbr ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'180 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. operation is not guaranteed if an undefined code other than h'fffd is decoded. general_illegal_instruction_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000180; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 161 of 1122 rej09b0370-0400 (10) slot illegal instruction exception ? sources: ? decoding of an undefined instruction in a delay slot delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fffd ? decoding of an instruction that modifies pc in a delay slot instructions that modify pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm,sr, ldc.l @rm+,sr ? decoding in user mode of a privileged instruction in a delay slot privileged instructions: ldc, stc, rt e, ldtlb, sleep, but excluding ldc/stc instructions that access gbr ? decoding of a pc-relative mo v instruction or mova instruction in a delay slot ? transition address: vbr + h'0000 0100 ? transition operations: the pc contents for the preceding delayed bran ch instruction are saved in spc. the sr and r15 contents when this exception occurred are saved in ssr and sgr. exception code h'1a0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. operation is not guaranteed if an undefined code other than h'fffd is decoded. slot_illegal_instruction_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'000001a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 162 of 1122 rej09b0370-0400 (11) general fpu disable exception ? source: decoding of an fpu instruction* not in a delay slot with sr.fd =1 ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'800 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. note: * fpu instructions are instructions in which the first 4 bits of the instruction code are h'f (but excluding undefined instruction h'fffd), and the lds, sts, lds.l, and sts.l instructions corresponding to fpul and fpscr. general_fpu_disable_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000800; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 163 of 1122 rej09b0370-0400 (12) slot fpu disable exception ? source: decoding of an fpu instruction in a delay slot with sr.fd =1 ? transition address: vbr + h'0000 0100 ? transition operations: the pc contents for the preceding delayed bran ch instruction are saved in spc. the sr and r15 contents when this exception occurred are saved in ssr and sgr. exception code h'820 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. slot_fpu_disable_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'00000820; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 164 of 1122 rej09b0370-0400 (13) user breakpoint trap ? source: fulfilling of a break condition set in the user break controller ? transition address: vbr + h'0000 0100, or dbr ? transition operations: in the case of a post-executi on break, the pc contents for the instruction following the instruction at which the breakpoint is set are se t in spc. in the case of a pre-execution break, the pc contents for the instruction at wh ich the breakpoint is set are set in spc. the sr and r15 contents when the break occurred are saved in ssr and sgr. exception code h'1e0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. it is also possible to branch to pc = dbr. for details of pc, etc., when a data break is se t, see section 20, user break controller (ubc). user_break_exception() { spc = (pre_execution break? pc : pc + 2); ssr = sr; sgr = r15; expevt = h'000001e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = (brcr.ubde==1 ? dbr : vbr + h'00000100); }
5. exceptions rev.4.00 oct. 10, 2008 page 165 of 1122 rej09b0370-0400 (14) fpu exception ? source: exception due to execution of a floating-point operation ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr . the r15 contents at this time are sa ved in sgr. exception code h'120 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. fpu_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000120; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
5. exceptions rev.4.00 oct. 10, 2008 page 166 of 1122 rej09b0370-0400 5.6.3 interrupts (1) nmi ? source: nmi pin edge detection ? transition address: vbr + h'0000 0600 ? transition operations: the pc and sr contents for the instruction at which this excep tion is accepted are saved in spc and ssr. the r15 contents at this time are saved in sgr. exception code h'1c0 is set in intevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0600. when the bl bit in sr is 0, this interrupt is not masked by the interrupt mask bits in sr, and is accepted at th e highest priority level. when the bl bit in sr is 1, a software setting can specify whether this interrupt is to be masked or accepted. for details, see section 19, interrupt controller (intc). nmi() { spc = pc; ssr = sr; sgr = r15; intevt = h'000001c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
5. exceptions rev.4.00 oct. 10, 2008 page 167 of 1122 rej09b0370-0400 (2) irl interrupts ? source: the interrupt mask bit setting in sr is smaller than the irl (3?0) level, and the bl bit in sr is 0 (accepted at instruction boundary). ? transition address: vbr + h'0000 0600 ? transition operations: the pc contents immediately afte r the instruction at which the interrupt is accepted are set in spc. the sr and r15 contents at the tim e of acceptance are set in ssr and sgr. the code corresponding to the irl (3?0) level is set in intevt. see table 19.4, for the corresponding codes. the bl, md , and rb bits are set to 1 in sr, and a branch is made to vbr + h'0600. the acceptance level is not set in the interrupt mask bits in sr. when the bl bit in sr is 1, the interrupt is masked. for deta ils, see section 19, interrupt controller (intc). irl() { spc = pc; ssr = sr; sgr = r15; intevt = h'00000200 ~ h'000003c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
5. exceptions rev.4.00 oct. 10, 2008 page 168 of 1122 rej09b0370-0400 (3) peripheral module interrupts ? source: the interrupt mask bit setting in sr is smaller than the peri pheral module (h-udi, gpio, dmac, pcic, tmu, rtc, sci, scif, wdt, or ref) interrupt level, and the bl bit in sr is 0 (accepted at instruction boundary). ? transition address: vbr + h'0000 0600 ? transition operations: the pc contents immediately afte r the instruction at which the interrupt is accepted are set in spc. the sr and r15 contents at the tim e of acceptance are set in ssr and sgr. the code corresponding to the interrupt source is set in intevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to vbr + h'0600. the module interrupt levels should be set as values between b'0000 and b'1111 in the interrupt priority registers (ipra?iprc) in the interrupt controller. for details, see section 19, interrupt controller (intc). module_interruption() { spc = pc; ssr = sr; sgr = r15; intevt = h'00000400 ~ h'00000b40; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
5. exceptions rev.4.00 oct. 10, 2008 page 169 of 1122 rej09b0370-0400 5.6.4 priority order wi th multiple exceptions with some instructions , such as instructions that ma ke two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. care is required in these cases, as the exception priority order differs from the normal order. 1. instructions that make two accesses to memory with mac instructions, memory-to-memory arithmetic/logic instructions, and tas instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. in these cases, therefor e, the following order is used to determine priority. a. data address error in first data transfer b. tlb miss in first data transfer c. tlb protection violation in first data transfer d. initial page write exception in first data transfer e. data address error in second data transfer f. tlb miss in second data transfer g. tlb protection violation in second data transfer h. initial page write exception in second data transfer 2. indivisible delayed branch instruction and delay slot instruction as a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instructi on. consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. the priority order shown below is for the case where the delay slot instruction has only one data transfer. a. a check is performed for the abort type and r eexecution type exceptions of priority levels 1 and 2 in the delayed branch instruction. b. a check is performed for the abort type and r eexecution type exceptions of priority levels 1 and 2 in the delay slot instruction. c. a check is performed for the completion type exception of priority level 2 in the delayed branch instruction. d. a check is performed for the completion type exception of priority level 2 in the delay slot instruction. e. a check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction. (there is no priority ranking between these two.) f. a check is performed for priority level 4 in the delayed branch instruction and priority level 4 in the delay slot instruction. (there is no priority ranking between these two.)
5. exceptions rev.4.00 oct. 10, 2008 page 170 of 1122 rej09b0370-0400 if the delay slot instruction has a second data transfer, two checks are performed in step b, as in 1 above. if the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instru ction pr register write operation (pc pr operation performed in bsr, bsrf, jsr) is not inhibited. 5.7 usage notes 1. return from exception handling a. check the bl bit in sr with software. if spc and ssr have been saved to external memory, set the bl bit in sr to 1 before restoring them. b. issue an rte instruction. wh en rte is executed, the spc c ontents are set in pc, the ssr contents are set in sr, and branch is made to the spc address to return from the exception handling routine. 2. if a general exception or inte rrupt occurs when sr.bl = 1 a. general exception when a general exception other than a user break occurs, manual reset occurs. the value in expevt at this time is h'0000 0020; the value of the spc and ssr registers is undefined. b. interrupt if an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the bl bit in sr has been cleared to 0 by software. if a nonmaskable interrupt (nmi) occurs, it can be held pending or accepted accord ing to the setting made by software. in the sleep or standby state, however, an interrupt is accepted even if the bl bit in sr is set to 1. 3. spc when an exception occurs a. re-execution type general exception the pc value for the instruction in which the general exception occurred is set in spc, and the instruction is re-executed after returning from exception handling. if an exception occurs in a delay slot instruction, however, the pc value for the delay slot instruction is saved in spc regardless of whether or no t the preceding delayed branch instruction condition is satisfied. b. completion type general exception or interrupt the pc value for the instruction following that in which the general exception occurred is set in spc. if an exception occurs in a branch instruction with delay slot, however, the pc value for the branch destination is saved in spc. 4. an exception must not be generated in an rte instruction delay slot, as the operation will be undefined in this case.
5. exceptions rev.4.00 oct. 10, 2008 page 171 of 1122 rej09b0370-0400 5.8 restrictions 1. restrictions on first instruction of exception handling routine ? do not locate a bt, bf, bt/s, bf/s, bra, or bsr instruction at address vbr + h'100, vbr + h'400, or vbr + h'600. ? when the ubde bit in the brcr register is set to 1 and the user break debug support function* is used, do not locate a bt, bf, bt/s , bf/s, bra, or bsr instruction at the address indicated by the dbr register. note: * see section 20.4, user break debug support function.
5. exceptions rev.4.00 oct. 10, 2008 page 172 of 1122 rej09b0370-0400
6. floating-point unit rev.4.00 oct. 10, 2008 page 173 of 1122 rej09b0370-0400 section 6 floating-point unit 6.1 overview the floating-point unit (fpu) has the following features: ? conforms to ieee754 standard ? 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) ? two rounding modes: round to nearest and round to zero ? two denormalization modes: flush to zero and treat denormalized number ? six exception sources: fpu error, invalid operation, divide by zero, overflow, underflow, and inexact ? comprehensive instructions: single-precision, double-precision, graphics support, system control when the fd bit in sr is set to 1, the fpu ca nnot be used, and an attempt to execute an fpu instruction will cause an fpu disable exception. 6.2 data formats 6.2.1 floating-point format a floating-point number consists of the following three fields: ? sign (s) ? exponent (e) ? fraction (f) the fpu can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 31 se f 30 23 22 0 figure 6.1 format of single -precision floati ng-point number
6. floating-point unit rev.4.00 oct. 10, 2008 page 174 of 1122 rej09b0370-0400 63 se f 62 52 51 0 figure 6.2 format of double -precision floating-point number the exponent is expressed in biased form, as follows: e = e + bias the range of unbiased exponent e is e min ? 1 to e max + 1. the two values e min ? 1 and e max + 1 are distinguished as follows. e min ? 1 indicates zero (both positive and negative sign) and a denormalized number, and e max + 1 indicates positive or negative infinity or a non-number (nan). table 6.1 shows bias, e min , and e max values. table 6.1 floating-point number formats and parameters parameter single-preci sion double-precision total bit width 32 bits 64 bits sign bit 1 bit 1 bit exponent field 8 bits 11 bits fraction field 23 bits 52 bits precision 24 bits 53 bits bias +127 +1023 e max +127 +1023 e min ?126 ?1022 floating-point number value v is determined as follows: if e = e max + 1 and f 0, v is a non-number (nan) irrespective of sign s if e = e max + 1 and f = 0, v = (?1) s (infinity) [positive or negative infinity] if e min e e max , v = (?1) s 2 e (1.f) [normalized number] if e = e min ? 1 and f 0, v = (?1) s 2 emin (0.f) [denormalized number] if e = e min ? 1 and f = 0, v = (?1) s 0 [positive or negative zero] table 6.2 shows the ranges of the various numbers in hexadecimal notation.
6. floating-point unit rev.4.00 oct. 10, 2008 page 175 of 1122 rej09b0370-0400 table 6.2 floating-point ranges type single-precision double-precision signaling non-numbe r h'7fffffff to h'7fc00000 h'7fffffff ffffffff to h'7ff80000 00000000 quiet non-number h'7fbfffff to h' 7f800001 h'7ff7ffff ffffffff to h'7ff00000 00000001 positive infinity h'7f800000 h'7ff00000 00000000 positive normalized number h'7f7fffff to h'00800000 h' 7fefffff ffffffff to h'00100000 00000000 positive denormalized number h'007fffff to h'00000001 h' 000fffff ffffffff to h'00000000 00000001 positive zero h'00000000 h'00000000 00000000 negative zero h'80000000 h'80000000 00000000 negative denormalized number h'80000001 to h'807fffff h'800 00000 00000001 to h'800fffff ffffffff negative normalized number h'80800000 to h'ff7fffff h' 80100000 0000 0000 to h'ffefffff ffffffff negative infinity h'ff 800000 h'fff00000 00000000 quiet non-number h'ff800001 to h'ffb fffff h'fff00000 00000001 to h'fff7ffff ffffffff signaling non-number h'ffc00000 to h'ffffffff h'fff80000 00000000 to h'ffffffff ffffffff 6.2.2 non-numbers (nan) figure 6.3 shows the bit pattern of a non-number (nan). a value is nan in the following case: ? sign bit: don't care ? exponent field: all bits are 1 ? fraction field: at least one bit is 1 the nan is a signaling nan (snan) if the msb of the fraction field is 1, and a quiet nan (qnan) if the msb is 0.
6. floating-point unit rev.4.00 oct. 10, 2008 page 176 of 1122 rej09b0370-0400 31 x 11111111 nxxxxxxxxxxxxxxxxxxxxxx 30 23 22 0 n = 1: snan n = 0: qnan figure 6.3 single-precision nan bit pattern an snan is input in an operation, except copy, fabs, and fneg, that generates a floating-point value. ? when the en.v bit in the fpscr register is 0, the operation result (output) is a qnan. ? when the en.v bit in the fpscr register is 1, an invalid operation exception will be generated. in this case, the contents of the operation destination register are unchanged. if a qnan is input in an operation that generates a floating-point value, and an snan has not been input in that operation, the output will always be a qnan irrespective of the setting of the en.v bit in the fpscr register. an exception will not be generated in this case. the qnan values generated by the fpu as operation results are as follows: ? single-precision qnan: h'7fbfffff ? double-precision qnan: h'7ff7ffff ffffffff see the individual instruction descriptions for details of floating-point operations when a non- number (nan) is input. 6.2.3 denormalized numbers for a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. when the dn bit in the fpu's status register f pscr is 1, a denormalized number (source operand or operation result) is always flushed to 0 in a floating-point operation that generates a value (an operation other than copy, fneg, or fabs). when the dn bit in fpscr is 0, a denormalized number (source operand or operation result) is processed as it is. see the individual instruction descriptions for details of floating-point operations when a denormalized number is input.
6. floating-point unit rev.4.00 oct. 10, 2008 page 177 of 1122 rej09b0370-0400 6.3 registers 6.3.1 floating-point registers figure 6.4 shows the floating-point register conf iguration. there are thirty-two 32-bit floating- point registers, referenced by specifying fr0?fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0? xf15, xd0/2/4/6/8/10/12/14, or xmtrx. 1. floating-point registers, fpri_bankj (32 registers) fpr0_bank0?fpr15_bank0 fpr0_bank1?fpr15_bank1 2. single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0?fr15 in dicate fpr0_bank0?fpr15_bank0; when fpscr.fr = 1, fr0?fr15 in dicate fpr0_bank1?fpr15_bank1. 3. double-precision floating-point registers, dri (8 registers): a dr regi ster comprises two fr registers dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} 4. single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} 5. single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0?xf15 in dicate fpr0_bank1?fpr15_bank1; when fpscr.fr = 1, xf0?xf15 in dicate fpr0_bank0?fpr15_bank0. 6. double-precision floating-point extended registers, xdi (8 registers): an xd register comprises two xf registers xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15}
6. floating-point unit rev.4.00 oct. 10, 2008 page 178 of 1122 rej09b0370-0400 7. single-precision floating-point extended register matrix: xmtrx xmtrx comprises all 16 xf registers xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 fpr0 _bank0 fpr1_bank0 fpr2_bank0 fpr3_bank0 fpr4_bank0 fpr5_bank0 fpr6_bank0 fpr7_bank0 fpr8_bank0 fpr9_bank0 fpr10_bank0 fpr11_bank0 fpr12_bank0 fpr13_bank0 fpr14_bank0 fpr15_bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0_bank1 fpr1_bank1 fpr2_bank1 fpr3_bank1 fpr4_bank1 fpr5_bank1 fpr6_bank1 fpr7_bank1 fpr8_bank1 fpr9_bank1 fpr10_bank1 fpr11_bank1 fpr12_bank1 fpr13_bank1 fpr14_bank1 fpr15_bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr = 0 fpscr.fr = 1 figure 6.4 floating-point registers
6. floating-point unit rev.4.00 oct. 10, 2008 page 179 of 1122 rej09b0370-0400 6.3.2 floating-point status/control register (fpscr) floating-point status/control register, fpscr (32 bits, initial value = h'0004 0001) 31 22 21 20 19 18 17 12 11 7 6 2 1 0 ? fr sz pr dn cause enable flag rm note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? fr: floating-point register bank fr = 0: fpr0_bank0?fpr15_bank0 are assigned to fr0?fr15; fpr0_bank1? fpr15_bank1 are assigned to xf0?xf15. fr = 1: fpr0_bank0?fpr15_bank0 are assigned to xf0?xf15; fpr0_bank1? fpr15_bank1 are assigned to fr0?fr15. ? sz: transfer size mode sz = 0: the data size of the fmov instruction is 32 bits. sz = 1: the data size of the fmov instruc tion is a 32-bit register pair (64 bits). ? pr: precision mode pr = 0: floating-point instructions are executed as single-precision operations. pr = 1: floating-point instructions are executed as double-precision operations (graphics support instructions are undefined). do not set sz and pr to 1 simultaneously; this setting is reserved. [sz, pr = 11]: reserved (fpu operation instruction is undefined.) ? dn: denormalization mode dn = 0: a denormalized number is treated as such. dn = 1: a denormalized nu mber is treated as zero. ? cause: fpu exception cause field ? enable: fpu exception enable field
6. floating-point unit rev.4.00 oct. 10, 2008 page 180 of 1122 rej09b0370-0400 ? flag: fpu exception flag field fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2 when an fpu operation instruction is executed, the fpu exception cause field is cleared to zero first. when the next fpu exception is occurred, the correspondi ng bits in the fpu exception cause field and fpu excep tion flag field are set to 1. the fpu exception flag field holds the status of the exception gene rated after the field was last cleared. ? rm: rounding mode rm = 00: round to nearest rm = 01: round to zero rm = 10: reserved rm = 11: reserved ? bits 22 to 31: reserved these bits are always read as 0, and should only be written with 0. 6.3.3 floating-point communication register (fpul) information is transferred between the fpu and cpu via the fpul regist er. the 32-bit fpul register is a system register, and is accessed from the cpu side by means of lds and sts instructions. for example, to convert the integer stor ed in general register r1 to a single-precision floating-point number, the processing flow is as follows: r1 (lds instruction) fpul (single-precision float instruction) fr1
6. floating-point unit rev.4.00 oct. 10, 2008 page 181 of 1122 rej09b0370-0400 6.4 rounding in a floating-point instruction, rounding is pe rformed when generating the final operation result from the intermediate result. therefore, the result of combination instructions such as fmac, ftrv, and fipr will differ from the result when using a basic instruction such as fadd, fsub, or fmul. rounding is performed once in fmac, but twice in fadd, fsub, and fmul. there are two rounding methods, the method to be used being determined by the rm field in fpscr. ? rm = 00: round to nearest ? rm = 01: round to zero round to nearest: the operation result is rounded to the nearest expressible value. if there are two nearest expressible values, the on e with an lsb of 0 is selected. if the unrounded value is 2 emax (2 ? 2 ?p ) or more, the result will be infinity with the same sign as the unrounded value. the values of emax and p, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. round to zero: the digits below the round bit of the unrounded value are discarded. if the unrounded value is larger than the maximum expressible absolute value, the value will be the maximum expressibl e absolute value. 6.5 floating-point exceptions fpu-related exceptions are as follows: ? general illegal instruction/slot illegal instruction exception the exception occurs if an fpu instru ction is executed when sr.fd = 1. ? fpu exceptions the exception sources are as follows: ? fpu error (e): when fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): in case of an invalid operation, such as nan input ? division by zero (z): division with a zero divisor ? overflow (o): when the operation result overflows ? underflow (u): when the operation result underflows ? inexact exception (i): when overflow, underflow, or rounding occurs
6. floating-point unit rev.4.00 oct. 10, 2008 page 182 of 1122 rej09b0370-0400 the fpscr fpu exception cause field contains bits corresponding to all of above e, v, z, o, u, and i, and the fpscr flag and enable fields contain bits corres ponding to v, z, o, u, and i, but not e. thus, fpu errors cannot be disabled. when an fpu exception occurs, the corresponding bit in the fpu exception cause field is set to 1, and 1 is added to the corresponding bit in the fpu exception flag field. when an fpu exception does not occur, the corr esponding bit in the fpu excepti on cause field is cleared to 0, but the corresponding bit in the fpu exception flag field remains unchanged. ? enable/disable exception handling the fpu supports enable exception handling and disable exception handling. enable exception handling is initiated in the following cases: ? fpu error (e): fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): fpscr.en.v = 1 and (i nstruction = ftrv or invalid operation) ? division by zero (z): fpscr.en.z = 1 and division with a zero divisor ? overflow (o): fpscr.en.o = 1 and instruction with possibility of operation result overflow ? underflow (u): fpscr.en.u = 1 and instruction with possibility of operation result underflow ? inexact exception (i): fpscr.en.i = 1 and instru ction with possibility of inexact operation result for information on possibilities (which differ depending on the individual instruction), see section 9, instruction descriptions, in the sh-4 software manual . all exception events that originate in the fpu are assigned as the same ex ception event. the meaning of an exception is determined by software by reading system regi ster fpscr and interpreting the information it contains. if no bits are set in the fpu exception cause field of fpscr when one or more of bits o, u, i, and v (in case of ftrv only) are set in the fpu exception enable field, this indicates that an actual fpu exception is not generated. al so, the destination register is not changed by any fpu exception handling operation. except for the above, the bit corresponding to v, z, o, u, or i is set to 1 in all processing, and the default value is generated as the result of the operation. ? invalid operation (v): qnan is generated as the result. ? division by zero (z): infinity with the same sign as the unrounded value is generated. ? overflow (o): in round to zero mode, the maximum normali zed number, with the same sign as the unrounded value, is generated. in round to nearest mode, infinity with the same sign as the unrounded value is generated.
6. floating-point unit rev.4.00 oct. 10, 2008 page 183 of 1122 rej09b0370-0400 ? underflow (u): when fpscr.dn = 0, a denormalized number w ith the same sign as the unrounded value, or zero with the same sign as the unrounded value, is generated. when fpscr.dn = 1, zero with the same sign as the unrounded value, is generated. ? inexact exception (i): an inexact result is generated. 6.6 graphics support functions the fpu supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 geometric operation instructions geometric operation instructions perform approximate-value computations. to enable high-speed computation with a minimum of hardware, the fp u ignores comparatively small values in the partial computation results of four multiplications. consequently, the error shown below is produced in the result of the computation: maximum error = max (individ ual multiplication result 2 ?min (number of multiplier significant digits?1, number of multiplicand significant digits?1) ) + max (result value 2 ?23 , 2 ?149 ) the number of significant digits is 24 for a norm alized number and 23 fo r a denormalized number (number of leading zeros in the fractional part). in future version of superh risc engine family, the above error is guaranteed, but the same result as sh7751 group is not guaranteed. fipr fvm, fvn (m, n: 0, 4, 8, 12): examples of the use of this instruction are given below. ? inner product (m n): this operation is generally used for surface/r ear surface determination for polygon surfaces. ? sum of square of elements (m = n): this operation is generally used to find the length of a vector. since approximate-value computations are performed to enable high-speed computation, the inexact exception (i) bit in the fpu exception caus e field and fpu exception flag field is always set to 1 when an fipr instruction is executed. ther efore, if the corresponding bit is set in the fpu exception enable field, fpu exception handling will be executed.
6. floating-point unit rev.4.00 oct. 10, 2008 page 184 of 1122 rej09b0370-0400 ftrv xmtrx, fvn (n: 0, 4, 8, 12): examples of the use of this instruction are given below. ? matrix (4 4) ? vector (4): this operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). since affine transformation processing for angle + parallel movement basically requires a 4 4 matrix, the fpu supports 4-dimensional operations. ? matrix (4 4) matrix (4 4): this operation requires the execution of four ftrv instructions. since approximate-value computations are performed to enable high-speed computation, the inexact exception (i) bit in the fpu exception caus e field and fpu exception flag field is always set to 1 when an ftrv instruction is executed. therefore, if the corresponding bit is set in the fpu exception enable field, fpu exception handling will be executed. for the same reason, it is not possible to check all data types in the registers beforehand when executing an ftrv instruction. if the v bit is set in the fpu exception enable field, fpu exception handling will be executed. frchg: this instruction modifies banked registers. for example, when the ftrv instruction is executed, matrix elements must be set in an arra y in the background bank. however, to create the actual elements of a translation matrix, it is easie r to use registers in the foreground bank. when the ldc instruction is used on fpscr, this instru ction expends 4 to 5 cycles in order to maintain the fpu state. with the frchg instruction, an fpscr.fr bit modification can be performed in one cycle. 6.6.2 pair single-precision data transfer the powerful geometric operation instructions, fpu also supports high-speed data transfer instructions. when fpscr.sz = 1, fpu can perform data transfer by means of pair single-precision data transfer instructions. ? fmov drm/xdm, drn/xdrn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) ? fmov drm/xdm, @rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15) these instructions enable two single-precision (2 32-bit) data items to be transferred; that is, the transfer performance of thes e instructions is doubled.
6. floating-point unit rev.4.00 oct. 10, 2008 page 185 of 1122 rej09b0370-0400 ? fschg this instruction changes the value of the sz bit in fpscr, enabling fast switching between use and non-use of pair single-precision data transfer. programming note: when fpscr.sz = 1 and big-endian mode is used, fmov can be used for a double-precision floating-point load or store. in little-endian mode, a double-precision floating-point load or store requires execution of two 32-bit data size operations with fpscr.sz = 0. 6.7 usage notes 6.7.1 rounding mode and underflow flag when using the round to nearest rounding mode, the underflow flag may not be set in cases defined as underflow by the ieee754 standard. under the ieee754 standard, when the round to nearest rounding mode is used and infinite- precision operation result x is (i) or (ii) (single-precision) or (iii) or (iv) (doubl e-precision), there are cases where ?the result after rounding is a normalized number, but an underflow results.? in such cases where ?the result after rounding is a normalized number, but an underflow results,? the fpu does not set the underflow flag to 1. in these cases the operation result, the value written to frn, is correct. also, if an fpu exception oc curs, the underflow flag is not set to 1 but the inexact flag is set to 1 in such cases. generati on of fpu exceptions can be enabled by setting the enable field to 1. (i) h'007fffff < x < h'00800000 (ii) h'807fffff > x > h'80800000 (iii) h'000fffff ffffffff < x < h'00100000 00000000 (iv) h'800fffff ffffffff > x > h'80100000 00000000 examples ? single-precision when fpscr.rm = 00 (round to nearest) and fpscr.pr = 0 (single-precision), and the fmul instruction (h'00fff000 * h'3f000800) is executed. a. according to ieee754 standard operation result: h'00800000 fpscr: h'0004300c
6. floating-point unit rev.4.00 oct. 10, 2008 page 186 of 1122 rej09b0370-0400 b. fpu operation result: h'00800000 fpscr: h'00041004 ? double-precision when fpscr.rm = 00 (round to nearest) and fpscr.pr = 1 (double-precision), and the fdiv instruction (h'001fffff ffffffff / h'40000000 00000000) is executed. a. according to ieee754 standard operation result: h'00100000 00000000 fpscr: h'000c300c b. fpu operation result: h'00100000 00000000 fpscr: h'000c1004 workarounds 1. use fpscr.rm = 01, that is to say round to zero rather than round to nearest mode. 2. use fpscr.rm = 00, that is to say round to nearest mode, and set the enable field to 1 to enable generation of inexact ex ceptions so that the exception ha ndling routine can be used to check whether or not an underflow has occurred. 6.7.2 setting of overflow flag by fipr or ftrv instruction when the maximum error produced by the fipr or ftrv instruction exceeds the maximum value expressible as a normalized nu mber (h'7f7fffff), the overflow fl ag may be set, even through the operation result is a positive or ne gative zero (h'00000000 or h'80000000). example: the operation result (fr7) after executin g the instruction fipr fv4, fv0 is h'00000000 (positive zero), but the overfl ow flag may be set nevertheless. fpscr = h'00040001 fr0 = h'ff7ef631 , fr1 = h80000000 , fr2 = h'8087f451 , fr3 = h'7f7ef631 fr4 = h'7f7ef631 , fr5 = h'0087f451 , fr6 = h'7f7ef631 , fr7 = h'7f7ef631 workaround: avoid using the fipr and ftrv instructions, and use the fadd, fmul, and fmac instruct ions instead.
6. floating-point unit rev.4.00 oct. 10, 2008 page 187 of 1122 rej09b0370-0400 6.7.3 sign of operation result when using fipr or ftrv instruction when two or more data items used in an operation by the fipr or ftrv instruction are infinity, and all of the infinity items in the multiplication results have the same sign, the sign of the operation result may be incorrect. workarounds 1. do not use infinity. if conditions (a) to (c) below are satisfied, infinity is never used in operations. a. use round to zero (fpscr. rm = 01) as the rounding mode. b. do not divide by zero. c. do not transfer a value of positive or negative infinity to fr0 to fr15 or to xf0 to xf15. 2. avoid using the fipr and ftrv instructions, and use the fadd, fmul, and fmac instructions instead. 6.7.4 notes on doub le-precision fadd and fsub instructions description: if the input data for a double-precision fadd instruction or a double-precision fsub instruction satisfies all of the conditions lis ted below, the inexact bits (fpscr.flag.i and fpscr.cause.i) may not be set even through the operation result is inexact. condition 1: the operation instruction is a double-precision fadd instruction or a double- precision fsub instruction. condition 2: the di fference between the drn and drm ex ponents is between 43 and 50. condition 3: at least one of bits 31 to 24 of the mantissa portion of whichever of drn and drm has the smaller absolute value is 1. condition 4: bits 23 to 0 of the mantissa portion of whichever of drn and drm has the smaller absolute value are all 0. condition 5: bits 40 to 32 of the mantissa portion of whichever of drn and drm has the smaller absolute value are all 0. in addition, the result of an operation meeting the above conditions may have a rounding error. specifically, in a case where the closest expressibl e value less than the unro unded value should be selected, the closest expressible value greater than the unrounde d value is selected instead. conversely, in a case wher e the closest expressible value greater than the unrounded value should be selected, the closest expressi ble value less than the unrou nded value is selected instead.
6. floating-point unit rev.4.00 oct. 10, 2008 page 188 of 1122 rej09b0370-0400 example: if the double-precision fsub instruction (fsub dr0, dr2) is executed with input data dr0 = h'c1f00000 80000000, dr2 = h'c4b250d2 0cc1fb74, and fpscr = h'000c0001, the correct operation result is dr2 = h'c4b250d2 0cc1f973, and fpscr.flag.i and fpscr.cause.i should be set to 1. however, the result actually produced by the fpu is dr2 = h'c4b250d2 0cc1f974, and fpscr.flag.i and fpscr.cause.i are not set to 1. effects: in addition to the problem described above , the numerical size of the result of the operation may contain a minute operation error equivalent to 1/256 of the lsb of the mantissa of the unrounded value. this is can be described as within the scope of the subsequent rounding mechanism. strictly speaking, it consists of the following. a: the infinite-pr ecision operation result b: the closest expressible value less than a c: the closest expressible value greater than a d: the operation result when a is rounded correctly e: the operation result when a is rounded by the fpu ? the rounding error when rounding is performed correctly in round to nearest mode is: 0 | d ? a | (1/2) (c ? b ) and the rounding error when rounding is performed by the fpu is: 0 | e ? a | < (129/256) ( c ? b ) if c ? b is considered the lsb of the mantissa, the range of rounding error is equivalent to 1/256 of the lsb of the mantissa of the correctly rounded value. ? the rounding error when rounding is performed correctly in round to zero mode is: ( ? 1) (c ? b) < | d |?| a | 0 and the rounding error when rounding is performed by the fpu is: ( ? 1) (c ? b) < | e |?| a | < (1/256) (c ? b) if c ? b is considered the lsb of the mantissa, the range of rounding error is equivalent to 1/256 of the lsb of the mantissa of the correctly rounded value.
7. instruction set rev.4.00 oct. 10, 2008 page 189 of 1122 rej09b0370-0400 section 7 instruction set 7.1 execution environment pc: pc indicates the address of the instruction itself. data sizes and data types: the sh-4 instruction set is implemented with 16-bit fixed-length instructions. the sh-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64- bit) data sizes for memory access. single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. double-precision floating-point data (64 bits) can be moved to and from memory using longword size. when a double-precision floating-point operation is specified (fpscr.pr = 1), the result of an operation using quadword access will be undefined. when the sh-4 moves byte-size or word-size data from memory to a register, the data is sign-extended. load-store architecture: the sh-4 features a load-store ar chitecture in which operations are basically executed using registers. except for bit-manipulation operations such as logical and that are executed directly in memory, operands in an operati on that requires memory access are loaded into registers and the operatio n is executed between the registers. delayed branches: except for the two bran ch instructions bf an d bt, the sh-4 branch instructions and rte are delayed branches. in a delayed branch, the instruction following the branch is executed before the branch destination instruction. this execution slot following a delayed branch is called a delay slot. for example, the bra execution sequence is as follows: static sequence dynamic sequence bra target bra target add r1, r0 next_2 add r1, r0 target_instr add in delay slot is executed before branching to target delay slot: a slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. see section 5, exceptions. the instruction following bf/s or bt/s for which the branch is not taken is also a delay slot instruction.
7. instruction set rev.4.00 oct. 10, 2008 page 190 of 1122 rej09b0370-0400 t bit: the t bit in the status register (sr) is used to show the result of a compare operation, and is referenced by a conditional branch instruction. an example of the use of a conditional branch instruction is shown below. add #1, r0 ; t bit is not changed by add operation cmp/eq r1, r0 ; if r0 = r1, t bit is set to 1 bt target ; branches to target if t bit = 1 (r0 = r1) in an rte delay slot, status register (sr) bits ar e referenced as follows. in instruction access, the md bit is used before modification, and in data access, the md bit is accessed after modification. the other bits?s, t, m, q, fd, bl, and rb?after modification are used for delay slot instruction execution. the stc and stc.l sr inst ructions access all sr bits after modification. constant values: an 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a pc-relative load instruction. mov.w @(disp, pc), rn mov.l @(disp, pc), rn there are no pc-relative load instructions for floa ting-point operations. however, it is possible to set 0.0 or 1.0 by using the fldi0 or fldi1 instruction on a single-precision floating-point register.
7. instruction set rev.4.00 oct. 10, 2008 page 191 of 1122 rej09b0370-0400 7.2 addressing modes addressing modes and effective address calculation methods are shown in table 7.1. when a location in virtual memory space is accessed (mmucr. at = 1), the effective address is translated into a physical address. if multiple virtual me mory space systems are se lected (mmucr.sv = 0), the least significant bit of pteh is also refere nced as the access asid. see section 3, memory management unit (mmu). table 7.1 addressing modes and effective addresses addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn ea (ea: effective address) register indirect with post- increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn rn 1/2/4/8 + rn + 1/2/4/8 rn ea after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn quadword: rn + 8 rn register indirect with pre- decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn 1/2/4/8 rn ? 1/2/4/8 ? rn ? 1/2/4/8 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn quadword: rn ? 8 rn rn ea (instruction executed with rn after calculation)
7. instruction set rev.4.00 oct. 10, 2008 page 192 of 1122 rej09b0370-0400 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp ea word: rn + disp 2 ea longword: rn + disp 4 ea indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 ea gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp ea word: gbr + disp 2 ea longword: gbr + disp 4 ea indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0 ea
7. instruction set rev.4.00 oct. 10, 2008 page 193 of 1122 rej09b0370-0400 addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8, pc) effective address is pc+4 with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc h'fffffffc pc + 4 + disp 2 or pc & h'fffffffc + 4 + disp 4 + 4 2/4 + & * disp (zero-extended) * with lon g word operand word: pc + 4 + disp 2 ea longword: pc & h'fffffffc + 4 + disp 4 ea pc-relative disp:8 effective address is pc+4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (si g n-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target
7. instruction set rev.4.00 oct. 10, 2008 page 194 of 1122 rej09b0370-0400 addressing mode instruction format effective address calculation method calculation formula pc-relative disp:12 effective address is pc+4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (si g n-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target rn effective address is sum of pc+4 and rn. pc 4 rn + + pc + 4 + rn pc + 4 + rn branch- target immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for the addressing modes below that use a di splacement (disp), the assembler descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed according to the operand size. this is done to clarify the oper ation of the chip. refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, gbr) ; gbr i ndirect with displacement @ (disp:8, pc) ; pc-relative with displacement disp:8, disp:1 2 ; pc-relative
7. instruction set rev.4.00 oct. 10, 2008 page 195 of 1122 rej09b0370-0400 7.3 instruction set table 7.2 shows the notation used in the following sh instruction list. table 7.2 notation used in instruction list item format description instruction mnemonic op.sz src, dest op: operation code sz: size src: source dest: source and/or destination operand summary of operation , : transfer direction (xx): memory operand m/q/t: sr flag bits &: logical and of individual bits |: logical or of individual bits : logical exclusive-or of individual bits ~: logical not of individual bits <>n: n-bit shift instruction code msb ? lsb mmmm: register number (rm, frm) nnnn: register number (rn, frn) 0000: r0, fr0 0001: r1, fr1 : 1111: r15, fr15 mmm: register number (drm, xdm, rm_bank) nnn: register number (drm, xdm, rn_bank) 000: dr0, xd0, r0_bank 001: dr2, xd2, r1_bank : 111: dr14, xd14, r7_bank mm: register number (fvm) nn: register number (fvn) 00: fv0 01: fv4 10: fv8 11: fv12 iiii: immediate data dddd: displacement privileged mode ?privileged? means the instruction can only be executed in privileged mode. t bit value of t bit after instruction execution ?: no change note: scaling ( 1, 2, 4, or 8) is executed according to the size of the instruction operand(s).
7. instruction set rev.4.00 oct. 10, 2008 page 196 of 1122 rej09b0370-0400 table 7.3 fixed-point transfer instructions instruction operation instruction code privileged t bit mov #imm,rn imm sign extension rn 1110nnnniiiiiiii ? ? mov.w @(disp,pc),rn (disp 2 + pc + 4) sign extension rn 1001nnnndddddddd ? ? mov.l @(disp,pc),rn (disp 4 + pc & h'fffffffc + 4) rn 1101nnnndddddddd ? ? mov rm,rn rm rn 0110nnnnmmmm0011 ? ? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 ? ? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 ? ? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 ? ? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 ? ? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 ? ? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 ? ? mov.b rm,@-rn rn-1 rn, rm (rn) 0010nnnnmmmm0100 ? ? mov.w rm,@-rn rn-2 rn, rm (rn) 0010nnnnmmmm0101 ? ? mov.l rm,@-rn rn-4 rn, rm (rn) 0010nnnnmmmm0110 ? ? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 ? ? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 ? ? mov.l @rm+,rn (rm) rn, rm + 4 rm 0110nnnnmmmm0110 ? ? mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd ? ? mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd ? ? mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd ? ? mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd ? ? mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd ? ? mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd ? ? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 ? ? mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 ? ? mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 ? ? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 ? ? mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 ? ? mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 197 of 1122 rej09b0370-0400 instruction operation instruction code privileged t bit mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd ? ? mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd ? ? mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd ? ? mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd ? ? mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd ? ? mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd ? ? mova @(disp,pc),r0 disp 4 + pc & h'fffffffc + 4 r0 11000111dddddddd ? ? movt rn t rn 0000nnnn00101001 ? ? swap.b rm,rn rm swap lower 2 bytes rn 0110nnnnmmmm1000 ? ? swap.w rm,rn rm swap upper/lower words rn 0110nnnnmmmm1001 ? ? xtrct rm,rn rm:rn middle 32 bits rn 0010nnnnmmmm1101 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 198 of 1122 rej09b0370-0400 table 7.4 arithmetic operation instructions instruction operation instruction code privileged t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 ? ? add #imm,rn rn + imm rn 0111nnnniiiiiiii ? ? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 ? carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 ? overflow cmp/eq #imm,r0 when r0 = imm, 1 t otherwise, 0 t 10001000iiiiiiii ? comparison result cmp/eq rm,rn when rn = rm, 1 t otherwise, 0 t 0011nnnnmmmm0000 ? comparison result cmp/hs rm,rn when rn rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0010 ? comparison result cmp/ge rm,rn when rn rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0011 ? comparison result cmp/hi rm,rn when rn > rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0110 ? comparison result cmp/gt rm,rn when rn > rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0111 ? comparison result cmp/pz rn when rn 0, 1 t otherwise, 0 t 0100nnnn00010001 ? comparison result cmp/pl rn when rn > 0, 1 t otherwise, 0 t 0100nnnn00010101 ? comparison result cmp/str rm,rn when any bytes are equal, 1 t otherwise, 0 t 0010nnnnmmmm1100 ? comparison result div1 rm,rn 1-step division (rn rm) 0011nnnnmmmm0100 ? calculation result div0s rm,rn msb of rn q, msb of rm m, m^q t 0010nnnnmmmm0111 ? calculation result div0u 0 m/q/t 0000000000011001 ? 0 dmuls.l rm,rn signed, rn rm mac, 32 32 64 bits 0011nnnnmmmm1101 ? ? dmulu.l rm,rn unsigned, rn rm mac, 32 32 64 bits 0011nnnnmmmm0101 ? ? dt rn rn ? 1 rn; when rn = 0, 1 t when rn 0, 0 t 0100nnnn00010000 ? comparison result exts.b rm,rn rm sign-extended from byte rn 0110nnnnmmmm1110 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 199 of 1122 rej09b0370-0400 instruction operation instruction code privileged t bit exts.w rm,rn rm sign-extended from word rn 0110nnnnmmmm1111 ? ? extu.b rm,rn rm zero-extended from byte rn 0110nnnnmmmm1100 ? ? extu.w rm,rn rm zero-extended from word rn 0110nnnnmmmm1101 ? ? mac.l @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 4 rn, rm + 4 rm 32 32 + 64 64 bits 0000nnnnmmmm1111 ? ? mac.w @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 2 rn, rm + 2 rm 16 16 + 64 64 bits 0100nnnnmmmm1111 ? ? mul.l rm,rn rn rm macl 32 32 32 bits 0000nnnnmmmm0111 ? ? muls.w rm,rn signed, rn rm macl 16 16 32 bits 0010nnnnmmmm1111 ? ? mulu.w rm,rn unsigned, rn rm macl 16 16 32 bits 0010nnnnmmmm1110 ? ? neg rm,rn 0 ? rm rn 0110nnnnmmmm1011 ? ? negc rm,rn 0 ? rm ? t rn, borrow t 0110nnnnmmmm1010 ? borrow sub rm,rn rn ? rm rn 0011nnnnmmmm1000 ? ? subc rm,rn rn ? rm ? t rn, borrow t 0011nnnnmmmm1010 ? borrow subv rm,rn rn ? rm rn, underflow t 0011nnnnmmmm1011 ? underflow
7. instruction set rev.4.00 oct. 10, 2008 page 200 of 1122 rej09b0370-0400 table 7.5 logic operation instructions instruction operation instruction code privileged t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 ? ? and #imm,r0 r0 & imm r0 11001001iiiiiiii ? ? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii ? ? not rm,rn ~rm rn 0110nnnnmmmm0111 ? ? or rm,rn rn | rm rn 0010nnnnmmmm1011 ? ? or #imm,r0 r0 | imm r0 11001011iiiiiiii ? ? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii ? tas.b @rn when (rn) = 0, 1 t otherwise, 0 t in both cases, 1 msb of (rn) 0100nnnn00011011 ? test result tst rm,rn rn & rm; when result = 0, 1 t otherwise, 0 t 0010nnnnmmmm1000 ? test result tst #imm,r0 r0 & imm; when result = 0, 1 t otherwise, 0 t 11001000iiiiiiii ? test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; when result = 0, 1 t otherwise, 0 t 11001100iiiiiiii ? test result xor rm,rn rn rm rn 0010nnnnmmmm1010 ? ? xor #imm,r0 r0 imm r0 11001010iiiiiiii ? ? xor.b #imm,@(r0,gbr) (r0 + gbr) imm (r0 + gbr) 11001110iiiiiiii ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 201 of 1122 rej09b0370-0400 table 7.6 shift instructions instruction operation instruction code privileged t bit rotl rn t rn msb 0100nnnn00000100 ? msb rotr rn lsb rn t 0100nnnn00000101 ? lsb rotcl rn t rn t 0100nnnn00100100 ? msb rotcr rn t rn t 0100nnnn00100101 ? lsb shad rm,rn when rn 0, rn << rm rn when rn < 0, rn >> rm [msb rn] 0100nnnnmmmm1100 ? ? shal rn t rn 0 0100nnnn00100000 ? msb shar rn msb rn t 0100nnnn00100001 ? lsb shld rm,rn when rn 0, rn << rm rn when rn < 0, rn >> rm [0 rn] 0100nnnnmmmm1101 ? ? shll rn t rn 0 0100nnnn00000000 ? msb shlr rn 0 rn t 0100nnnn00000001 ? lsb shll2 rn rn << 2 rn 0100nnnn00001000 ? ? shlr2 rn rn >> 2 rn 0100nnnn00001001 ? ? shll8 rn rn << 8 rn 0100nnnn00011000 ? ? shlr8 rn rn >> 8 rn 0100nnnn00011001 ? ? shll16 rn rn << 16 rn 0100nnnn00101000 ? ? shlr16 rn rn >> 16 rn 0100nnnn00101001 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 202 of 1122 rej09b0370-0400 table 7.7 branch instructions instruction operation instruction code privileged t bit bf label when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001011dddddddd ? ? bf/s label delayed branch; when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001111dddddddd ? ? bt label when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001001dddddddd ? ? bt/s label delayed branch; when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001101dddddddd ? ? bra label delayed branch, disp 2 + pc + 4 pc 1010dddddddddddd ? ? braf rn rn + pc + 4 pc 0000nnnn00100011 ? ? bsr label delayed branch, pc + 4 pr, disp 2 + pc + 4 pc 1011dddddddddddd ? ? bsrf rn delayed branch, pc + 4 pr, rn + pc + 4 pc 0000nnnn00000011 ? ? jmp @rn delayed branch, rn pc 0100nnnn00101011 ? ? jsr @rn delayed branch, pc + 4 pr, rn pc 0100nnnn00001011 ? ? rts delayed branch, pr pc 0000000000001011 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 203 of 1122 rej09b0370-0400 table 7.8 system control instructions instruction operation instruction code privileged t bit clrmac 0 mach, macl 0000000000101000 ? ? clrs 0 s 0000000001001000 ? ? clrt 0 t 0000000000001000 ? 0 ldc rm,sr rm sr 0100mmmm00001110 privileged lsb ldc rm,gbr rm gbr 0100mmmm00011110 ? ? ldc rm,vbr rm vbr 0100mmmm00101110 privileged ? ldc rm,ssr rm ssr 0100mmmm00111110 privileged ? ldc rm,spc rm spc 0100mmmm01001110 privileged ? ldc rm,dbr rm dbr 0100mmmm11111010 privileged ? ldc rm,rn_bank rm rn_bank (n = 0 to 7) 0100mmmm1nnn1110 privileged ? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 privileged lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 ? ? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 privileged ? ldc.l @rm+,ssr (rm) ssr, rm + 4 rm 0100mmmm00110111 privileged ? ldc.l @rm+,spc (rm) spc, rm + 4 rm 0100mmmm01000111 privileged ? ldc.l @rm+,dbr (rm) dbr, rm + 4 rm 0100mmmm11110110 privileged ? ldc.l @rm+,rn_bank (rm) rn_bank, rm + 4 rm 0100mmmm1nnn0111 privileged ? lds rm,mach rm mach 0100mmmm00001010 ? ? lds rm,macl rm macl 0100mmmm00011010 ? ? lds rm,pr rm pr 0100mmmm00101010 ? ? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 ? ? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 ? ? lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 ? ? ldtlb pteh/ptel tlb 0000000000111000 privileged ? movca.l r0,@rn r0 (rn) (without fetching cache block) 0000nnnn11000011 ? ? nop no operation 0000000000001001 ? ? ocbi @rn invalidates operand cache block 0000nnnn10010011 ? ? ocbp @rn writes back and invalidates operand cache block 0000nnnn10100011 ? ? ocbwb @rn writes back operand cache block 0000nnnn10110011 ? ? pref @rn (rn) operand cache 0000nnnn10000011 ? ? rte delayed branch, ssr/spc sr/pc 0000000000101011 privileged ?
7. instruction set rev.4.00 oct. 10, 2008 page 204 of 1122 rej09b0370-0400 instruction operation instruction code privileged t bit sets 1 s 0000000001011000 ? ? sett 1 t 0000000000011000 ? 1 sleep sleep or standby 0000000000011011 privileged ? stc sr,rn sr rn 0000nnnn00000010 privileged ? stc gbr,rn gbr rn 0000nnnn00010010 ? ? stc vbr,rn vbr rn 0000nnnn00100010 privileged ? stc ssr,rn ssr rn 0000nnnn00110010 privileged ? stc spc,rn spc rn 0000nnnn01000010 privileged ? stc sgr,rn sgr rn 0000nnnn00111010 privileged ? stc dbr,rn dbr rn 0000nnnn11111010 privileged ? stc rm_bank,rn rm_bank rn (m = 0 to 7) 0000nnnn1mmm0010 privileged ? stc.l sr,@-rn rn ? 4 rn, sr (rn) 0100nnnn00000011 privileged ? stc.l gbr,@-rn rn ? 4 rn, gbr (rn) 0100nnnn00010011 ? ? stc.l vbr,@-rn rn ? 4 rn, vbr (rn) 0100nnnn00100011 privileged ? stc.l ssr,@-rn rn ? 4 rn, ssr (rn) 0100nnnn00110011 privileged ? stc.l spc,@-rn rn ? 4 rn, spc (rn) 0100nnnn01000011 privileged ? stc.l sgr,@-rn rn ? 4 rn, sgr (rn) 0100nnnn00110010 privileged ? stc.l dbr,@-rn rn ? 4 rn, dbr (rn) 0100nnnn11110010 privileged ? stc.l rm_bank,@-rn rn ? 4 rn, rm_bank (rn) (m = 0 to 7) 0100nnnn1mmm0011 privileged ? sts mach,rn mach rn 0000nnnn00001010 ? ? sts macl,rn macl rn 0000nnnn00011010 ? ? sts pr,rn pr rn 0000nnnn00101010 ? ? sts.l mach,@-rn rn ? 4 rn, mach (rn) 0100nnnn00000010 ? ? sts.l macl,@-rn rn ? 4 rn, macl (rn) 0100nnnn00010010 ? ? sts.l pr,@-rn rn ? 4 rn, pr (rn) 0100nnnn00100010 ? ? trapa #imm pc + 2 spc, sr ssr, #imm << 2 tra, h'160 expevt, vbr + h'0100 pc 11000011iiiiiiii ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 205 of 1122 rej09b0370-0400 table 7.9 floating-point si ngle-precision instructions instruction operation instruction code privileged t bit fldi0 frn h'00000000 frn 1111nnnn10001101 ? ? fldi1 frn h'3f800000 frn 1111nnnn10011101 ? ? fmov frm,frn frm frn 1111nnnnmmmm1100 ? ? fmov.s @rm,frn (rm) frn 1111nnnnmmmm1000 ? ? fmov.s @(r0,rm),frn (r0 + rm) frn 1111nnnnmmmm0110 ? ? fmov.s @rm+,frn (rm) frn, rm + 4 rm 1111nnnnmmmm1001 ? ? fmov.s frm,@rn frm (rn) 1111nnnnmmmm1010 ? ? fmov.s frm,@-rn rn-4 rn, frm (rn) 1111nnnnmmmm1011 ? ? fmov.s frm,@(r0,rn) frm (r0 + rn) 1111nnnnmmmm0111 ? ? fmov drm,drn drm drn 1111nnn0mmm01100 ? ? fmov @rm,drn (rm) drn 1111nnn0mmmm1000 ? ? fmov @(r0,rm),drn (r0 + rm) drn 1111nnn0mmmm0110 ? ? fmov @rm+,drn (rm) drn, rm + 8 rm 1111nnn0mmmm1001 ? ? fmov drm,@rn drm (rn) 1111nnnnmmm01010 ? ? fmov drm,@-rn rn-8 rn, drm (rn) 1111nnnnmmm01011 ? ? fmov drm,@(r0,rn) drm (r0 + rn) 1111nnnnmmm00111 ? ? flds frm,fpul frm fpul 1111mmmm00011101 ? ? fsts fpul,frn fpul frn 1111nnnn00001101 ? ? fabs frn frn & h'7fff ffff frn 1111nnnn01011101 ? ? fadd frm,frn frn + frm frn 1111nnnnmmmm0000 ? ? fcmp/eq frm,frn when frn = frm, 1 t otherwise, 0 t 1111nnnnmmmm0100 ? comparison result fcmp/gt frm,frn when frn > frm, 1 t otherwise, 0 t 1111nnnnmmmm0101 ? comparison result fdiv frm,frn frn/frm frn 1111nnnnmmmm0011 ? ? float fpul,frn (float) fpul frn 1111nnnn00101101 ? ? fmac fr0,frm,frn fr0*frm + frn frn 1111nnnnmmmm1110 ? ? fmul frm,frn frn*frm frn 1111nnnnmmmm0010 ? ? fneg frn frn h'80000000 frn 1111nnnn01001101 ? ? fsqrt frn frn frn 1111nnnn01101101 ? ? fsub frm,frn frn ? frm frn 1111nnnnmmmm0001 ? ? ftrc frm,fpul (long) frm fpul 1111mmmm00111101 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 206 of 1122 rej09b0370-0400 table 7.10 floating-point do uble-precision instructions instruction operation instruction code privileged t bit fabs drn drn & h'7fff ffff ffff ffff drn 1111nnn001011101 ? ? fadd drm,drn drn + drm drn 1111nnn0mmm00000 ? ? fcmp/eq drm,drn when drn = drm, 1 t otherwise, 0 t 1111nnn0mmm00100 ? comparison result fcmp/gt drm,drn when drn > drm, 1 t otherwise, 0 t 1111nnn0mmm00101 ? comparison result fdiv drm,drn drn /drm drn 1111nnn0mmm00011 ? ? fcnvds drm,fpul double_to_ float[drm] fpul 1111mmm010111101 ? ? fcnvsd fpul,drn float_to_ double [fpul] drn 1111nnn010101101 ? ? float fpul,drn (float)fpul drn 1111nnn000101101 ? ? fmul drm,drn drn *drm drn 1111nnn0mmm00010 ? ? fneg drn drn ^ h'8000 0000 0000 0000 drn 1111nnn001001101 ? ? fsqrt drn drn drn 1111nnn001101101 ? ? fsub drm,drn drn ? drm drn 1111nnn0mmm00001 ? ? ftrc drm,fpul (long) drm fpul 1111mmm000111101 ? ? table 7.11 floating-point control instructions instruction operation instruction code privileged t bit lds rm,fpscr rm fpscr 0100mmmm01101010 ? ? lds rm,fpul rm fpul 0100mmmm01011010 ? ? lds.l @rm+,fpscr (rm) fpscr, rm+4 rm 0100mmmm01100110 ? ? lds.l @rm+,fpul (rm) fpul, rm+4 rm 0100mmmm01010110 ? ? sts fpscr,rn fpscr rn 0000nnnn01101010 ? ? sts fpul,rn fpul rn 0000nnnn01011010 ? ? sts.l fpscr,@-rn rn ? 4 rn, fpscr (rn) 0100nnnn01100010 ? ? sts.l fpul,@-rn rn ? 4 rn, fpul (rn) 0100nnnn01010010 ? ?
7. instruction set rev.4.00 oct. 10, 2008 page 207 of 1122 rej09b0370-0400 table 7.12 floating-point grap hics acceleration instructions instruction operation instruction code privileged t bit fmov drm,xdn drm xdn 1111nnn1mmm01100 ? ? fmov xdm,drn xdm drn 1111nnn0mmm11100 ? ? fmov xdm,xdn xdm xdn 1111nnn1mmm11100 ? ? fmov @rm,xdn (rm) xdn 1111nnn1mmmm1000 ? ? fmov @rm+,xdn (rm) xdn, rm + 8 rm 1111nnn1mmmm1001 ? ? fmov @(r0,rm),xdn (r0 + rm) xdn 1111nnn1mmmm0110 ? ? fmov xdm,@rn xdm (rn) 1111nnnnmmm11010 ? ? fmov xdm,@-rn rn ? 8 rn, xdm (rn) 1111nnnnmmm11011 ? ? fmov xdm,@(r0,rn) xdm (r0+rn) 1111nnnnmmm10111 ? ? fipr fvm,fvn inner_product [fvm, fvn] fr[n+3] 1111nnmm11101101 ? ? ftrv xmtrx,fvn transform_vector [xmtrx, fvn] fvn 1111nn0111111101 ? ? frchg ~fpscr.fr fpscr.fr 1111101111111101 ? ? fschg ~fpscr.sz fpscr.sz 1111001111111101 ? ? 7.4 usage notes 7.4.1 notes on trapa instruction, sleep instruction, and u ndefined instruction (h'fffd) ? incorrect data may be written to the cache when a trapa instruct ion or undefined instruction code h'fffd is executed. ? the itlb hit judgment may be incorrect when a trapa instruction or undefined instruction code h'fffd is executed, causing a multi-hit exception to occur after re-registration. ? incorrect data may be written to an fpu-related register or to the mach or macl register when a trapa instruction, sleep instruction, or undefined instruction code h'fffd is executed. conditions under which problem occurs 1. incorrect data may be writte n to the instruction cache when the following three conditions occur at the same time. a. the instruction cache is enabled (ccr.ice = 1).
7. instruction set rev.4.00 oct. 10, 2008 page 208 of 1122 rej09b0370-0400 b. a trapa instruction or undefined instruction code h'fffd in a cache-enabled area (u0, p0, p1, or p3 area) is executed. c. the four words of data following the tr apa instruction or undefined instruction code h'fffd mentioned in b. contai n code that can be interprete d as an instruction to access (read or write) an address (h'f0000000 to h'f7ffffff) mapped to the internal cache or internal tlb. 2. incorrect data may be writte n to the operand cache when the following three conditions occur at the same time. a. the operand cache is enabled (ccr.oce = 1). b. undefined instruction code h'fffd is executed. c. the four words of data following the undefined instruction code h'fffd mentioned in b. contain code that can be interpreted as an ocbi, ocbp, ocbwb, or tas.b instruction accessing an address (h'e0000000 to h'e3ffff ff) mapped to the internal store queue. 3. the itlb hit judgment may be incorrect when the following three conditions occur at the same time. if an itlb hit is erroneously judged to be a miss, itlb re-registration is performed. this can cause an i tlb multi-hit exception to occur. a. the mmu is enabled (mmucr.at = 1). b. a trapa instruction or undefined instruction code h'fffd in a tlb conversion area (u0, p0, or p3 area) is executed. c. the four words of data following the tr apa instruction or undefined instruction code h'fffd mentioned in b. contai n code that can be interprete d as an instruction to access (read or write) an address (h'f0000000 to h'f7ffffff) mapped to the internal cache or internal tlb. 4. incorrect data may be written to an fpu-rela ted register (fr0 to fr15, xf0 to xf15, fpscr, or fpul) or to the mach or macl register when the following two conditions occur at the same time. a. a trapa instruction, sleep instruction, or undefined instruction code h'fffd is executed b. the eight words of data following the trapa instruction, sleep instruction, or undefined instruction code h'fffd mentioned in a. contain h'fxxx (an instruction with h'f as the first four bits), excluding h'fffd, and the c ode can be interpreted, in combination with fpscr.pr at that point, as an undefined instruction. example: instruction h'fxxe (x: any hexadecimal digit) is defined here as undefined when fpscr.pr is set to 1. note: the number of instructions following the instructions mentioned above that may be affected by the problem is as follows: in the case of 1. to 3., the number of instructions that can be executed in 2xick, and in the case of 4., the number of instructions that can be executed in 4xick. the maximum nu mber of instructions that can be executed in 2xick or
7. instruction set rev.4.00 oct. 10, 2008 page 209 of 1122 rej09b0370-0400 4xick is four or eight, respectively. therefore, the affected codes are those occurring in ?the four words (or eight words) of data following the instruction.? workarounds 1. to prevent the problem, use either of workarounds a. or b. below. a. include a nop instruction in the eight words of data fo llowing each trap a instruction, sleep instruction, or undefi ned instruction code h'fffd. b. include an or r0,r0 in struction in the five words of data following each trapa instruction, sleep instruction, or undefine d instruction code h'fffd. this workaround also applies to cases where ?the eight words of data following the ? instruction ? contain h'fxxx,? as mentioned in condition 4. b., becau se two or instructions are never executed simultaneously, so a minimum of 5xick is required for execution.
7. instruction set rev.4.00 oct. 10, 2008 page 210 of 1122 rej09b0370-0400
8. pipelining rev.4.00 oct. 10, 2008 page 211 of 1122 rej09b0370-0400 section 8 pipelining this lsi is a 2-ilp (instruction-level-paralle lism) superscalar pipelining microprocessor. instruction execution is pipelined, and two instruc tions can be executed in parallel. the execution cycles depend on the implementation of a processor. definitions in this section may not be applicable to sh-4 core models other than this lsi. 8.1 pipelines figure 8.1 shows the basic pipelines. normally, a pipeline consists of five or six stages: instruction fetch (i), decode and register read (d), execution (ex/sx/f0/ f1/f2/f3), data access (na/ma), and write-back (s/fs). an instruction is executed as a combination of basic pipelines. figure 8.2 shows the instruction execution patterns.
8. pipelining rev.4.00 oct. 10, 2008 page 212 of 1122 rej09b0370-0400 1. general pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? destination address calculation for pc-relative branch ? non-memory data access ? write-back i d ex ? operation na s 2. general load/store pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? memory data access ? write-back i d ex ? address calculation ma s 3. special pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? non-memory data access ? write-back i d sx ? operation na s 4. special load/store pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? memory data access ? write-back i d sx ? address calculation ma s 5. floatin g -point pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? computation 2 ? computation 3 ? write-back i d f1 ? computation 1 f2 fs 6. floatin g -point extended pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? computation 1 ? computation 3 ? write-back i d f0 ? computation 0 f1 f2 fs ? computation 2 f3 computation: takes several cycles 7. fdiv/fsqrt pipeline figure 8.1 basic pipelines
8. pipelining rev.4.00 oct. 10, 2008 page 213 of 1122 rej09b0370-0400 1. 1-step operation: 1 issue cycle ext[su].[bw], mov, mov#, mova, movt, swap.[bw], xtrct, add * , cmp * , div * , dt, neg * , sub * , and, and#, not, or, or#, tst, tst#, xor, xor#, rot * , sha * , shl * , bf * , bt * , bra, nop, clrs, clrt, sets, sett, lds to fpul, sts from fpul/fpscr, fldi0, fldi1, fmov, flds, fsts, single-/double-precision fabs/fneg i d ex na s 2. load/store: 1 issue cycle mov.[bwl], fmov * @, lds.l to fpul, ldtlb, pref, sts.l from fpul/fpscr i d ex ma s 3. gbr-based load/store: 1 issue cycle mov.[bwl]@(d,gbr) i d sx ma s 4. jmp, rts, braf: 2 issue cycles i d ex na s d ex na s 5. tst.b: 3 issue cycles i d sx ma s d sx na s d sx na s 6. and.b, or.b, xor.b: 4 issue cycles i d sx ma s d sx na s d sx na s d sx ma s 7. tas.b: 5 issue cycles i d ex ma s d ex ma s d ex na s d ex na s d ex ma s 8. rte: 5 issue cycles i d ex na s d ex na s d ex na s d ex na s d ex na s 9. sleep: 4 issue cycles i d ex na s d ex na s d ex na s d ex na s figure 8.2 instruction execution patterns
8. pipelining rev.4.00 oct. 10, 2008 page 214 of 1122 rej09b0370-0400 10. ocbi: 1 issue cycle i d ex ma s ma 11. ocbp, ocbwb: 1 issue cycle i d ex ma s ma ma ma ma 12. movca.l: 1 issue cycle i d ex ma s ma ma ma ma ma ma 13. trapa: 7 issue cycles i d ex na s d ex na s d ex na s d ex na s d ex na s d ex na s d ex na s 14. ldc to dbr/rp_bank/ssr/spc/vbr, bsr: 1 issue cycle i d ex na s sx sx 15. ldc to gbr: 3 issue cycles i d ex na s d d sx sx 16. ldc to sr: 4 issue cycles i d ex na s d d d sx sx sx i d ex ma s 17. ldc.l to dbr/rp_bank/ssr/spc/vbr: 1 issue cycle sx sx 18. ldc.l to gbr: 3 issue cycles i d ex ma s d d sx sx figure 8.2 instruction execution patterns (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 215 of 1122 rej09b0370-0400 19. ldc.l to sr: 4 issue cycles i d ex ma s d d d sx sx sx 20. stc from dbr/gbr/rp_bank/sr/ssr/spc/vbr: 2 issue cycles i d sx na s d sx na s 21. stc.l from sgr: 3 issue cycles i d sx na s d sx na s d sx na s 22. stc.l from dbr/gbr/rp_bank/sr/ssr/spc/vbr: 2 issue cycles i d sx na s d sx ma s 23. stc.l from sgr: 3 issue cycles i d sx na s d sx na s d sx ma s 24. lds to pr, jsr, bsrf: 2 issue cycles i d ex na s d sx sx 25. lds.l to pr: 2 issue cycles i d ex ma s d sx sx 26. sts from pr: 2 issue cycles i d sx na s d sx na s 27. sts.l from pr: 2 issue cycles i d sx na s d sx ma s 28. clrmac, lds to mach/l: 1 issue cycle i d ex na s f1 f1 f2 fs 29. lds.l to mach/l: 1 issue cycle i d ex ma s f1 f1 f2 fs 30. sts from mach/l: 1 issue cycle i d ex na s figure 8.2 instruction execution patterns (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 216 of 1122 rej09b0370-0400 31. sts.l from mach/l: 1 issue cycle i d ex ma s 32. lds to fpscr: 1 issue cycle i d ex na s f1 f1 f1 f1 f1 f1 33. lds.l to fpscr: 1 issue cycle i d ex ma s 34. fixed-point multiplication: 2 issue cycles dmuls.l, dmulu.l, mul.l, muls.w, mulu.w i d ex na s (cpu) d ex na s f1 (fpu) f1 f1 f1 f2 fs 35. mac.w, mac.l: 2 issue cycles i d ex ma s (cpu) d ex ma s f1 (fpu) f1 f1 f1 f2 fs 36. sin g le-precision floatin g -point computation: 1 issue cycle fcmp/eq,fcmp/gt, fadd,float,fmac,fmul,fsub,ftrc,frchg,fschg i d f1 f2 fs 37. sin g le-precision fdiv/sqrt: 1 issue cycle i d f1 f2 fs f3 f1 f2 fs 38. double-precision floatin g -point computation 1: 1 issue cycle fcnvds, fcnvsd, float, ftrc i d f1 f2 fs d f1 f2 fs 39. double-precision floatin g -point computation 2: 1 issue cycle fadd, fmul, fsub i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs figure 8.2 instruction execution patterns (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 217 of 1122 rej09b0370-0400 i d f1 f2 fs d f1 f2 fs 40. double-precision fcmp: 2 issue cycles fcmp/eq,fcmp/gt i d f1 f2 fs f3 f1 f2 fs 41. double-precision fdiv/sqrt: 1 issue cycle fdiv, fsqrt f1 f2 d f1 f2 fs f1 f2 fs 42. fipr: 1 issue cycle i d f0 f1 f2 fs 43. ftrv: 1 issue cycle f1 f2 fs d f0 i f1 f2 fs d f0 f1 f2 fs d f0 f1 f2 fs d f0 notes: ?? : locks d-sta g e : re g ister read only : locks, but no operation is executed. : can overlap another f1, but not another f1. d d ?? f1 : cannot overlap a sta g e of the same kind, except when two instructions are executed in parallel. figure 8.2 instruction execution patterns (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 218 of 1122 rej09b0370-0400 8.2 parallel-executability instructions are categorized into six groups according to the inte rnal function bl ocks used, as shown in table 8.1. table 8.2 shows the parallel-ex ecutability of pairs of instructions in terms of groups. for example, add in the ex group and bra in the br group can be executed in parallel. table 8.1 instruction groups 1. mt group clrt cmp/hi rm,rn mov rm,rn cmp/eq #imm,r0 cmp/hs rm,rn nop cmp/eq rm,rn cmp/pl rn sett cmp/ge rm,rn cmp/pz rn tst #imm,r0 cmp/gt rm,rn cmp/str rm,rn tst rm,rn 2. ex group add #imm,rn movt rn shll2 rn add rm,rn neg rm,rn shll8 rn addc rm,rn negc rm,rn shlr rn addv rm,rn not rm,rn shlr16 rn and #imm,r0 or #imm,r0 shlr2 rn and rm,rn or rm,rn shlr8 rn div0s rm,rn rotcl rn sub rm,rn div0u rotcr rn subc rm,rn div1 rm,rn rotl rn subv rm,rn dt rn rotr rn swap.b rm,rn exts.b rm,rn shad rm,rn swap.w rm,rn exts.w rm,rn shal rn xor #imm,r0 extu.b rm,rn shar rn xor rm,rn extu.w rm,rn shld rm,rn xtrct rm,rn mov #imm,rn shll rn mova @(disp,pc),r0 shll16 rn
8. pipelining rev.4.00 oct. 10, 2008 page 219 of 1122 rej09b0370-0400 3. br group bf disp bra disp bt disp bf/s disp bsr disp bt/s disp 4. ls group fabs drn fmov.s @rm+,frn mov.l r0,@(disp,gbr) fabs frn fmov.s frm,@(r0,rn) mov.l rm,@(disp,rn) fldi0 frn fmov.s frm,@-rn mov.l rm,@(r0,rn) fldi1 frn fmov.s frm,@rn mov.l rm,@-rn flds frm,fpul fneg drn mov.l rm,@rn fmov @(r0,rm),drn fneg frn mov.w @(disp,gbr),r0 fmov @(r0,rm),xdn fsts fpul,frn mov.w @(disp,pc),rn fmov @rm,drn lds rm,fpul mov.w @(disp,rm),r0 fmov @rm,xdn mov.b @(disp,gbr),r0 mov.w @(r0,rm),rn fmov @rm+,drn mov.b @(disp,rm),r0 mov.w @rm,rn fmov @rm+,xdn mov.b @(r0,rm),rn mov.w @rm+,rn fmov drm,@(r0,rn) mov.b @rm,rn mov.w r0,@(disp,gbr) fmov drm,@-rn mov.b @rm+,rn mov.w r0,@(disp,rn) fmov drm,@rn mov.b r0,@(disp,gbr) mov.w rm,@(r0,rn) fmov drm,drn mov.b r0,@(disp,rn) mov.w rm,@-rn fmov drm,xdn mov.b rm,@(r0,rn) mov.w rm,@rn fmov frm,frn mov.b rm,@-rn movca.l r0,@rn fmov xdm,@(r0,rn) mov.b rm,@rn ocbi @rn fmov xdm,@-rn mov.l @(disp,gbr),r0 ocbp @rn fmov xdm,@rn mov.l @(disp,pc),rn ocbwb @rn fmov xdm,drn mov.l @(disp,rm),rn pref @rn fmov xdm,xdn mov.l @(r0,rm),rn sts fpul,rn fmov.s @(r0,rm),frn mov.l @rm,rn fmov.s @rm,frn mov.l @rm+,rn
8. pipelining rev.4.00 oct. 10, 2008 page 220 of 1122 rej09b0370-0400 5. fe group fadd drm,drn fipr fvm,fvn fsqrt drn fadd frm,frn float fpul,drn fsqrt frn fcmp/eq frm,frn float fpul,frn fsub drm,drn fcmp/gt frm,frn fmac fr0,frm,frn fsub frm,frn fcnvds drm,fpul fmul drm,drn ftrc drm,fpul fcnvsd fpul,drn fmul frm,frn ftrc frm,fpul fdiv drm,drn frchg ftrv xmtrx,fvn fdiv frm,frn fschg
8. pipelining rev.4.00 oct. 10, 2008 page 221 of 1122 rej09b0370-0400 6. co group and.b #imm,@(r0,gbr) lds rm,fpscr stc sr,rn braf rm lds rm,mach stc ssr,rn bsrf rm lds rm,macl stc vbr,rn clrmac lds rm,pr stc.l dbr,@-rn clrs lds.l @rm+,fpscr stc.l gbr,@-rn dmuls.l rm,rn lds.l @rm+,f pul stc.l rp_bank,@-rn dmulu.l rm,rn lds.l @rm+ ,mach stc.l sgr,@-rn fcmp/eq drm,drn lds.l @rm+,macl stc.l spc,@-rn fcmp/gt drm,drn lds.l @rm+,pr stc.l sr,@-rn jmp @rn ldtlb stc.l ssr,@-rn jsr @rn mac.l @rm+,@rn+ stc.l vbr,@-rn ldc rm,dbr mac.w @rm+,@rn+ sts fpscr,rn ldc rm,gbr mul.l rm,rn sts mach,rn ldc rm,rp_bank muls.w rm,rn sts macl,rn ldc rm,spc mulu.w rm,rn sts pr,rn ldc rm,sr or.b #imm,@(r0,gbr) sts.l fpscr,@-rn ldc rm,ssr rte sts.l fpul,@-rn ldc rm,vbr rts sts.l mach,@-rn ldc.l @rm+,dbr sets sts.l macl,@-rn ldc.l @rm+,gbr sleep sts.l pr,@-rn ldc.l @rm+,rp_bank stc dbr,rn tas.b @rn ldc.l @rm+,spc stc gbr,rn trapa #imm ldc.l @rm+,sr stc rp_bank,rn tst.b #imm,@(r0,gbr) ldc.l @rm+,ssr stc sgr, rn xor.b #imm,@(r0,gbr) ldc.l @rm+,vbr stc spc,rn
8. pipelining rev.4.00 oct. 10, 2008 page 222 of 1122 rej09b0370-0400 table 8.2 parallel-executability 2nd instruction mt ex br ls fe co mt o o o o o x ex o x o o o x br o o x o o x ls o o o x o x fe o o o o x x 1st instruction co x x x x x x legend: o: can be executed in parallel x: cannot be executed in parallel 8.3 execution cycles and pipeline stalling there are three basic clocks in th is processor: the i-clock, b-clock, and p-clock. each hardware unit operates on one of these clocks, as follows: ? i-clock: cpu, fpu, mmu, caches ? b-clock: external bus controller ? p-clock: peripheral units the frequency ratios of the three clocks are de termined with the frequency control register (frqcr). in this section, machine cycles are ba sed on the i-clock unless otherwise specified. for details of frqcr, see section 10, clock oscillation circuits. instruction execution cycles are su mmarized in table 8.3. penalty cy cles due to a pipeline stall or freeze are not considered in this table. ? issue rate: interval between the issue of an instruction and that of the next instruction ? latency: interval between the issue of an instruction and the generation of its result (completion) ? instruction execution pattern (see figure 8.2) ? lock stage: locked pipeli ne stages(see table 8.3) ? lock start: interval between the issue of an instruction and the start of locking (see table 8.3) ? lock cycle: lock time (see table 8.3)
8. pipelining rev.4.00 oct. 10, 2008 page 223 of 1122 rej09b0370-0400 the instruction exec ution sequence is expressed as a comb ination of the execution patterns shown in figure 8.2. one instruction is separated from the next by the number of machine cycles for its issue rate. normally, execution, data access, and wr ite-back stages cannot be overlapped onto the same stages of another instruction; the only exception is when two instructions are executed in parallel under parallel-executability conditions. refer to (a) through (d) in figure 8.3 for some simple examples. latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. when there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles: ? (latency) cycles when there is fl ow dependency (read-after-write) ? (latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write) ? single/double-precision fdiv, fsqrt is the pr eceding instruction (latency ? 1) cycles ? the other fe group except above is the prec eding instruction (latency ? 2) cycles ? 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases: ? ftrv is the preceding in struction (5 cycles) ? a double-precision fa dd, fsub, or fmul is the pr eceding instruction (2 cycles) in the case of flow dependency, latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 8.3 (e)). ? when a floating-point computation is followed by a floating-point register store, the latency of the floating-point computation may be decreased by 1 cycle. ? if there is a load of the shift amount immedi ately before an shad/shld instruction, the latency of the load is increased by 1 cycle. ? if an instruction with a latency of less than 2 cycles, including write-back to a floating-point register, is followed by a double-precision floating-point instruction, fipr, or ftrv, the latency of the first instructio n is increased to 2 cycles. the number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 8.3. (e)). output dependency occurs when the destination operands are the same in a preceding fe group instruction and a following ls group instruction. for the stall cycles of an instruction with output dependency, the longest latency to the last write- back among all the destination operands must be applied instead of ?laten cy? (see figure 8.3 (f)). a stall due to output dependency with respect to fpscr, which reflects the result of a floating- point operation, never occurs. for example, when fadd follows fdiv with no dependency
8. pipelining rev.4.00 oct. 10, 2008 page 224 of 1122 rej09b0370-0400 between floating-point registers, fadd is not stalled even if both instructions update the cause field of fpscr. anti-flow dependency can occur only betwee n a preceding double-pr ecision fadd, fmul, fsub, or ftrv and a following fmov, fldi0, fldi1, fabs, fneg, or fsts. see figure 8.3 (g). if an executing instruction locks any resource?i.e. a function block that performs a basic operation?a following instruction that attempts to use the locked resource is stalled (figure 8.3 (h)). this kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate the interfering instructions. for ex ample, when a load instruction and an add instruction that refere nces the loaded value are consec utive, the 2-cycle stall of the add is eliminated by inserting three instructions without dependency. software performance can be improved by such instruction scheduling. other causes of a stall are as follows. ? instruction tlb miss ? instruction access to external me mory (instruction cache miss, etc.) ? data access to external memory (operand cach e miss, etc.) ? data access to a memory-mapped control register during the penalty cycles of an instruction tlb miss or external instruct ion access, no instruction is issued, but execution of instructions that have already been issued continues. the penalty for a data access is a pipeline freeze: that is, the execu tion of uncompleted instru ctions is interrupted until the arrival of the requested data. the number of penalty cycles for instruction and data accesses is largely dependent on the user's memory subsystems.
8. pipelining rev.4.00 oct. 10, 2008 page 225 of 1122 rej09b0370-0400 (a) serial execution: non-parallel-executable instructions add r2,r1 mov.l @r4,r5 mov r1,r2 next shad r0,r1 add r2,r3 next i d ex na s i d ex na s id ... 1 stall cycle (b) parallel execution: parallel-executable and no dependency i d ex na s i d ex ma s (c) issue rate: multi-step instruction and.b#1,@(r0,gbr) i d sx ma s d sx ma s d sx na s d sx na s i i (d) branch 1 issue cycle 1 issue cycle 4 issue cycles ... i d ex na s i d ex na s 2-cycle latency for i-sta g e of branch destination 1 stall cycle i d i d ex na s i d ex na s i d ex na s bt/s l_far add r0,r1 sub r2,r3 bt/s l_far add r0,r1 l_far i d ex na s i d i d ? ?? ... no stall bt l_skip add #1,r0 l_skip: ... i d e a s 4 stall cycles ex- g roup shad and ex- g roup add cannot be executed in parallel. therefore, shad is issued first, and the followin g add is recombined with the next instruction. ex- g roup add and ls- g roup mov.l can be executed in parallel. overlappin g of sta g es in the 2nd instruction is possible. and.b and mov are fetched simultaneously, but mov is stalled due to resource lockin g . after the lock is released, mov is refetched to g ether with the next instruction. no stall occurs if the branch is not taken. if the branch is taken, the i-sta g e of the branch destination is stalled for the period of latency. this stall can be covered with a delay slot instruction which is not parallel- executable with the branch instruction. even if the bt/bf branch is taken, the i- sta g e of the branch destination is not stalled if the displacement is zero. figure 8.3 examples of pipelined execution
8. pipelining rev.4.00 oct. 10, 2008 page 226 of 1122 rej09b0370-0400 (e) flow dependency i d ex na s i d ex na s mov r0,r1 add r2,r1 add r2,r1 mov.l @r1,r1 next i d ex na s i d ex ma s i i ... ... ... zero-cycle latency 1-cycle latency 1 stall cycle mov.l @r1,r1 add r0,r1 next i d ex ma s i d i ex na s d ex na s 2-cycle latency 1 stall cycle mov.l @r1,r1 shad r1,r2 next fadd fr1,fr2 sts fpul,r1 sts fpscr,r2 i d ex na s i 4-cycle latency for fpscr 2 stall cycles i d f1 f2 fs i d ex ma s i d i 2-cycle latency 2 stall cycles ex na s d 1-cycle increase i i i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs d f1 f2 fs ex na s d ex na s d fadd dr0,dr2 7-cycle latency for lower fr 8-cycle latency for upper fr fmov fr3,fr5 fmov fr2,fr4 float fpul,dr0 fmov.s fr0,@-r15 fr3 write fr2 write i d f1 f2 fs d f1 f2 fs i d ex ma s 3-cycle latency for upper/lower fr fr1 write fr0 write fldi1 fr3 fipr fv0,fv4 fmov @r1,xd14 ftrv xmtrx,fv0 i d ex na s i d d f0 f1 f2 fs zero-cycle latency 3-cycle increase 3 stall cycles i d ex ma s i d d f0 f1 f2 fs d f0 f1 fs f2 d f0 f2 f1 fs d f1 f0 f2 fs 2-cycle latency 1-cycle increase 3 stall cycles the followin g instruction, add, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. add and mov.l are not executed in parallel, since mov.l references the result of add as its destination address. because mov.l and add are not fetched simultaneously in this example, add is stalled for only 1 cycle even thou g h the latency of mov.l is 2 cycles. due to the flow dependency between the load and the shad/shld shift amount, the latency of the load is increased to 3 cycles. figure 8.3 examples of pipelined execution (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 227 of 1122 rej09b0370-0400 i d ex na s i d ex na s d f1 f2 fs d f1 f2 fs (e) flow dependency (cont) i i lds r0,fpul float fpul,fr0 lds r1,fpul float fpul,fr1 effectively 1-cycle latency for consecutive lds/float instructions i d ex na s d f1 f2 fs i d f1 f2 fs i i d ex na s effectively 1-cycle latency for consecutive ftrc/sts instructions ftrc fr0,fpul sts fpul,r0 ftrc fr1,fpul sts fpul,r1 (f) output dependency d f1 f2 fs i i d f1 f2 fs f1 f2 fs 11-cycle latency 10 stall cycles = latency (11) - 1 the re g isters are written-back in pro g ram order. d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs ex na s i d 7-cycle latency for lower fr 8-cycle latency for upper fr 6 stall cycles = lon g est latency (8) - 2 fr2 write fr3 write d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f0 f0 f0 f0 f2 fs ( g ) anti-flow dependency ex ma s i d 5 stall cycles d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f2 fs ex na s i d 2 stall cycles d f1 f2 fs f1 f2 fs fsqrt fr4 fmov fr0,fr4 fadd dr0,dr2 fmov fr0,fr3 ftrv xmtrx,fv0 fmov @r1,xd0 fadd dr0,dr2 fmov fr4,fr1 f3 figure 8.3 examples of pipelined execution (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 228 of 1122 rej09b0370-0400 (h) resource conflict f1 sta g e locked for 1 cycle latency 1 cycle/issue 1 stall cycle (f1 sta g e resource conflict) fdiv fr6,fr7 fmac fr0,fr8,fr9 fmac fr0,fr10,fr11 fmac fr0,fr12,fr13 fipr fv8,fv0 fadd fr15,fr4 i d f1 f0 f2 fs i d f1 f2 fs 1 stall cycle lds.l @r15+,pr i d ex ma fs dsx sx sx na s sx na s d i 3 stall cycles stc gbr,r2 fadd dr0,dr2 i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs ex ma s f1 ex ma s d f1 f1 f2 fs f1 f2 fs i d 5 stall cycles mac.w @r1+,@r2+ i d ex ma s f1 f1 f1 f2 fs f1 f2 fs i f1 d ex ma s f1 d ex ma s f1 f2 fs f1 f2 fs f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 ... i d 3 stall cycles 1 stall cycle 2 stall cycles mac.w @r1+,@r2+ mac.w @r1+,@r2+ fadd dr4,dr6 f1 sta g e can overlap precedin g f1, but f1 cannot overlap f1. d ex ma s d i d f1 f2 fs i d f1 f2 fs f1 f2 fs f1 f2 i dfs f3 i d f1 f2 fs #1 #2 #3 .................................................. #10 #11 #8 #9 #12 ... : figure 8.3 examples of pipelined execution (cont)
8. pipelining rev.4.00 oct. 10, 2008 page 229 of 1122 rej09b0370-0400 table 8.3 execution cycles lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 1 exts.b rm,rn ex 1 1 #1 ? ? ? 2 exts.w rm,rn ex 1 1 #1 ? ? ? 3 extu.b rm,rn ex 1 1 #1 ? ? ? 4 extu.w rm,rn ex 1 1 #1 ? ? ? 5 mov rm,rn mt 1 0 #1 ? ? ? 6 mov #imm,rn ex 1 1 #1 ? ? ? 7 mova @(disp,pc),r0 ex 1 1 #1 ? ? ? 8 mov.w @(disp,pc),rn ls 1 2 #2 ? ? ? 9 mov.l @(disp,pc),rn ls 1 2 #2 ? ? ? 10 mov.b @rm,rn ls 1 2 #2 ? ? ? 11 mov.w @rm,rn ls 1 2 #2 ? ? ? 12 mov.l @rm,rn ls 1 2 #2 ? ? ? 13 mov.b @rm+,rn ls 1 1/2 #2 ? ? ? 14 mov.w @rm+,rn ls 1 1/2 #2 ? ? ? 15 mov.l @rm+,rn ls 1 1/2 #2 ? ? ? 16 mov.b @(disp,rm),r0 ls 1 2 #2 ? ? ? 17 mov.w @(disp,rm),r0 ls 1 2 #2 ? ? ? 18 mov.l @(disp,rm),rn ls 1 2 #2 ? ? ? 19 mov.b @(r0,rm),rn ls 1 2 #2 ? ? ? 20 mov.w @(r0,rm),rn ls 1 2 #2 ? ? ? 21 mov.l @(r0,rm),rn ls 1 2 #2 ? ? ? 22 mov.b @(disp,gbr),r0 ls 1 2 #3 ? ? ? 23 mov.w @(disp,gbr),r0 ls 1 2 #3 ? ? ? 24 mov.l @(disp,gbr),r0 ls 1 2 #3 ? ? ? 25 mov.b rm,@rn ls 1 1 #2 ? ? ? 26 mov.w rm,@rn ls 1 1 #2 ? ? ? 27 mov.l rm,@rn ls 1 1 #2 ? ? ? 28 mov.b rm,@-rn ls 1 1/1 #2 ? ? ? 29 mov.w rm,@-rn ls 1 1/1 #2 ? ? ? 30 mov.l rm,@-rn ls 1 1/1 #2 ? ? ? data transfer instructions 31 mov.b r0,@(disp,rn) ls 1 1 #2 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 230 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 32 mov.w r0,@(disp,rn) ls 1 1 #2 ? ? ? 33 mov.l rm,@(disp,rn) ls 1 1 #2 ? ? ? 34 mov.b rm,@(r0,rn) ls 1 1 #2 ? ? ? 35 mov.w rm,@(r0,rn) ls 1 1 #2 ? ? ? 36 mov.l rm,@(r0,rn) ls 1 1 #2 ? ? ? 37 mov.b r0,@(disp,gbr) ls 1 1 #3 ? ? ? 38 mov.w r0,@(disp,gbr) ls 1 1 #3 ? ? ? 39 mov.l r0,@(disp,gbr) ls 1 1 #3 ? ? ? 40 movca.l r0,@rn ls 1 3?7 #12 ma 4 3?7 41 movt rn ex 1 1 #1 ? ? ? 42 ocbi @rn ls 1 1?2 #10 ma 4 1?2 43 ocbp @rn ls 1 1?5 #11 ma 4 1?5 44 ocbwb @rn ls 1 1?5 #11 ma 4 1?5 45 pref @rn ls 1 1 #2 ? ? ? 46 swap.b rm,rn ex 1 1 #1 ? ? ? 47 swap.w rm,rn ex 1 1 #1 ? ? ? data transfer instructions 48 xtrct rm,rn ex 1 1 #1 ? ? ? 49 add rm,rn ex 1 1 #1 ? ? ? 50 add #imm,rn ex 1 1 #1 ? ? ? 51 addc rm,rn ex 1 1 #1 ? ? ? 52 addv rm,rn ex 1 1 #1 ? ? ? 53 cmp/eq #imm,r0 mt 1 1 #1 ? ? ? 54 cmp/eq rm,rn mt 1 1 #1 ? ? ? 55 cmp/ge rm,rn mt 1 1 #1 ? ? ? 56 cmp/gt rm,rn mt 1 1 #1 ? ? ? 57 cmp/hi rm,rn mt 1 1 #1 ? ? ? 58 cmp/hs rm,rn mt 1 1 #1 ? ? ? 59 cmp/pl rn mt 1 1 #1 ? ? ? 60 cmp/pz rn mt 1 1 #1 ? ? ? 61 cmp/str rm,rn mt 1 1 #1 ? ? ? fixed-point arithmetic instructions 62 div0s rm,rn ex 1 1 #1 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 231 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 63 div0u ex 1 1 #1 ? ? ? 64 div1 rm,rn ex 1 1 #1 ? ? ? 65 dmuls.l rm,rn co 2 4/4 #34 f1 4 2 66 dmulu.l rm,rn co 2 4/4 #34 f1 4 2 67 dt rn ex 1 1 #1 ? ? ? 68 mac.l @rm+,@rn+ co 2 2/2/4/4 #35 f1 4 2 69 mac.w @rm+,@rn+ co 2 2/2/4/4 #35 f1 4 2 70 mul.l rm,rn co 2 4/4 #34 f1 4 2 71 muls.w rm,rn co 2 4/4 #34 f1 4 2 72 mulu.w rm,rn co 2 4/4 #34 f1 4 2 73 neg rm,rn ex 1 1 #1 ? ? ? 74 negc rm,rn ex 1 1 #1 ? ? ? 75 sub rm,rn ex 1 1 #1 ? ? ? 76 subc rm,rn ex 1 1 #1 ? ? ? fixed-point arithmetic instructions 77 subv rm,rn ex 1 1 #1 ? ? ? 78 and rm,rn ex 1 1 #1 ? ? ? 79 and #imm,r0 ex 1 1 #1 ? ? ? 80 and.b #imm,@(r0,gbr) co 4 4 #6 ? ? ? 81 not rm,rn ex 1 1 #1 ? ? ? 82 or rm,rn ex 1 1 #1 ? ? ? 83 or #imm,r0 ex 1 1 #1 ? ? ? 84 or.b #imm,@(r0,gbr) co 4 4 #6 ? ? ? 85 tas.b @rn co 5 5 #7 ? ? ? 86 tst rm,rn mt 1 1 #1 ? ? ? 87 tst #imm,r0 mt 1 1 #1 ? ? ? 88 tst.b #imm,@(r0,gbr) co 3 3 #5 ? ? ? 89 xor rm,rn ex 1 1 #1 ? ? ? 90 xor #imm,r0 ex 1 1 #1 ? ? ? logical instructions 91 xor.b #imm,@(r0,gbr) co 4 4 #6 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 232 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 92 rotl rn ex 1 1 #1 ? ? ? 93 rotr rn ex 1 1 #1 ? ? ? 94 rotcl rn ex 1 1 #1 ? ? ? 95 rotcr rn ex 1 1 #1 ? ? ? 96 shad rm,rn ex 1 1 #1 ? ? ? 97 shal rn ex 1 1 #1 ? ? ? 98 shar rn ex 1 1 #1 ? ? ? 99 shld rm,rn ex 1 1 #1 ? ? ? 100 shll rn ex 1 1 #1 ? ? ? 101 shll2 rn ex 1 1 #1 ? ? ? 102 shll8 rn ex 1 1 #1 ? ? ? 103 shll16 rn ex 1 1 #1 ? ? ? 104 shlr rn ex 1 1 #1 ? ? ? 105 shlr2 rn ex 1 1 #1 ? ? ? 106 shlr8 rn ex 1 1 #1 ? ? ? shift instructions 107 shlr16 rn ex 1 1 #1 ? ? ? 108 bf disp br 1 2 (or 1) #1 ? ? ? 109 bf/s disp br 1 2 (or 1) #1 ? ? ? 110 bt disp br 1 2 (or 1) #1 ? ? ? 111 bt/s disp br 1 2 (or 1) #1 ? ? ? 112 bra disp br 1 2 #1 ? ? ? 113 braf rn co 2 3 #4 ? ? ? 114 bsr disp br 1 2 #14 sx 3 2 115 bsrf rn co 2 3 #24 sx 3 2 116 jmp @rn co 2 3 #4 ? ? ? 117 jsr @rn co 2 3 #24 sx 3 2 branch instructions 118 rts co 2 3 #4 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 233 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 119 nop mt 1 0 #1 ? ? ? 120 clrmac co 1 3 #28 f1 3 2 121 clrs co 1 1 #1 ? ? ? 122 clrt mt 1 1 #1 ? ? ? 123 sets co 1 1 #1 ? ? ? 124 sett mt 1 1 #1 ? ? ? 125 trapa #imm co 7 7 #13 ? ? ? 126 rte co 5 5 #8 ? ? ? 127 sleep co 4 4 #9 ? ? ? 128 ldtlb co 1 1 #2 ? ? ? 129 ldc rm,dbr co 1 3 #14 sx 3 2 130 ldc rm,gbr co 3 3 #15 sx 3 2 131 ldc rm,rp_bank co 1 3 #14 sx 3 2 132 ldc rm,sr co 4 4 #16 sx 3 2 133 ldc rm,ssr co 1 3 #14 sx 3 2 134 ldc rm,spc co 1 3 #14 sx 3 2 135 ldc rm,vbr co 1 3 #14 sx 3 2 136 ldc.l @rm+,dbr co 1 1/3 #17 sx 3 2 137 ldc.l @rm+,gbr co 3 3/3 #18 sx 3 2 138 ldc.l @rm+,rp_bank co 1 1/3 #17 sx 3 2 139 ldc.l @rm+,sr co 4 4/4 #19 sx 3 2 140 ldc.l @rm+,ssr co 1 1/3 #17 sx 3 2 141 ldc.l @rm+,spc co 1 1/3 #17 sx 3 2 142 ldc.l @rm+,vbr co 1 1/3 #17 sx 3 2 143 lds rm,mach co 1 3 #28 f1 3 2 144 lds rm,macl co 1 3 #28 f1 3 2 145 lds rm,pr co 2 3 #24 sx 3 2 146 lds.l @rm+,mach co 1 1/3 #29 f1 3 2 147 lds.l @rm+,macl co 1 1/3 #29 f1 3 2 148 lds.l @rm+,pr co 2 2/3 #25 sx 3 2 149 stc dbr,rn co 2 2 #20 ? ? ? system control instructions 150 stc sgr,rn co 3 3 #21 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 234 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 151 stc gbr,rn co 2 2 #20 ? ? ? 152 stc rp_bank,rn co 2 2 #20 ? ? ? 153 stc sr,rn co 2 2 #20 ? ? ? 154 stc ssr,rn co 2 2 #20 ? ? ? 155 stc spc,rn co 2 2 #20 ? ? ? 156 stc vbr,rn co 2 2 #20 ? ? ? 157 stc.l dbr,@-rn co 2 2/2 #22 ? ? ? 158 stc.l sgr,@-rn co 3 3/3 #23 ? ? ? 159 stc.l gbr,@-rn co 2 2/2 #22 ? ? ? 160 stc.l rp_bank,@-rn co 2 2/2 #22 ? ? ? 161 stc.l sr,@-rn co 2 2/2 #22 ? ? ? 162 stc.l ssr,@-rn co 2 2/2 #22 ? ? ? 163 stc.l spc,@-rn co 2 2/2 #22 ? ? ? 164 stc.l vbr,@-rn co 2 2/2 #22 ? ? ? 165 sts mach,rn co 1 3 #30 ? ? ? 166 sts macl,rn co 1 3 #30 ? ? ? 167 sts pr,rn co 2 2 #26 ? ? ? 168 sts.l mach,@-rn co 1 1/1 #31 ? ? ? 169 sts.l macl,@-rn co 1 1/1 #31 ? ? ? system control instructions 170 sts.l pr,@-rn co 2 2/2 #27 ? ? ? 171 fldi0 frn ls 1 0 #1 ? ? ? 172 fldi1 frn ls 1 0 #1 ? ? ? 173 fmov frm,frn ls 1 0 #1 ? ? ? 174 fmov.s @rm,frn ls 1 2 #2 ? ? ? 175 fmov.s @rm+,frn ls 1 1/2 #2 ? ? ? 176 fmov.s @(r0,rm),frn ls 1 2 #2 ? ? ? 177 fmov.s frm,@rn ls 1 1 #2 ? ? ? 178 fmov.s frm,@-rn ls 1 1/1 #2 ? ? ? 179 fmov.s frm,@(r0,rn) ls 1 1 #2 ? ? ? 180 flds frm,fpul ls 1 0 #1 ? ? ? single- precision floating-point instructions 181 fsts fpul,frn ls 1 0 #1 ? ? ?
8. pipelining rev.4.00 oct. 10, 2008 page 235 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 182 fabs frn ls 1 0 #1 ? ? ? 183 fadd frm,frn fe 1 3/4 #36 ? ? ? 184 fcmp/eq frm,frn fe 1 2/4 #36 ? ? ? 185 fcmp/gt frm,frn fe 1 2/4 #36 ? ? ? 186 fdiv frm,frn fe 1 12/13 #37 f3 2 10 f1 11 1 187 float fpul,frn fe 1 3/4 #36 ? ? ? 188 fmac fr0,frm,frn fe 1 3/4 #36 ? ? ? 189 fmul frm,frn fe 1 3/4 #36 ? ? ? 190 fneg frn ls 1 0 #1 ? ? ? 191 fsqrt frn fe 1 11/12 #37 f3 2 9 f1 10 1 192 fsub frm,frn fe 1 3/4 #36 ? ? ? 193 ftrc frm,fpul fe 1 3/4 #36 ? ? ? 194 fmov drm,drn ls 1 0 #1 ? ? ? 195 fmov @rm,drn ls 1 2 #2 ? ? ? 196 fmov @rm+,drn ls 1 1/2 #2 ? ? ? 197 fmov @(r0,rm),drn ls 1 2 #2 ? ? ? 198 fmov drm,@rn ls 1 1 #2 ? ? ? 199 fmov drm,@-rn ls 1 1/1 #2 ? ? ? single- precision floating-point instructions 200 fmov drm,@(r0,rn) ls 1 1 #2 ? ? ? 201 fabs drn ls 1 0 #1 ? ? ? 202 fadd drm,drn fe 1 (7, 8)/9 #39 f1 2 6 203 fcmp/eq drm,drn co 2 3/5 #40 f1 2 2 204 fcmp/gt drm,drn co 2 3/5 #40 f1 2 2 205 fcnvds drm,fpul fe 1 4/5 #38 f1 2 2 206 fcnvsd fpul,drn fe 1 (3, 4)/5 #38 f1 2 2 f3 2 23 f1 22 3 207 fdiv drm,drn fe 1 (24, 25)/ 26 #41 f1 2 2 208 float fpul,drn fe 1 (3, 4)/5 #38 f1 2 2 double- precision floating-point instructions 209 fmul drm,drn fe 1 (7, 8)/9 #39 f1 2 6
8. pipelining rev.4.00 oct. 10, 2008 page 236 of 1122 rej09b0370-0400 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 210 fneg drn ls 1 0 #1 ? ? ? f3 2 22 f1 21 3 211 fsqrt drn fe 1 (23, 24)/ 25 #41 f1 2 2 212 fsub drm,drn fe 1 (7, 8)/9 #39 f1 2 6 double- precision floating-point instructions 213 ftrc drm,fpul fe 1 4/5 #38 f1 2 2 214 lds rm,fpul ls 1 1 #1 ? ? ? 215 lds rm,fpscr co 1 4 #32 f1 3 3 216 lds.l @rm+,fpul co 1 1/2 #2 ? ? ? 217 lds.l @rm+,fpscr co 1 1/4 #33 f1 3 3 218 sts fpul,rn ls 1 3 #1 ? ? ? 219 sts fpscr,rn co 1 3 #1 ? ? ? 220 sts.l fpul,@-rn co 1 1/1 #2 ? ? ? fpu system control instructions 221 sts.l fpscr,@-rn co 1 1/1 #2 ? ? ? 222 fmov drm,xdn ls 1 0 #1 ? ? ? 223 fmov xdm,drn ls 1 0 #1 ? ? ? 224 fmov xdm,xdn ls 1 0 #1 ? ? ? 225 fmov @rm,xdn ls 1 2 #2 ? ? ? 226 fmov @rm+,xdn ls 1 1/2 #2 ? ? ? 227 fmov @(r0,rm),xdn ls 1 2 #2 ? ? ? 228 fmov xdm,@rn ls 1 1 #2 ? ? ? 229 fmov xdm,@-rm ls 1 1/1 #2 ? ? ? 230 fmov xdm,@(r0,rn) ls 1 1 #2 ? ? ? 231 fipr fvm,fvn fe 1 4/5 #42 f1 3 1 232 frchg fe 1 1/4 #36 ? ? ? 233 fschg fe 1 1/4 #36 ? ? ? f0 2 4 graphics acceleration instructions 234 ftrv xmtrx,fvn fe 1 (5, 5, 6, 7)/8 #43 f1 3 4 notes: 1. see table 8.1 fo r the instruction groups. 2. latency ?l1/l2...?: latency corresponding to a write to each register , including mach/macl/fpscr example: mov.b @rm+, rn ?1/2?: the lat ency for rm is 1 cycle, and the latency for rn is 2 cycles. 3. branch latency: interval until the branch destination instruction is fetched
8. pipelining rev.4.00 oct. 10, 2008 page 237 of 1122 rej09b0370-0400 4. conditional branch latency ?2 (or 1)?: the latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. double-precision floating-point instruction latency ?(l1, l2)/l3?: l1 is the latency for fr [n+1], l2 that for fr [n], and l3 that for fpscr. 6. ftrv latency ?(l1, l2, l3, l4)/l5?: l1 is t he latency for fr [n], l2 that for fr [n+1], l3 that for fr [n+2], l4 that for fr [n+3], and l5 that for fpscr. 7. latency ?l1/l2/l3/l4? of mac.l and mac.w instructions: l1 is the latency for rm, l2 that for rn, l3 that for mach, and l4 that for macl. 8. latency ?l1/l2? of mul.l, muls.w, mu lu.w, dmuls.l, and dmulu.l instructions: l1 is the latency for mach, and l2 that for macl. 9. execution pattern: the instruction execution pattern number (see figure 8.2) 10. lock/stage: stage lock ed by the instruction 11. lock/start: locking start cycle; 1 is the first d-stage of the instruction. 12. lock/cycles: number of cycles locked exceptions: 1. when a floating-point computation instru ction is followed by an fmov store, an sts fpul, rn instruction, or an sts.l fpul, @-rn instruction, the la tency of the floating- point computation is decreased by 1 cycle. 2. when the preceding instruction loads the shift amount of the following shad/shld, the latency of the load is increased by 1 cycle. 3. when an ls group instruction with a laten cy of less than 3 cycles is followed by a double-precision floating-point instruction, fipr, or ftrv, the latency of the first instruction is increased to 3 cycles. example: in the case of fmov fr4,fr0 and fipr fv0,fv4, fipr is stalled for 2 cycles. 4. when mac.w/mac.l/mul.l/muls.w/mulu. w/dmuls.l/dmulu.l is followed by an sts.l mach/macl, @-rn inst ruction, the latency of mac.w/mac.l/mul.l/muls.w/mulu. w/dmuls.l/dmulu.l is 5 cycles. 5. in the case of c onsecutive executions of mac.w/mac.l/mul.l/muls.w/mulu.w/dm uls.l/dmulu.l, the latency is decreased to 2 cycles. 6. when an lds to mach/macl is followed by an sts.l mach/macl, @-rn instruction, the latency of t he lds to mach/macl is 4 cycles. 7. when an lds to mach/macl is followed by mac.w/mac.l/mul.l/muls.w/mulu.w/dmuls. l/dmulu.l, the la tency of the lds to mach/macl is 1 cycle. 8. when an fschg or frchg instruction is followed by an ls group instruction that reads or writes to a floating-point register , the preceding ls group instruction[s] cannot be executed in parallel. 9. when a single-precision ftrc instruction is followed by an sts fpul, rn instruction, the latency of the single-precision ftrc instruction is 1 cycle.
8. pipelining rev.4.00 oct. 10, 2008 page 238 of 1122 rej09b0370-0400 8.4 usage notes the following are additional notes on pipeline operation and the method of calculating the number of clock cycles. the number of states (i clock cy cles) required for stages where an external bus access, etc., occurs may include an increased number of cycles, in a ddition to the number of memory access cycles set by the bus state controller (bsc), etc. for example, the occurrence of th e following may result in idle cycles as observed from the external bus. 1. transfer of data from the logical address bus to the physical address bus 2. transfer of data between buses using different operation clocks the stages where external memory access occurs include some instruction fetch (i) and some memory access (ma) stages.
9. power-down modes rev.4.00 oct. 10, 2008 page 239 of 1122 rej09b0370-0400 section 9 power-down modes 9.1 overview in the power-down modes, some of the on-chip peripheral modules and the cpu functions are halted, enabling power consumption to be reduced. 9.1.1 types of power-down modes the following power-down modes and functions are provided: ? sleep mode ? deep sleep mode ? standby mode ? hardware standby mode ? module standby function (tmu, rtc, sci/scif, dmac, sq, and ubc) table 9.1 shows the conditions for entering thes e modes from the program execution state, the status of the cpu and peripheral modules in each mode, and the method of exiting each mode.
9. power-down modes rev.4.00 oct. 10, 2008 page 240 of 1122 rej09b0370-0400 table 9.1 status of cpu and peripheral modules in power-down modes status power- down mode entering conditions cpg cpu on-chip memory on-chip peripheral modules pins external memory exiting method sleep sleep instruction executed while stby bit is 0 in stbcr operating halted (registers held) held operating held refresh- ing ? interrupt ? reset deep sleep sleep instruction executed while stby bit is 0 in stbcr, and dslp bit is 1 in stbcr2 operating halted (registers held) held operating (dma halted) held self- refresh- ing ? interrupt ? reset standby sleep instruction executed while stby bit is 1 in stbcr halted halted (registers held) held halted * held self- refresh- ing ? interrupt ? reset hard- ware standby setting ca pin to low level halted halted unde- fined halted * high- imped- ance state unde- fined ? power-on reset module standby setting mstp bit to 1 in stbcr operating operatin g held specified modules halted * held refresh- ing ? clearing mstp bit to 0 ? reset note: * the rtc operates when the start bit in rcr2 is 1 (see section 11, realtime clock (rtc)).
9. power-down modes rev.4.00 oct. 10, 2008 page 241 of 1122 rej09b0370-0400 9.1.2 register configuration table 9.2 shows the registers used for power-down mode control. table 9.2 power-down mode registers name abbreviation r/w initial value p4 address area 7 address access size standby control register stbcr r/w h'00 h 'ffc00004 h'1fc00004 8 standby control register 2 stbcr2 r/w h'00 h 'ffc00010 h'1fc00010 8 clock stop register clkstp00 r/w h'00000000 h'fe0a0000 h'1e0a0000 32 clock stop clear register clkstpclr00 w h'00000000 h'fe0a0008 h'1e0a0008 32 9.1.3 pin configuration table 9.3 shows the pins used for power-down mode control. table 9.3 power-down mode pins pin name abbreviation i/o function processor status 1 processor status 0 status1 status0 output indicate the proc essor's operating status (status1, status0). hh: reset hl: sleep mode lh: standby mode ll: normal operation sleep request sleep input a transition to sleep mode is effected by inputting a low-level to the pin. hardware standby request ca input a transition to hardware standby mode is effected by inputting a low-level to the pin. legend: h: high level l: low level
9. power-down modes rev.4.00 oct. 10, 2008 page 242 of 1122 rej09b0370-0400 9.2 register descriptions 9.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-b it readable/writable register that specifies the power-down mode status. it is initialized to h'00 by a power-on reset via the reset pin or due to watchdog timer overflow. bit: 7 6 5 4 3 2 1 0 stby phz ppu mstp4 mstp3 mstp2 mstp1 mstp0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?standby (stby): specifies a transition to standby mode. bit 7: stby description 0 transition to sleep mode on execution of sleep instruction (initial value) 1 transition to standby mode on execution of sleep instruction bit 6?peripheral module pin high impedance control (phz): controls the state of peripheral module related pins in standby mode. when the phz bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode. for the relevant pins, see section 9.2.2, peripheral module pin high impedance control. bit 6: phz description 0 peripheral module related pins are in normal state (initial value) 1 peripheral module related pins go to high-impedance state bit 5?peripheral module pin pull-up control (ppu): controls the state of peripheral module related pins. when the ppu bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the inpu t or high-impedance state. for the relevant pins, see section 9.2.3, peripheral module pin pull-up control. bit 5: ppu description 0 peripheral module related pin pull-up resistors are on (initial value) 1 peripheral module related pin pull-up resistors are off
9. power-down modes rev.4.00 oct. 10, 2008 page 243 of 1122 rej09b0370-0400 bit 4?module stop 4 (mstp4): specifies stopping of the clock supply to the dmac among the on-chip peripheral modules. the clock supply to the dmac is stopped when the mstp4 bit is set to 1. when dma transfer is used, stop the tran sfer before setting the mstp4 bit to 1. when dma transfer is performed after clearing the mstp4 bit to 0, dmac settings must be made again. bit 4: mstp4 description 0 dmac operates (initial value) 1 dmac clock supply is stopped bit 3?module stop 3 (mstp3): specifies stopping of the clock supply to serial communication interface channel 2 (scif) among the on-chip periphe ral modules. the clock supply to the scif is stopped when the mstp3 bit is set to 1. bit 3: mstp3 description 0 scif operates (initial value) 1 scif clock supply is stopped bit 2?module stop 2 (mstp2): specifies stopping of the clock supply to the timer unit channel 0 to 2 (tmu) among the on-chip peripheral modules. the clock supply to the tmu is stopped when the mstp2 bit is set to 1. bit 2: mstp2 description y tmu channel 0 to 2 operates (initial value) 1 tmu channel 0 to 2 clock supply is stopped bit 1?module stop 1 (mstp1): specifies stopping of the cloc k supply to the realtime clock (rtc) among the on-chip peripheral modules. the clock supply to the rtc is stopped when the mstp1 bit is set to 1. when the clock supply is stopped, rtc re gisters cannot be accessed but the counters continue to operate. bit 1: mstp1 description 0 rtc operates (initial value) 1 rtc clock supply is stopped
9. power-down modes rev.4.00 oct. 10, 2008 page 244 of 1122 rej09b0370-0400 bit 0?module stop 0 (mstp0): specifies stopping of the clock supply to serial communication interface channel 1 (sci) among the on-chip periphe ral modules. the clock supply to the sci is stopped when the mstp0 bit is set to 1. bit 0: mstp0 description 0 sci operates (initial value) 1 sci clock supply is stopped 9.2.2 peripheral module pin high impedance control when bit 6 in the standby control register (stbcr) is set to 1, peripheral module related pins go to the high-impedance st ate in standby mode. ? relevant pins sci related pins sck md0/sck2 txd md1/txd2 md7/ cts2 md8/ rts2 dma related pins dack0 drak0 dack1 drak1 ? other information the setting in this register is invalid when the above pins are used as port output pins. for details of pin states, see appendix d, pin functions. 9.2.3 peripheral module pin pull-up control when bit 5 in the standby control register (stbcr) is cleared to 0, peripheral module related pins are pulled up when in the in put or high-impedance state. ? relevant pins sci related pins md0/sck2 md1/txd2 md2/rxd2 md7/ cts2 md8/ rts2 sck rxd txd dma related pins dreq0 dack0 drak0 dreq1 dack1 drak1 tmu related pin tclk
9. power-down modes rev.4.00 oct. 10, 2008 page 245 of 1122 rej09b0370-0400 9.2.4 standby control register 2 (stbcr2) standby control register 2 (stbcr2) is an 8-bit re adable/writable register that specifies the sleep mode and deep sleep mode transition conditions. it is initialized to h'00 by a power-on reset via the reset pin or due to watchdog timer overflow. bit: 7 6 5 4 3 2 1 0 dslp sthz ? ? ? ? mstp6 mstp5 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r r/w r/w bit 7?deep sleep (dslp): specifies a transition to deep sleep mode bit 7: dslp description 0 transition to sleep mode or stand by mode on execution of sleep instruction, according to setting of stby bit in stbcr register (initial value) 1 transition to deep sleep mode on execution of sleep instruction * note: * when the stby bit in the stbcr register is 0 bit 6?status pin high-impedance control (sthz): this bit selects whether the status0 and 1 pins are set to high-impedance when in hardware standby mode. bit 6: sthz description 0 sets status0, 1 pins to high-impedance when in hardware standby mode (initial value) 1 drives status0, 1 pins to lh when in hardware standby mode bits 5 to 2?reserved: only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. these bits are always read as 0. bit 1?module stop 6 (mstp6): specifies that the clock supply to the store queue (sq) in the cache controller (ccn) is stopped. setting the mstp 6 bit to 1 stops the cl ock supply to the sq, and the sq functions are therefore unavailable. for details regarding the sh7751, see section 4.7, store queues. bit 1: mstp6 description 0 sq operating (initial value) 1 clock supply to sq stopped
9. power-down modes rev.4.00 oct. 10, 2008 page 246 of 1122 rej09b0370-0400 bit 0?module stop 5 (mstp5): specifies stopping of the cloc k supply to the user break controller (ubc) among the on-chip peripheral modules. see section 20.6, user break controller stop function for how to set the clock supply. bit 0: mstp5 description 0 ubc operating (initial value) 1 clock supply to ubc stopped 9.2.5 clock stop register 00 (clkstp00) clock stop register 00 (clkstp00) is a 32-bit readable/writable register that controls the operating clock for peripheral modules. the clock supply is restarted by writing 1 to the corresponding bit in the clkstpclr00 register. writing 0 to clkstp00 will not change the bit value. clkstp00 is initialized to h'00000000 by a reset. it is not initialized in standby mode. bit: 31 30 29 ... 11 10 9 8 ? ? ? ... ? ? ? ? initial value: 0 0 0 ... 0 0 0 0 r/w: r r r ... r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? cstp2 cstp1 cstp0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 31 to 3?reserved: these bits are always read as 0, and should only be written with 0. bit 2?clock stop 2 (cstp2): specifies stopping of the peripheral clock supply to the pci bus controller (pcic). for details see section 22, pci controller (pcic). bit 2: cstp2 description 0 peripheral clock is supplied to pcic (initial value) 1 peripheral clock supply to pcic is stopped
9. power-down modes rev.4.00 oct. 10, 2008 page 247 of 1122 rej09b0370-0400 bit 1?clock stop 1 (cstp1): specifies stopping of the peripheral clock supply to timer unit (tmu) channels 3 and 4. bit 1: cstp1 description 0 peripheral clock is supplied to tmu channels 3 and 4 (initial value) 1 peripheral clock supply to tmu channels 3 and 4 is stopped bit 0?clock stop 0 (cstp0): specifies stopping of the peripheral clock supply to the interrupt controller (intc). when this bit is set, pcic and tmu channel 3 and 4 interrupts are not detected. bit 0: cstp0 description 0 intc detects pcic and tmu channel 3 and 4 interrupts (initial value) 1 intc does not detect pcic and tmu channel 3 and 4 interrupts 9.2.6 clock stop clear register 00 (clkstpclr00) clock stop clear register 00 (clkstpclr00) is a 32-bit write-only register that is used to clear corresponding bits in the clkstp00 register. bit: 31 30 29 ... 11 10 9 8 ... initial value: 0 0 0 ... 0 0 0 0 r/w: w w w ... w w w w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: w w w w w w w w bits 31 to 0?clock stop clear: the value of a clock stop clear bit indicates whether the corresponding clock stop bit is to be cleared. see section 9.2.5, clock stop register 00 (clkstp00), for the correspondence between bits and the clocks stopped. bits 31 to 0 description 0 corresponding clock stop bit is not changed (initial value) 1 corresponding clock stop bit is cleared
9. power-down modes rev.4.00 oct. 10, 2008 page 248 of 1122 rej09b0370-0400 9.3 sleep mode 9.3.1 transition to sleep mode if a sleep instruction is executed when the stby bit in stbcr is cleared to 0, the chip switches from the program execution state to sleep mode. after execution of the sleep instruction, the cpu halts but its register contents are retained. the on-chip peripheral modules continue to operate, and the clock continues to be output from the ckio pin. in sleep mode, a high-level signal is output at the status1 pin, and a low-level signal at the status0 pin. 9.3.2 exit from sleep mode sleep mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset. in sleep mode, interrupts are accepted even if the bl bit in the sr regi ster is 1. if necessary, spc and ssr should be saved to the stack before executing the sleep instruction. exit by interrupt: when an nmi, irl, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. the code corresponding to the interrupt source is set in the intevt register. exit by reset: sleep mode is exited by means of a power-on or manual reset via the reset pin, or a power-on or manual reset executed when the watchdog timer overflows. 9.4 deep sleep mode 9.4.1 transition to deep sleep mode if a sleep instruction is executed when the stby bit in stbcr is cleared to 0 and the dslp bit in stbcr2 is set to 1, the chip switches from the program execution state to deep sleep mode. after execution of the sleep inst ruction, the cpu halts but its register contents are retained. except for the dmac*, on-chip peripheral modules continue to operate. the clock continues to be output to the ckio pin, but all bus access (including auto refresh) stops. when using memory that requires refreshing, set the self-refresh function pr ior to making the transition to deep sleep mode. in deep sleep mode, a high-level signal is output at the status1 pin, and a low-level signal at the status0 pin.
9. power-down modes rev.4.00 oct. 10, 2008 page 249 of 1122 rej09b0370-0400 note: * terminate dma transfer s prior to making the transition to deep sleep mode. if you make a transition to deep sleep mode while dma transfers are in progress, the results of those transfers cannot be guaranteed. 9.4.2 exit from deep sleep mode as with sleep mode, deep sleep mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset. 9.5 pin sleep mode 9.5.1 transition to pin sleep mode changing the sleep pin to the low level causes this lsi to make a transition to sleep mode. to ensure that memory is correctly refreshed, us e this function when the dslp bit of stbcr2 is set to 0. 9.5.2 exit from pin sleep mode setting the sleep pin level high causes this lsi to return to the normal state. the pin sleep mode is also canceled when the conditions specified in section 9.3.2, ?exit from sleep mode? are satisfied. in a power-on reset, the sleep pin should be fixed high. 9.6 standby mode 9.6.1 transition to standby mode if a sleep instruction is executed when the stby bit in stbcr is set to 1, the chip switches from the program execution state to standby mode. in standby mode, the on-chip peripheral modules halt as well as the cpu. clock output from the ckio pin is also stopped. the cpu and cache register contents are retained . some on-chip peripheral module registers are initialized. the state of the peripheral module registers in standby mode is shown in table 9.4.
9. power-down modes rev.4.00 oct. 10, 2008 page 250 of 1122 rej09b0370-0400 table 9.4 state of registers in standby mode module initialized registers registers that retain their contents interrupt controller ? all registers user break controller ? all registers bus state controller ? all registers on-chip oscillation circuits ? all registers timer unit tstr register * all registers except tstr realtime clock ? all registers direct memory access controller ? all registers serial communication interface see appendix a, address list see appendix a, address list notes: dma transfer should be terminated before making a transition to standby mode. transfer results are not guaranteed if standby mode is entered during transfer. * not initialized when the realtime clock (r tc) is in use (see section 12, timer unit (tmu)). the procedure for a transition to standby mode is shown below. 1. clear the tme bit in the wdt timer contro l register (wtcsr) to 0, and stop the wdt. set the initial value for the up-count in the wdt timer counter (wtcnt), and set the clock to be used for the up-count in bits cks2?cks0 in the wtcsr register. 2. set the stby bit in the stbcr register to 1, then execute a sleep instruction. 3. when standby mode is entered and the chip's internal clock stops, a low-level signal is output at the status1 pin, and a high-lev el signal at the status0 pin. 9.6.2 exit from standby mode standby mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset via the reset and mreset pins. exit by interrupt: a hot start can be performed by means of the on-chip wdt. when an nmi, irl * 1 , rtc, or gpio * 2 interrupt is detected, the wdt starts counting. after the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the status1 and status0 pins both go low. interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the intevt register. in standby mode, interrupts are accepted even if the bl bit in the sr register is 1, and so, if necessary, spc and ssr should be saved to the stack before executing the sleep instruction.
9. power-down modes rev.4.00 oct. 10, 2008 page 251 of 1122 rej09b0370-0400 the phase of the ckio pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. notes: 1. only when the rtc clock (32.768 khz) is operating (see section 19.2.2, irl interrupts), standby mode can be exited by means of irl3?irl0 (when the irl3? irl0 level is higher than the sr register imask mask level). 2. gpic can be used to cancel standby mode when th e rtc clock (32.768 khz) is operating (when the gpic level is higher than the sr register imask mask level). exit by reset: standby mode is exited by means of a reset (power-on or manual) via the reset pin. the reset pin should be held low until clock oscillation stabilizes. the internal clock continues to be output at the ckio pin. 9.6.3 clock pause function in standby mode, it is possible to stop or change the frequency of the clock input from the extal pin. this function is used as follows. 1. enter standby mode following the transition procedure described above. 2. when standby mode is entered and the chip's internal clock stops, a low-level signal is output at the status1 pin, and a high-lev el signal at the status0 pin. 3. the input clock is stopped, or its frequency changed, after the status1 pin goes low and the status0 pin high. 4. when the frequency is changed, input an nm i or irl interrupt after the change. when the clock is stopped, input an nmi or irl interrupt after applying the clock. 5. after the time set in the wdt, clock supply begins inside the chip, the status1 and status0 pins both go low, and operation is resumed from interrupt exception handling. 9.7 module standby function 9.7.1 transition to module standby function setting the mstp6?mstp0 and cstp 2?cstp0 bits in the standby control register, standby control register 2, and clock stop clear register 00 to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. use of this function allows power consumption in sleep mode to be further reduced. in the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
9. power-down modes rev.4.00 oct. 10, 2008 page 252 of 1122 rej09b0370-0400 bit description cstp2 0 peripheral clock is supplied to pcic 1 peripheral clock supply to pcic is stopped cstp1 0 peripheral clock is supplied to tmu channels 3 and 4 1 peripheral clock supply to tmu channels 3 and 4 is stopped cstp0 0 intc detects pcic and tmu channel 3 and 4 interrupts 1 intc does not detect pcic and tmu channel 3 and 4 interrupts mstp6 0 sq operates 1 clock supplied to sq is stopped mstp5 0 ubc operates 1 clock supplied to ubc is stopped * 3 mstp4 0 dmac operates 1 clock supplied to dmac is stopped * 4 mstp3 0 scif operates 1 clock supplied to scif is stopped mstp2 0 tmu operates 1 clock supplied to tmu is stopped, and register is initialized * 1 mstp1 0 rtc operates 1 clock supplied to rtc is stopped * 2 mstp0 0 sci operates 1 clock supplied to sci is stopped notes: 1. the register initialized is the same as in standby mode, but initialization is not performed if the rtc clock is not in us e (see section 12, timer unit (tmu)). 2. the counter operates when the start bi t in rcr2 is 1 (see section 11, realtime clock (rtc)). 3. for details, see section 20.6, user break controller stop function. 4. terminate dma transfers prior to making the transition to module standby mode. if you make a transition to module standby mode while dma transfers are in progress, the results of those transfe rs cannot be guaranteed. 9.7.2 exit from module standby function in the case of the standby control register and standby control register 2, the module standby function is exited by writing 0 to the mstp6?mstp0 bits. in the case of clock stop register 00, the module standby function is exited by writing 1 to the corresponding bit in clock stop clear register 00.
9. power-down modes rev.4.00 oct. 10, 2008 page 253 of 1122 rej09b0370-0400 the module standby function is not exited by means of a power-on reset via the reset pin or a power-on reset caused by watchdog timer overflow. 9.8 hardware standby mode 9.8.1 transition to hardware standby mode setting the ca pin level low effects a transition to hardware standby mode. in this mode, all modules other than the rtc stop, as in the st andby mode selected using the sleep command. hardware standby mode differs from standby mode as follows: 1. interrupts and manual resets are not available; 2. all output pins other than the status pin are in the high-impedance state and the pull-up resistance is off. 3. on the sh7751, the rtc continues to operate even when no power is supplied to power pins other than the rtc power supply pin. the status of the status pin is determined by the sthz bit of stbcr2. see section d, pin functions, for details of output pin states. operation when a low-level is input to the ca pin when in the standby mode depends on the cpg status, as follows: 1. in standby mode the clock remains stopped and a transition is made to the hardware standby state. interrupts and manual resets are disabled, but the output pins re main in the same state as in standby mode. 2. when wdt is operating when standby mode is exited by interrupt standby mode is momentarily exited, the cpu restarts, and then a transition is made to hardware standby mode. note that the level of the ca pin must be kept low while in hardware standby mode. 9.8.2 exit from hardware standby mode hardware standby mode can only be cancelled by a power-on reset. driving the ca pin high when the reset pin is being driven low causes clock oscilla tion to start. at this point, maintain the reset pin at low level until clock oscillation stabilizes. the cpu will start power-on reset processing if the reset pin is driven high. hardware standby mode cannot be cancelled by an interrupt or a manual reset.
9. power-down modes rev.4.00 oct. 10, 2008 page 254 of 1122 rej09b0370-0400 9.8.3 usage notes 1. the ca pin level must be kept high when the rtc power supply is started (figure 9.15). 2. on the sh7751r, supply power to the v dd , v ddq , v dd-cpg , v dd ? pll1 , and v dd-pll2 power supply pins in addition to the rtc power supply pin in hardware standby mode. 9.9 status pin change timing the status1 and status0 pin change timing is shown below. the meaning of the status pin settings is as follows: reset: hh (status1 high, status0 high) sleep: hl (status1 high, status0 low) standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) the meaning of the clock units is as follows: bcyc: bus clock cycle pcyc: peripheral clock cycle
9. power-down modes rev.4.00 oct. 10, 2008 page 255 of 1122 rej09b0370-0400 9.9.1 in reset power-on reset ckio reset status normal reset normal 0?5 bcyc 0?30 bcyc pll stabilization time figure 9.1 status output in power-on reset manual reset ckio (hi g h) reset m reset * status normal reset normal 0?30 bcyc 0 bcyc note: * in a manual reset, status = hh (reset) is set and an internal reset started after waitin g until the end of the currently executin g bus cycle. must be asserted for t resw or lon g er figure 9.2 status output in manual reset
9. power-down modes rev.4.00 oct. 10, 2008 page 256 of 1122 rej09b0370-0400 9.9.2 in exit from standby mode standby interrupt ckio status normal standby normal wdt count oscillation stops interrupt request wdt overflow figure 9.3 status output in standby interrupt sequence standby power-on reset reset ckio r eset * 1 status normal reset normal 0?10 bcyc standby oscillation stops * 2 0?30 bcyc notes: 1. when standby mode is exited by means of a power-on reset, a wdt count is not performed. hold reset low for the pll oscillation stabilization time. 2. undefined figure 9.4 status output in standby power-on reset sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 257 of 1122 rej09b0370-0400 standby manual reset ckio (hi g h) reset status normal reset mreset * undefined standby normal 0?20 bcyc 0?30 bcyc note: * when standby mode is exited by means of a manual reset, a wdt count is not performed. hold mreset low for the pll oscillation stabilization time. reset oscillation stops figure 9.5 status output in standby manual reset sequence 9.9.3 in exit from sleep mode sleep interrupt ckio status normal sleep normal interrupt request figure 9.6 status output in sleep interrupt sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 258 of 1122 rej09b0370-0400 sleep power-on reset reset ckio status normal reset sleep normal 0?10 bcyc 0?30 bcyc r eset * 1 * 2 notes: 1. when sleep mode is exited by means of a power-on reset, hold reset low for the oscillation stabilization time. 2. undefined figure 9.7 status output in sleep power-on reset sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 259 of 1122 rej09b0370-0400 sleep manual reset reset reset status normal reset m reset * sleep normal ckio (hi g h) 0?30 bcyc 0?30 bcyc note: * hold mreset low until status = reset. figure 9.8 status output in sleep manual reset sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 260 of 1122 rej09b0370-0400 9.9.4 in exit from deep sleep mode deep sleep interrupt ckio status normal sleep normal interrupt request figure 9.9 status output in deep sleep interrupt sequence deep sleep power-on reset reset ckio status normal sleep reset normal 0?10 bcyc 0?30 bcyc reset * 1 * 2 notes: 1. when deep sleep mode is exited by means of a power-on reset, hold reset low for the oscillation stabilization time. 2. undefined figure 9.10 status output in deep sleep power-on reset sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 261 of 1122 rej09b0370-0400 deep sleep manual reset reset reset status normal sleep reset m reset * normal ckio (hi g h) 0?30 bcyc 0?30 bcyc note: * hold mreset low until status = reset. figure 9.11 status output in deep sleep manual reset sequence
9. power-down modes rev.4.00 oct. 10, 2008 page 262 of 1122 rej09b0370-0400 9.9.5 hardware standby mode timing figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. the ca pin level must be kept low while in hardware standby mode. after setting the reset pin level low, the clock starts when the ca pin level is switched to high. ckio ca status reset 0?10 bcyc 0?10 bcyc standby * 2 reset waitin g for end of bus cycle undefined notes: 1. same at sleep and reset 2. hi g h impedance when stbcr2. sthz = 0 normal * 1 figure 9.12 hardware standby mode timing (when ca = low in normal operation)
9. power-down modes rev.4.00 oct. 10, 2008 page 263 of 1122 rej09b0370-0400 ckio (hi g h) ca status standby 0?10 bcyc normal reset standby * wdt count wdt overflow interrupt request note: * hi g h impedance when stbcr2. sthz = 0 figure 9.13 hardware standby mode timing (when ca = low in wdt operation) v ddq * v dd reset ca min 0s min 0s max 50 s note: * v ddq , v dd-cpg v dd min figure 9.14 timing when po wer other than vdd-rtc is off
9. power-down modes rev.4.00 oct. 10, 2008 page 264 of 1122 rej09b0370-0400 ca v dd-rtc reset v dd , v ddq * min 0s note: * v dd , v dd-pll1/2 , v ddq , v dd-cpg power-on oscillation settlin g time figure 9.15 timing when vdd-rtc power is off on 9.10 usage notes 9.10.1 note on current consumption after a power-on reset, the current consumption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating-point operation instructions listed below is executed. 1. arithmetic operation instructions mac.w, mac.l 2. floating-point operation instructions ? when fpscr.pr = 0 fadd, fsub, fmul, fmac, float, ftrc, fdiv, fsqrt, fipr, ftrv ? when fpscr.pr = 1 fadd, fsub, fmul, float, ftrc, fdiv, fsqrt, fcnvsd, fcnvds workaround: after a power-on reset, execute one or more of the above instructions before transitioning to sleep mode or standby mode.
9. power-down modes rev.4.00 oct. 10, 2008 page 265 of 1122 rej09b0370-0400 example: to reduce the effect on fpscr, arrange the following two instructions starting at h'a0000000. address instruction string h'a0000000 fldi1 fr0 h'a0000002 fadd fr0, fr0 ; fldi1 fr0 loads 1 into fr0, : : ; so the cause and flag bits of fpscr are not set to 1.
9. power-down modes rev.4.00 oct. 10, 2008 page 266 of 1122 rej09b0370-0400
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 267 of 1122 rej09b0370-0400 section 10 clock oscillation circuits 10.1 overview the on-chip oscillation circuits comprise a clock pulse generator (cpg) and a watchdog timer (wdt). the cpg generates the clocks supplied inside the processor and performs power-down mode control. the wdt is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed. it can be used as a normal watchdog timer or an interval timer. 10.1.1 features the cpg has the following features: ? three clocks the cpg can generate the cpu clock (ick) us ed by the cpu, fpu, caches, and tlb, the peripheral module clock (pck) used by the peripheral modules, and the bus clock (bck) used by the external bus interface. ? six clock modes any of six clock operating modes can be selected, with different combinations of cpu clock, bus clock, and peripheral module clock division ratios after a power-on reset. ? frequency change function pll (phase-locked loop) circuits and a frequency divider in the cpg enable the cpu clock, bus clock, and peripheral module clock frequencies to be changed. frequency changes are performed by software in accordance with th e settings in the frequency control register (frqcr). ? pll on/off control power consumption can be reduced by stopping the pll circuits during low-frequency operation. ? power-down mode control it is possible to stop the clock in sleep mode and standby mode, and to stop specific modules with the module standby function.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 268 of 1122 rej09b0370-0400 the wdt has the following features ? can be used to secure clock stabilization time used when exiting standby mode or a temporary standby state when the clock frequency is changed. ? can be switched between watchdog timer mode and interval timer mode ? internal reset generation in watchdog timer mode an internal reset is executed on counter overflow. power-on reset or manual reset can be selected. ? interrupt generation in interval timer mode an interval timer interrupt is generated on counter overflow. ? selection of eight counter input clocks any of eight clocks can be selected, scaled from the 1 clock of frequency divider 2 shown in figure 10.1. the cpg is described in sections 10.2 to 10.6, and the wdt in sections 10.7 to 10.9.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 269 of 1122 rej09b0370-0400 10.2 overview of cpg 10.2.1 block diagram of cpg figures 10.1(1) and 10.1(2) show a block diagram of the cpg in the sh7751 and sh7751r. legend: frqcr: frequency control register stbcr: standby control register stbcr2: standby control register 2 oscillator circuit pll circuit 1 frequency divider 2 crystal oscillation circuit frequency divider 1 pll circuit 2 cpu clock (ick) cycle icyc peripheral module clock (pck) cycle pcyc bus clock (bck) cycle bcyc cpg control unit clock frequency control circuit standby control circuit bus interface internal bus xtal extal md8 ckio md2 md1 md0 frqcr stbcr2 1 1/2 1/3 1/4 1/6 1/8 6 1/2 1 stbcr figure 10.1 (1) block diagram of cpg (sh7751)
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 270 of 1122 rej09b0370-0400 legend: frqcr: stbcr: stbcr2: frequency control register standby control register standby control register 2 oscillator circuit pll circuit 1 frequency divider 2 crystal oscillation circuit cpu clock (ick) cycle icyc peripheral module clock (pck) cycle pcyc bus clock (bck) cycle bcyc cpg control unit clock frequency control circuit standby control circuit bus interface internal bus xtal extal md8 ckio md2 md1 md0 frqcr stbcr2 1 1/2 1/3 1/4 1/6 1/8 6 12 pll circuit 2 1 stbcr figure 10.1 (2) block diagram of cpg (sh7751r)
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 271 of 1122 rej09b0370-0400 the function of each of the cpg blocks is described below. pll circuit 1: pll circuit 1 has a function for multiplying the clock frequency from the extal pin or crystal oscillation circuit by 6 (sh7751 and sh7751r) or 12 (sh7751r). starting and stopping is controlled by a frequency control register setting. control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. pll circuit 2: pll circuit 2, according to the output clock feedback from the ckio pin, coordinates the phases of the bus clock and the ckio pin output clock. starting and stopping is controlled by a frequency control register setting. crystal oscillation circuit: this is the oscillator circuit used when a crystal resonator is connected to the xtal and extal pins. use of th e crystal oscillation circuit can be selected with the md8 pin. frequency divider 1 (sh7751r only): frequency divider 1 has a function for adjusting the clock waveform duty to 50% by halving the input clock frequency when clock input from the extal pin is supplied internally without using pll circuit 1. frequency divider 2: frequency divider 2 generates the cpu clock (ick), bus clock (bck), and peripheral module clock (pck). the division ratio is set in the frequency control register. clock frequency control circuit: the clock frequency control circuit controls the clock frequency by means of the md pins and frequency control register. standby control circuit: the standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched and in sleep and standby modes. frequency control register (frqcr): the frequency control register contains control bits for clock output from the ckio pin, pll circuit 1 and 2 on/off control, and the cpu clock, bus clock, and peripheral module clock frequency division ratios. standby control register (stbcr): the standby control register contains power save mode control bits. for further information on the standby control register, see section 9, power-down modes. standby control register 2 (stbcr2): standby control register 2 contains a power save mode control bit. for further information on standby control register 2, see section 9, power-down modes.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 272 of 1122 rej09b0370-0400 10.2.2 cpg pin configuration table 10.1 shows the cpg pins and their functions. table 10.1 cpg pins pin name abbreviation i/o function mode control pins md0 input set clock operating mode md1 md2 xtal output connects crystal resonator extal input connects crystal resonator, or used as external clock input pin crystal i/o pins (clock input pins) md8 input selects use/non-u se of crystal resonator when md8 = 0, external clock is input from extal when md8 = 1, crystal resonator is connected directly to extal and xtal clock output pin ckio output used as external clock output pin level can also be fixed ckio enable pin cke output 0 when ckio output clock is unstable and in case of synchronous dram self-refreshing * note: * set to 1 in a power-on reset. for details of synchronous dram self-re freshing, see section 13.3.5, synchronous dram interface. 10.2.3 cpg register configuration table 10.2 shows the cpg register configuration. table 10.2 cpg register name abbreviation r/w initial value p4 address area 7 address access size frequency control register frqcr r/w undefined h?ffc00000 h?1fc00000 16
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 273 of 1122 rej09b0370-0400 10.3 clock operating modes tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (md2?md0) settings (initial settings such as the frequency division ratio). table 10.4 shows frqcr settings and internal clock frequencies. table 10.3 (1) clock operating modes (sh7751) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 off on on 6 3/2 3/2 h'0e1a 1 0 1 off on on 6 1 1 h'0e23 2 0 on on on 3 1 1/2 h'0e13 3 0 1 1 off on on 6 2 1 h'0e13 4 1 0 0 on on on 3 3/2 3/4 h'0e0a 5 1 off on on 6 3 3/2 h'0e0a 6 1 0 off off off 1 1/2 1/2 h'0808 notes: 1. the clock operating mode is the only factor to determine whether to turn the 1/2 frequency divider on or off. 2. for the frequency range of the input cl ock, see the extal clock input frequency (f ex ) and ckio clock output (f op ) in section 23.3.1, clock and control signal timing. table 10.3 (2) clock operating modes (sh7751r) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 on ( 12) on 12 3 3 h'0e1a 1 0 1 on ( 12) on 12 3/2 3/2 h'0e2c 2 0 on ( 6) on 6 2 1 h'0e13 3 0 1 1 on ( 12) on 12 4 2 h'0e13 4 1 0 on ( 6) on 6 3 3/2 h'0e0a 5 0 1 on ( 12) on 12 6 3 h'0e0a 6 1 0 off ( 6) off 1 1/2 1/2 h'0808 notes: 1. the multiplication factor of pll1 is solely determined by the clock operating mode.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 274 of 1122 rej09b0370-0400 2. for the ranges input clock frequency, s ee the description of the extal clock input frequency (f ex ) and the ckio clock output (f op ) in section 23.3.1, clock and control signal timing. table 10.4 frqcr settings and internal clock frequencies frequency division ratio of frequency divider 2 frqcr (lower 9 bits) cpu clock bus clock peripheral module clock h'000 1/2 h'002 1/4 h'004 1 1/8 h'008 1/2 h'00a 1/4 h'00c 1/2 1/8 h'011 1/3 h'013 1/3 1/6 h'01a 1/4 h'01c 1/4 1/8 h'023 1/6 1/6 h'02c 1 1/8 1/8 h'048 1/2 h'04a 1/4 h'04c 1/2 1/8 h'05a 1/4 h'05c 1/4 1/8 h'063 1/6 1/6 h'06c 1/2 1/8 1/8 h'091 1/3 h'093 1/3 1/6 h'0a3 1/3 1/6 1/6 h'0da 1/4 h'0dc 1/4 h'0ec 1/4 1/8 1/8 h'123 1/6 1/6 1/6 h'16c 1/8 1/8 1/8 note: do not set values other than those shown in the table for the lower 9 bits of frqcr.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 275 of 1122 rej09b0370-0400 10.4 cpg register description 10.4.1 frequency cont rol register (frqcr) the frequency control register (frqcr) is a 16 -bit readable/writable re gister that specifies use/non-use of clock output from the ckio pin, pll circuit 1 and 2 on/off control, and the cpu clock, bus clock, and periphera l module clock frequency division ratios. only word access can be used on frqcr. frqcr is initialized only by a power-on reset via the reset pin. the initial value of each bit is determined by the clock operating mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ckoen pll1en pll2en ifc2 initial value: 0 0 0 0 1 1 1 ? r/w: r/w r/w r/w r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ifc1 ifc0 bfc2 bfc1 bfc0 pfc2 pfc1 pfc0 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12?reserved: these bits are always read as 0, and should only be written with 0. bit 11?clock output enable (ckoen): specifies whether a clock is output from the ckio pin or the ckio pin is placed in the high-impedance state. when the ckio pin goes to the high- impedance state, operation conti nues at the operating frequency be fore this state was entered. when the ckio pin becomes high-impedance, it is pulled up. bit 11: ckoen description 0 ckio pin goes to high-impedance state (pulled up * ) 1 clock is output from ckio pin (initial value) note: * it is not pulled up in hardware standby mode.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 276 of 1122 rej09b0370-0400 bit 10?pll circuit 1 enable (pll1en): specifies whether pll circ uit 1 is on or off. bit 10: pll1en description 0 pll circuit 1 is not used 1 pll circuit 1 is used (initial value) bit 9?pll circuit 2 enable (pll2en): specifies whether pll circuit 2 is on or off. bit 9: pll2en description 0 pll circuit 2 is not used 1 pll circuit 2 is used (initial value) bits 8 to 6?cpu clock frequency division ratio (ifc): these bits specify the cpu clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 8: ifc2 bit 7: ifc1 bit 6: ifc0 description 0 0 0 1 1 1/2 1 0 1/3 1 1/4 1 0 0 1/6 1 1/8 other than the above setting prohibited (do not set)
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 277 of 1122 rej09b0370-0400 bits 5 to 3?bus clock frequency division ratio (bfc): these bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 5: bfc2 bit 4: bfc1 bit 3: bfc0 description 0 0 0 1 1 1/2 1 0 1/3 1 1/4 1 0 0 1/6 1 1/8 other than the above setting prohibited (do not set) bits 2 to 0?peripheral module clock frequency division ratio (pfc): these bits specify the peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 2: pfc2 bit 1: pfc1 bit 0: pfc0 description 0 0 0 1/2 1 1/3 1 0 1/4 1 1/6 1 0 0 1/8 other than the above setting prohibited (do not set)
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 278 of 1122 rej09b0370-0400 10.5 changing the frequency there are two methods of changing the internal clock frequency: by changing stopping and starting of pll circuit 1, and by changing the frequ ency division ratio of each clock. in both cases, control is performed by software by means of the frequency control register. these methods are described below. 10.5.1 changing pll circuit 1 starting/stopping (when pll circuit 2 is off) when pll circuit 1 is changed from the stopped to started state, a pll circuit 1 oscillation stabilization time is required. the oscillation stab ilization time count is performed by the on-chip wdt. 1. set a value in wdt to provide the specified oscillation stabilization time, and stop the wdt. the following settings are necessary: wtcsr register tme bit = 0: wdt stopped wtcsr register cks2?cks0 bits: wdt count clock division ratio wtcnt counter: initial counter value 2. set the pll1en bit to 1. 3. internal processor operation stops temporarily, and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing. 10.5.2 changing pll circuit 1 starting/stopping (when pll circuit 2 is on) when pll circuit 2 is on, a pll circuit 1 and pll circuit 2 oscillation stabilization time is required. 1. make wdt settings as in section 10.5.1. 2. set the pll1en bit to 1. 3. internal processor operation stops temporarily , pll circuit 1 oscillates, and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, pll circuit 2 starts oscillating. the wdt resumes its up- count from the value set in step 1 above. during this time, also, the internal clock is stopped and an unstable clock is output to the ckio pin. 5. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 279 of 1122 rej09b0370-0400 10.5.3 changing bus clock division ratio (when pll circuit 2 is on) if pll circuit 2 is on when the bus clock frequency division ratio is changed, a pll circuit 2 oscillation stabilization time is required. 1. make wdt settings as in section 10.5.1. 2. set the bfc2?bfc0 bits to the desired value. 3. internal processor operation stops temporarily , and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing. 10.5.4 changing bus clock division ratio (when pll circuit 2 is off) if pll circuit 2 is off when the bus clock frequency division ratio is changed, a wdt count is not performed. 1. set the bfc2?bfc0 bits to the desired value. 2. the set clock is switched to immediately. 10.5.5 changing cpu or peripheral module clock division ratio when the cpu or peripheral module clock frequency division ratio is changed, a wdt count is not performed. 1. set the ifc2?ifc0 or pfc2?pfc0 bits to the desired value. 2. the set clock is switched to immediately.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 280 of 1122 rej09b0370-0400 10.6 output clock control the ckio pin can be switched between clock output and a high-impedance state by means of the ckoen bit in the frqcr register. when the ckio pin goes to the high-impedance state, it is pulled up. 10.7 overview of watchdog timer 10.7.1 block diagram figure 10.2 shows a block diagram of the wdt. standby release internal reset request interrupt request standby control reset control interrupt control wtcsr wtcnt bus interface clock selection overflow frequency divider clock selector clock wdt le g end: wtcsr: watchdo g timer control/status re g ister wtcnt: watchdo g timer counter standby mode frequency divider 2 1 clock figure 10.2 block diagram of wdt
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 281 of 1122 rej09b0370-0400 10.7.2 register configuration the wdt has the two registers summarized in tabl e 10.5. these registers control clock selection and timer mode switching. table 10.5 wdt registers name abbreviation r/w initial value p4 address area 7 address access size watchdog timer counter wtcnt r/w * h'00 h'ffc00008 h'1fc 00008 r: 8, w: 16 * watchdog timer control/status register wtcsr r/w * h'00 h'ffc0000c h'1fc0000c r: 8, w: 16 * note: * use word-size access when writing. perform t he write with the upper byte set to h'5a or h'a5, respectively. byte- and longword-size writes cannot be used. use byte access when reading. 10.8 wdt register descriptions 10.8.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit re adable/writable counter that counts up on the selected clock. when wtcnt overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. wtcnt is initialized to h'00 only by a power-on reset via the reset pin. to write to the wtcnt counter, use a word-size access with the upper byte set to h'5a. to read wtcnt, use a byte-size access. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 282 of 1122 rej09b0370-0400 10.8.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtc sr) is an 8-bit readable/writable register containing bits for selecting the count cl ock and timer mode, and overflow flags. wtcsr is initialized to h'00 only by a power-on reset via the reset pin. it retains its value in an internal reset due to wdt overflow. when used to count the clock stabilization time when exiting standby mode, wtcsr retains its value after the counter overflows. to write to the wtcsr register, use a word-size access with the upper byte set to h'a5. to read wtcsr, use a byte-size access. bit: 7 6 5 4 3 2 1 0 tme wt/ it rsts wovf iovf cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?timer enable (tme): specifies starting and stopping of timer operation. clear this bit to 0 when using the wdt in standby mode or to change a clock frequency. bit 7: tme description 0 up-count stopped, wtcnt value retained (initial value) 1 up-count started bit 6?timer mode select (wt/ it ): specifies whether the wdt is used as a watchdog timer or interval timer. bit 6: wt/ it description 0 interval timer mode (initial value) 1 watchdog timer mode note: the up-count may not be performed correctly if wt/ it is modified while the wdt is running. bit 5?reset select (rsts): specifies the kind of reset to be performed when wtcnt overflows in watchdog timer mode. this setting is ignored in interval timer mode. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 283 of 1122 rej09b0370-0400 bit 4?watchdog timer overflow flag (wovf): indicates that wtcnt has overflowed in watchdog timer mode. this flag is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3?interval timer overflow flag (iovf): indicates that wtcnt has overflowed in interval timer mode. this flag is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode bits 2 to 0?clock select 2 to 0 (cks2?cks0): these bits select the clock used for the wtcnt count from eight clocks obtained by dividing the frequency divider 2 input clock*. the overflow periods shown in the following table are for use of a 33 mhz input clock, with frequency divider 1 off, and pll circuit 1 on ( 6). note: * when pll1 is switched on or off, the clock following the switch is used. description bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period 0 0 0 1/32 (initial value) 41 s 1 1/64 82 s 1 0 1/128 164 s 1 1/256 328 s 1 0 0 1/512 656 s 1 1/1024 1.31 ms 1 0 1/2048 2.62 ms 1 1/4096 5.25 ms note: the up-count may not be performed correctly if bits cks2?cks0 are modified while the wdt is running. always stop the wdt before modifying these bits.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 284 of 1122 rej09b0370-0400 10.8.3 notes on register access the watchdog timer counter (wtcnt) and watchd og timer control/status register (wtcsr) differ from other registers in being more difficu lt to write to. the procedure for writing to these registers is given below. writing to wtcnt and wtcsr: these registers must be written to with a word transfer instruction. they cannot be written to with a byte or longword transfer instruction. when writing to wtcnt, perform the transfer with the upper byte set to h'5a and the lower byte containing the write data. when writing to wtcsr, perform the tr ansfer with the upper byte set to h'a5 and the lower byte containing the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. the write form ats are shown in figure 10.3. 15 8 7 0 h'5a write data address: h'ffc00008 (h'1fc00008) 15 8 7 0 h'a5 write data address: h'ffc0000c (h'1fc0000c) wtcsr write wtcnt write figure 10.3 writing to wtcnt and wtcsr
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 285 of 1122 rej09b0370-0400 10.9 using the wdt 10.9.1 standby clearing procedure the wdt is used when clearing standby mode by means of an nmi or other interrupt. the procedure is shown below. (as the wdt does not operate when standby mode is cleared with a reset, the reset pin should be held low until the clock stabilizes.) 1. be sure to clear the tme bit in the wtcsr register to 0 before making a transition to standby mode. if the tme bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. select the count clock to be used with bits cks2?cks0 in the wtcsr register, and set the initial value in the wtcnt counter. make these settings so that the time until the count overflows is at least as long as th e clock oscillation stabilization time. 3. make a transition to standby mode, and stop the clock, by executing a sleep instruction. 4. the wdt starts counting on detection of an nmi signal transition edge or an interrupt. 5. when the wdt count overflows, the cpg st arts clock supply and the processor resumes operation. the wovf flag in the wtcsr register is not set at this time. 6. the counter stops at a value of h'00?h'01. the value at which the counter stops depends on the clock ratio. 10.9.2 frequency changing procedure the wdt is used in a frequency change using the pll. it is not used when the frequency is changed simply by making a frequency divider switch. 1. be sure to clear the tme bit in the wtcsr register to 0 before making a frequency change. if the tme bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. select the count clock to be used with bits cks2?cks0 in the wtcsr register, and set the initial value in the wtcnt counter. make these settings so that the time until the count overflows is at least as long as th e clock oscillation stabilization time. 3. when the frequency control register (frqcr ) is modified, the clock stops. the wdt starts counting. 4. when the wdt count overflows, the cpg st arts clock supply and the processor resumes operation. the wovf flag in the wtcsr register is not set at this time. 5. the counter stops at a value of h'00?h'01. the value at which the counter stops depends on the clock ratio.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 286 of 1122 rej09b0370-0400 6. when re-setting wtcnt immediately after modifying the frequency control register (frqcr), first read the counter and confirm that its value is as described in step 5 above. 10.9.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, select the type of reset with the rsts bit, and the count clock with bits cks2?cks0, and set the initial value in the wtcnt counter. 2. when the tme bit in the wtcsr register is set to 1, the count starts in watchdog timer mode. 3. during operation in watchdog timer mode, write h'00 to the counter periodically so that it does not overflow. 4. when the counter overflows, the wdt sets th e wovf flag in the wtcs r register to 1, and generates a reset of the type specified by the rsts bit. the counter then continues counting. 10.9.4 using interval timer mode when the wdt is operating in interval timer mode , an interval timer interrupt is generated each time the counter overflows. this enables interrupts to be generated at fixed intervals. 1. clear the wt/ it bit in the wtcsr register to 0, select the count clock with bits cks2?cks0, and set the initial value in the wtcnt counter. 2. when the tme bit in the wtcsr register is set to 1, the count starts in interval timer mode. 3. when the counter overflows, the wdt sets th e iovf flag in the wtcsr register to 1, and sends an interval timer interrupt request to intc. the counter continues counting.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 287 of 1122 rej09b0370-0400 10.10 notes on board design when using a crystal resonator: place the crystal resonator and capacitors close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. extal xtal sh7751 sh7751r cl1 cl2 r avoid crossing signal lines recommended values cl1 = cl2 = 0?33 pf r = 0 note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. figure 10.4 points for attention when using crystal resonator when inputting external clock from extal pin: make no connection to the xtal pin.
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 288 of 1122 rej09b0370-0400 when using a pll oscillator circuit: separate vdd ? cpg and vss ? cpg from the other vdd and vss lines at the board power supply source, and insert resistors rcb and rb, and decoupling capacitors cpb and cb, close to the pins. vdd-pll1 cpb1 cpb2 cb rcb1 recommended values rcb1 = rcb2 = 10 cpb1 = cpb2 = 10 f rb = 10 cb = 10 f rcb2 rb power supply (vdd) power supply (vddq) vss-pll1 vdd-pll2 sh7751 sh7751r vss-pll2 vdd-cpg vss-cpg figure 10.5 points for attention when using pll oscillator circuit
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 289 of 1122 rej09b0370-0400 10.11 usage notes 10.11.1 invalid manual reset trigg ered by watchdog timer (sh7751 only) under certain conditions the on-chip watchdog tim er (wdt) may trigger an invalid manual reset. conditions under which problem occurs: the on-chip wdt triggers an invalid manual reset when all of the following four conditions are satisfied. 1. after the wdt overflows, regardless of the values of the wt/ it and rsts bits in wtcsr. 2. before the counter (wtcnt) is incremented by the clock specified by the wtcsr.cks bit. 3. the value of at least one of the tme, wt/ it , and rsts bits in wtcsr is 0. 4. a value of 1 is written to the tme, wt/ it , and rsts bits in wtcsr. workaround: a workaround for this problem is to use software to increment wtcnt before writing 1 to the tme, wt/ it , and rsts bits in wtcsr. specifi c lines of code for this purpose are listed below. example: add the following lines of code before the instructions for writing 1 to the tme, wt/ it , and rsts bits in wtcsr. mov.l #wtcnt,r7 mov.w #h'5a00,r8 mov.w r8,@r7 mov.l #wtcsr,r9 mov.w #h'a580,r10 mov.w r10,@r9 l.oop_wdt: mov.b @r7,r0 cmp/eq #h'00, r0 bt l.oop_wdt
10. clock oscillation circuits rev.4.00 oct. 10, 2008 page 290 of 1122 rej09b0370-0400
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 291 of 1122 rej09b0370-0400 section 11 realtime clock (rtc) 11.1 overview this lsi includes an on-chip realtime clock (rtc) and a 32.768 khz crystal oscillation circuit for use by the rtc. 11.1.1 features the rtc has the following features. ? clock and calendar functions (bcd display) counts seconds, minutes, hours, day- of-week, days, months, and years. ? 1 to 64 hz timer (binary display) the 64 hz counter register indicat es a state of 64 hz to 1 hz within the rtc frequency divider ? start/stop function ? 30-second adjustment function ? alarm interrupts comparison with second, minute, hour, day-of-week, day, month, or year (sh7751r only) can be selected as the alarm interrupt condition ? periodic interrupts an interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected ? carry interrupt carry interrupt function indicating a second counter carry, or a 64 hz counter carry when the 64 hz counter is read ? automatic leap year adjustment
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 292 of 1122 rej09b0370-0400 11.1.2 block diagram figure 11.1 shows a block diagram of the rtc. r64cnt rtcclk 16.384 khz 32.768 khz 128 hz at i pri cui rcr1 rcr2 rcr3 ryrcnt ryrar rmoncnt rwkcnt rdaycnt rhrcnt rmincnt rseccnt rsecar rminar rhrar rdayar rwkar rmonar prescaler rtc crystal oscillation circuit rtc operation control unit reset, stby, etc counter unit interrupt control unit to registers bus interface internal peripheral module bus * * note: * sh7751r only figure 11.1 block diagram of rtc
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 293 of 1122 rej09b0370-0400 11.1.3 pin configuration table 11.1 shows the rtc pins. table 11.1 rtc pins pin name abbreviation i/o function rtc oscillation circuit crystal pin extal2 input connects crystal to rtc oscillation circuit rtc oscillation circuit crystal pin xtal2 output connects crystal to rtc oscillation circuit clock input/clock output tclk i/o external clock input pin/input capture control input pin/rtc output pi n (shared with tmu) dedicated rtc power supply v dd-rtc ? rtc oscillation circuit power supply pin * dedicated rtc gnd pin v ss-rtc ? rtc oscillation circuit gnd pin * note: * power must be supplied to the rtc power su pply pins even when the rtc is not used. 11.1.4 register configuration table 11.2 summarizes the rtc registers. table 11.2 rtc registers initialization name abbrevia- tion r/w power- on reset manual reset standby mode initial value p4 address area 7 address access size 64 hz counter r64cnt r counts counts counts undefined h'ffc80000 h'1fc80000 8 second counter rseccnt r/w counts counts counts undefined h'ffc80004 h'1fc80004 8 minute counter rmincnt r/w counts counts counts undefined h'ffc80008 h'1fc80008 8 hour counter rhrcnt r/w counts counts counts undefined h'ffc8000c h'1fc8000c 8 day-of- week counter rwkcnt r/w counts counts counts undefined h'ffc80010 h'1fc80010 8 day counter rdaycnt r/w counts counts counts undefined h'ffc80014 h'1fc80014 8
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 294 of 1122 rej09b0370-0400 initialization name abbrevia- tion r/w power-on reset manual reset standby mode initial value p4 address area 7 address access size month counter rmoncnt r/w counts counts counts undefined h'ffc80018 h'1fc80018 8 year counter ryrcnt r/w counts counts counts undefined h'ffc8001c h'1fc8001c 16 second alarm register rsecar r/w initialized * 1 held held undefined * 1 h'ffc80020 h'1fc80020 8 minute alarm register rminar r/w initialized * 1 held held undefined * 1 h'ffc80024 h'1fc80024 8 hour alarm register rhrar r/w initialized * 1 held held undefined * 1 h'ffc80028 h'1fc80028 8 day-of- week alarm register rwkar r/w initialized * 1 held held undefined * 1 h'ffc8002c h'1fc8002c 8 day alarm register rdayar r/w initialized * 1 held held undefined * 1 h'ffc80030 h'1fc80030 8 month alarm register rmonar r/w initialized * 1 held held undefined * 1 h'ffc80034 h'1fc80034 8 rtc control register 1 rcr1 r/w initialized initialized held h'00 * 3 h'ffc80038 h'1fc80038 8 rtc control register 2 rcr2 r/w initialized initialized * 2 held h'09 * 4 h'ffc8003c h'1fc8003c 8 rtc control register 3 * 5 rcr3 r/w initialized held held h'00 h'ffc80050 h'1fc80050 8 year alarm register * 5 ryrar r/w held held held undefined h'ffc80054 h'1fc80054 16 notes: 1. the enb bit in eac h register is initialized. 2. bits other than the rtcen bit and start bit are initialized. 3. the value of the cf bit and af bit is undefined. 4. the value of t he pef bit is undefined. 5. sh7751r only
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 295 of 1122 rej09b0370-0400 11.2 register descriptions 11.2.1 64 hz counter (r64cnt) r64cnt is an 8-bit read-only register that indi cates a state of 64 hz to 1 hz within the rtc frequency divider. if this register is read when a carry is generated from the 128 khz frequency division stage, bit 7 (cf) in rtc control register 1 (rcr1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 hz counter read. in this case, the read value is not valid, and so r64cnt must be read again after first writing 0 to the cf bit in rcr1 to clear it. when the reset bit or adj bit in rtc control re gister 2 (rcr2) is set to 1, the rtc frequency divider is initialized and r64cnt is initialized to h'00. r64cnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0 and cannot be modified. bit: 7 6 5 4 3 2 1 0 ? 1 hz 2 hz 4 hz 8 hz 16 hz 32 hz 64 hz initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r r r r r r r
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 296 of 1122 rej09b0370-0400 11.2.2 second counter (rseccnt) rseccnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded second value in the rtc. it counts on the carry (transition of the r69cnt.1hz bit from 0 to 1) generated once per second by the 64 hz counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rseccnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? 10-second units 1-second units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r/w r/w r/w r/w r/w r/w r/w 11.2.3 minute counter (rmincnt) rmincnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded minute value in the rtc. it counts on the carry generated once per minute by the second counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmincnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? 10-minute units 1-minute units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r/w r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 297 of 1122 rej09b0370-0400 11.2.4 hour counter (rhrcnt) rhrcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded hour value in the rtc. it counts on the carry generated once per hour by the minute counter. the setting range is decimal 00 to 23. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rhrcnt is not initialized by a power-on or manual reset, or in standby mode. bits 7 and 6 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? 10-hour units 1-hour units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r r r/w r/w r/w r/w r/w r/w 11.2.5 day-of-week counter (rwkcnt) rwkcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day-of-week value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 0 to 6. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rwkcnt is not initialized by a power-on or manual reset, or in standby mode. bits 7 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? day-of-week code initial value: 0 0 0 0 0 undefined undefined undefined r/w: r r r r r r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 298 of 1122 rej09b0370-0400 day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat 11.2.6 day counter (rdaycnt) rdaycnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 01 to 31. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rdaycnt is not initialized by a power-on or manual reset, or in standby mode. the setting range for rdaycnt depends on the month and whether the year is a leap year, so care is required when making th e setting. taking the year counter (ryrcnt) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. bits 7 and 6 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? 10-day units 1-day units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r r r/w r/w r/w r/w r/w r/w 11.2.7 month counter (rmoncnt) rmoncnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded month value in the rtc. it counts on the carry generated once per month by the day counter. the setting range is decimal 01 to 12. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmoncnt is not initialized by a power-on or manual reset, or in standby mode.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 299 of 1122 rej09b0370-0400 bits 7 to 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? ? 10-month unit 1-month units initial value: 0 0 0 undefined undefined undefined undefined undefined r/w: r r r r/w r/w r/w r/w r/w 11.2.8 year counter (ryrcnt) ryrcnt is a 16-bit readable/writable register us ed as a counter for setting and counting the bcd-coded year value in the rtc. it counts on the carry generated once per year by the month counter. the setting range is decimal 0000 to 9999. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. ryrcnt is not initialized by a power-on or manual reset, or in standby mode. bit: 15 14 13 12 11 10 9 8 1000-year units 100-year units initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 10-year units 1-year units initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 300 of 1122 rej09b0370-0400 11.2.9 second alarm register (rsecar) rsecar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded second value counter, rseccnt. when the enb bi t is set to 1, the rsecar value is compared with the rseccnt value. comparison between th e counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the other fields in rsecar are not initialized by a power-on or ma nual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10-second units 1-second units initial value: 0 undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.2.10 minute alarm register (rminar) rminar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded minute value counter, rmincnt. when the enb bit is set to 1, the rminar value is compared with the rmincnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rminar is initialized by a power-on reset. the other fields in rminar are not initialized by a power-on or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10-minute units 1-minute units initial value: 0 undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 301 of 1122 rej09b0370-0400 11.2.11 hour alarm register (rhrar) rhrar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded hour value counter, rhrcnt. when the enb bit is set to 1, the rhrar value is compared with the rhrcnt value. comparison between the coun ter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 23 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rhrar is initialized by a power-on reset. the other fields in rhrar are not initialized by a power-on or manual reset, or in standby mode. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? 10-hour units 1-hour units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r/w r r/w r/w r/w r/w r/w r/w 11.2.12 day-of-week alarm register (rwkar) rwkar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded day-of-week value counter, rwkcnt. when the enb bit is set to 1, the rwkar value is compared with the rwkcnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 0 to 6 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the other fields in rwkar are not initialized by a power-on or manual reset, or in standby mode.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 302 of 1122 rej09b0370-0400 bits 6 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? ? ? ? day-of-week code initial value: 0 0 0 0 0 undefined undefined undefined r/w: r/w r r r r r/w r/w r/w day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat 11.2.13 day alarm register (rdayar) rdayar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded day value counter, rdaycnt. when the enb bit is set to 1, the rdayar value is compared with the rdaycnt valu e. comparison between the coun ter and the alarm register is performed for those registers among rsec ar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 31 + enb bit. the rtc will not operate normally if any other value is set. the setting range for rdayar depends on the month and whether the year is a leap year, so care is required when making the setting. the enb bit in rdayar is initialized by a power-on reset. the other fields in rdayar are not initialized by a power-on or manual reset, or in standby mode. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? 10-day units 1-day units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r/w r r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 303 of 1122 rej09b0370-0400 11.2.14 month alarm register (rmonar) rmonar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded month value counter, rmoncnt. when the enb bit is set to 1, the rmonar value is compared with the rmoncnt valu e. comparison between the coun ter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 12 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the other fields in rmonar are not initialized by a power-on or manual reset, or in standby mode. bits 6 and 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? ? 10-month unit 1-month units initial value: 0 0 0 undefined undefined undefined undefined undefined r/w: r/w r r r/w r/w r/w r/w r/w 11.2.15 rtc control register 1 (rcr1) rcr1 is an 8-bit readable/writable register contai ning a carry flag and alarm flag, plus flags to enable or disable inte rrupts for these flags. the cie and aie bits are initialized to 0 by a power-on or manual reset; the value of bits other than cie and aie is undefined. in standby mode rcr1 is not initialized, and retains its current value. bit: 7 6 5 4 3 2 1 0 cf ? ? cie aie ? ? af initial value: undefined undefined undefined 0 0 undefined undefined undefined r/w: r/w r r r/w r/w r r r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 304 of 1122 rej09b0370-0400 bit 7?carry flag (cf): this flag is set to 1 on generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read. the count register value read at this time is not guaranteed, and so the count regi ster must be read again. bit 7: cf description 0 no second counter carry, or 64 hz counter carry when 64 hz counter is read [clearing condition] when 0 is written to cf 1 second counter carry, or 64 hz counter carry when 64 hz counter is read [setting conditions] ? generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read ? when 1 is written to cf bit 4?carry interrupt enable flag (cie): enables or disables interrupt generation when the carry flag (cf) is set to 1. bit 4: cie description 0 carry interrupt is not generated when cf flag is set to 1 (initial value) 1 carry interrupt is generated when cf flag is set to 1 bit 3?alarm interrupt enable flag (aie): enables or disables interrupt generation when the alarm flag (af) is set to 1. bit 3: aie description 0 alarm interrupt is not generated when af flag is set to 1 (initial value) 1 alarm interrupt is generated when af flag is set to 1
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 305 of 1122 rej09b0370-0400 bit 0?alarm flag (af): set to 1 when the alarm time set in those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1 matches the respective counter values. bit 0: af description 0 alarm registers and counter values do not match (initial value) [clearing condition] when 0 is written to af 1 alarm registers and counter values match * [setting condition] when alarm registers in which the enb bit is set to 1 and counter values match * note: * writing 1 does not change the value. bits 6, 5, 2, and 1?reserved. the initial value of these bits is undefined. a write to these bits is invalid, but the write value should always be 0. 11.2.16 rtc control register 2 (rcr2) rcr2 is an 8-bit readable/writable register us ed for periodic interrupt control, 30-second adjustment, and frequency divider reset and rtc count control. rcr2 is basically initialized to h'09 by a power-on reset, except that the value of the pef bit is undefined. in a manual reset, bits other than rtcen and start are initialized, while the value of the pef bit is undefined. in standby mode rcr2 is not initialized, and retains its current value. bit: 7 6 5 4 3 2 1 0 pef pes2 pes1 pes0 rtcen adj reset start initial value: undefined 0 0 0 1 0 0 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 306 of 1122 rej09b0370-0400 bit 7?periodic interrupt flag (pef): indicates interrupt generation at the interval specified by bits pes2?pes0. when this flag is set to 1, a periodic interrupt is generated. bit 7: pef description 0 interrupt is not gener ated at interval specified by bits pes2?pes0 [clearing condition] when 0 is written to pef 1 interrupt is generated at interv al specified by bits pes2?pes0 [setting conditions] ? generation of interrupt at interv al specified by bits pes2?pes0 ? when 1 is written to pef bits 6 to 4?periodic int errupt enable (pes2?pes0): these bits specify the period for periodic interrupts. bit 6: pes2 bit 5: pes1 bit 4: pes0 description 0 0 0 no periodic interrupt generation (initial value) 1 periodic interrupt generated at 1/256-second intervals 1 0 periodic interrupt generated at 1/64-second intervals 1 periodic interrupt generated at 1/16-second intervals 1 0 0 periodic interrupt generated at 1/4-second intervals 1 periodic interrupt generated at 1/2-second intervals 1 0 periodic interrupt generated at 1-second intervals 1 periodic interrupt generated at 2-second intervals bit 3?oscillation circuit enable (rtcen): controls the operation of the rtc crystal oscillation circuit. bit 3: rtcen description 0 rtc crystal oscillation circuit halted 1 rtc crystal oscillation circuit operating (initial value)
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 307 of 1122 rej09b0370-0400 bit 2?30-second adjustment (adj): used for 30-second adjustment. when 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. the frequency divider circuits (rtc prescaler and r64cnt) are also reset at this time. this bit always returns 0 if read. bit 2: adj description 0 normal clock operation (initial value) 1 30-second adjustment performed bit 1?reset (reset): the frequency divider circuits are initialized by writing 1 to this bit. when 1 is written to the reset bit, the frequency divider circuits (rtc prescaler and r64cnt) are reset and the reset bit is auto matically cleared to 0 (i.e. does not need to be written with 0). bit 1: reset description 0 normal clock operation (initial value) 1 frequency divider circuits are reset bit 0?start bit (start): stops and restarts coun ter (clock) operation. bit 0: start description 0 second, minute, hour, day, day-of-w eek, month, and year counters are stopped * 1 second, minute, hour, day, day-of-week , month, and year counters operate normally * (initial value) note: * the 64 hz counter continues to operate unless stopped by means of the rtcen bit.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 308 of 1122 rej09b0370-0400 11.2.17 rtc control register (rcr3) and year-alarm register (ryrar) (sh7751r only) rcr3 and ryrar are readab le/writable registers. ryrar is the alarm register for the rtc's bcd-coded year-value counter ryrcnt. when the yenb bit of rcr3 is set to 1, the ryrcnt value is compared with the ryra r value. comparison between the counter and the alarm register only takes place with the alarm registers in which the enb and yenb bits are set to 1. the alarm flag of rcr1 is only set to 1 when the respective values all match. the setting range of ryrar is decimal 0000 to 9999, and normal operation is not obtained if a value beyond this range is set here. rcr3 is initialized by a power-on reset, but ryrar will not be initialized by a power-on or manual reset, or by the device entering standby mode. bits 6 to 0 of rcr3 are always read as 0. a write to these bits is invalid. if a value is written to these bits, it should always be 0. rcr3 bit: 7 6 5 4 3 2 1 0 yenb ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r r r ryrar bit: 15 14 13 12 11 10 9 8 1000 years 100 years initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 10 years 1 year initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 309 of 1122 rej09b0370-0400 11.3 operation examples of the use of the rtc are shown below. 11.3.1 time setting procedures figure 11.2 shows examples of the time setting procedures. stop clock reset frequency divider set second/minute/hour/day/ day-of-week/month/year start clock operation set rcr2.reset to 1 clear rcr2.start to 0 in any order set rcr2.start to 1 (a) settin g time after stoppin g clock clear carry fla g write to counter re g ister carry fla g = 1? no ye s clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) set ryrcnt first and rseccnt last read rcr1 re g ister and check cf bit (b) settin g time while clock is runnin g figure 11.2 examples of time setting procedures the procedure for setting the time after stopping the clock is shown in figure 11.2 (a). the programming for this method is simple, and it is useful for setting all the counters, from second to year.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 310 of 1122 rej09b0370-0400 the procedure for setting the time while the clock is running is shown in figure 11.2 (b). this method is useful for modifying only certain counter values (for example, only the second data or hour data). if a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. the carry flag should therefore be used to check the write status. if the carry flag ( rcr1.cf) is set to 1, the write must be repeated. the interrupt function can also be used to determine the carry flag status.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 311 of 1122 rej09b0370-0400 11.3.2 time reading procedures figure 11.3 shows examples of the time reading procedures. disable carry interrupts clear carry fla g read counter re g ister carry fla g = 1? clear rcr1.cie to 0 clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) read rcr1 re g ister and check cf bit (a) readin g time without usin g interrupts no ye s clear carry fla g enable carry interrupts clear carry fla g read counter re g ister interrupt g enerated? ye s disable carry interrupts no (b) readin g time usin g interrupts set rcr1.cie to 1 clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) clear rcr1.cie to 0 figure 11.3 examples of time reading procedures if a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. the procedure for reading the time without using interrupts is shown in figure
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 312 of 1122 rej09b0370-0400 11.3 (a), and the procedure using carry interrupts in figure 11.3 (b). the method without using interrupts is normally used to keep the program simple. 11.3.3 alarm function the use of the alarm function is illustrated in figure 11.4. clock runnin g disable alarm interrupts set alarm time clear alarm fla g enable alarm interrupts monitor alarm time (wait for interrupt or check alarm fla g ) clear rcr1.aie to prevent erroneous interrupts be sure to reset the fla g as it may have been set durin g alarm time settin g set rcr1.aie to 1 figure 11.4 example of use of alarm function an alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (sh7751r only) value, or a combination of these. write 1 to the enb bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits. write 0 to the enb bit in registers not involved in the alarm setting. when the counter and the alarm time match, rcr1.af is set to 1. alarm detection can be confirmed by reading this bit, but normally an interrupt is used. if 1 has been written to rcr1.aie, an alarm interrupt is generated in th e event of alarm, enabling the alarm to be detected. the alarm flag remains set while the counter and al arm time match. if the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. this needs to be taken into consideration when writing the program.
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 313 of 1122 rej09b0370-0400 11.4 interrupts there are three kinds of rtc inte rrupt: alarm interrupts, periodic interrupts, and carry interrupts. an alarm interrupt request (ati) is generated when the alarm flag (af) in rcr1 is set to 1 while the alarm interrupt enable bit (aie) is also set to 1. a periodic interrupt request (pri) is generated when the periodic interrupt enable bits (pes2? pes0) in rcr2 are set to a value other than 000 and the periodic interrupt flag (pef) is set to 1. a carry interrupt request (cui) is generated when the carry flag (cf) in rcr1 is set to 1 while the carry interrupt enable bit (cie) is also set to 1. 11.5 usage notes 11.5.1 register initialization after powering on and making the rcr1 register settings, reset the frequency divider (by setting rcr2.reset to 1) and make initial se ttings for all the other registers. 11.5.2 carry flag and interru pt flag in standby mode when the carry flag or interrupt flag is set to 1 at the same time this lsi transits to normal mode from standby mode by a reset or interrupt, the flag may not be set to 1. after exiting standby mode, check the counters to judge the flag states if necessary. 11.5.3 crystal oscillation circuit crystal oscillation circuit constants (recommended values) are shown in table 11.3, and the rtc crystal oscillation circuit in figure 11.5. table 11.3 crystal oscillation circu it constants (recommended values) f osc c in c out 32.768 khz 10?22 pf 10?22 pf
11. realtime clock (rtc) rev.4.00 oct. 10, 2008 page 314 of 1122 rej09b0370-0400 this lsi extal2 xtal2 xtal c in c out r f r d noise filter c rtc r rtc 3.3 v vdd-rtc vss-rtc notes: 1. select either the c in or c out side for the frequency adjustment variable capacitor accordin g to requirements such as the adjustment ran g e, de g ree of stability, etc. 2. built-in resistance value r f (typ. value) = 10 m , r d (typ. value) = 400 k 3. c in and c out values include floatin g capacitance due to the wirin g . take care when usin g a solid- earth board. 4. the crystal oscillation stabilization time depends on the mounted circuit constants, floatin g capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2 and xtal2) wirin g is routed as far away as possible from other power lines (except gnd) and si g nal lines. 7. insert a noise filter in the rtc power supply. figure 11.5 example of crysta l oscillation circuit connection
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 315 of 1122 rej09b0370-0400 section 12 timer unit (tmu) 12.1 overview this lsi includes an on-chip 32-bit timer unit (tmu) comprising five 32-bit timer channels (channels 0 to 4). 12.1.1 features the tmu has the following features. ? auto-reload type 32-bit down-coun ter provided for each channel ? input capture function provided in channel 2 ? selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used ? 32-bit timer constant register for auto-reload us e, readable/writable at any time, and 32-bit down-counter provided for each channel ? selection of seven counter input clocks for channels 0 to 2 external clock (tclk), on-chip rtc output clock, five internal clocks (pck/4, pck/16, pck/64, pck/256, pck/1024) (pck is the peripheral module clock) ? selection of five internal clocks for channels 3 and 4 ? channels 0 to 2 can also operate in module standby mode when the on-chip rtc output clock is selected as the counter input clock; that is , timer operation continues even when the clock has been stopped for the tmu. timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit. ? two interrupt sources one underflow source (channels 0 to 4) and one input capture source (channel 2) ? dmac data transfer request capability on channel 2, a data transfer request is sent to the dmac when an input capture interrupt is generated.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 316 of 1122 rej09b0370-0400 12.1.2 block diagram figure 12.1 shows a block diagram of the tmu. reset, stby, etc. tuni0,1 pck/4, 16, 64 * tuni2 ticpi2 tclk rtcclk tuni3, tuni4 tocr tstr tstr2 tcnt tcor tcr tcpr2 tcnt2 tcor2 tcr2 tcnt tcor tcr bus interface internal peripheral module bus note: * signals with 1/4, 1/16, and 1/64 the pck frequency, supplied to the on-chip peripheral functions. counter unit interrupt control unit counter unit interrupt control unit counter unit interrupt control unit ch 0,1 ch 2 ch 3,4 tmu operation control unit prescaler tclk control unit to chan- nels 0 to 4 to chan- nels 0 to 2 figure 12.1 block diagram of tmu 12.1.3 pin configuration table 12.1 shows the tmu pins. table 12.1 tmu pins pin name abbreviation i/o function clock input/clock output tclk i/o exter nal clock input pin/input capture control input pin/rtc output pin (shared with rtc)
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 317 of 1122 rej09b0370-0400 12.1.4 register configuration table 12.2 summarizes the tmu registers. table 12.2 tmu registers initialization chan- nel name abbre- viation r/w power- on reset manual reset stand- by mode initial value p4 address area 7 address access size com- mon timer output control register tocr r/w ini- tialized ini- tialized held h'00 h'ffd80000 h'1fd80000 8 timer start register tstr r/w ini- tialized ini- tialized ini- tialized * 1 h'00 h'ffd80004 h'1fd80004 8 timer start register 2 tstr2 r/w ini- tialized held held h'00 h'fe100004 h'1e100004 8 0 timer constant register 0 tcor0 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80008 h'1fd80008 32 timer counter 0 tcnt0 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd8000c h'1fd8000c 32 timer control register 0 tcr0 r/w ini- tialized ini- tialized held h'0000 h'ffd80010 h'1fd80010 16 1 timer constant register 1 tcor1 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80014 h'1fd80014 32 timer counter 1 tcnt1 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd80018 h'1fd80018 32 timer control register 1 tcr1 r/w ini- tialized ini- tialized held h'0000 h'ffd8001c h'1fd8001c 16 2 timer constant register 2 tcor2 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80020 h'1fd80020 32 timer counter 2 tcnt2 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd80024 h'1fd80024 32 timer control register 2 tcr2 r/w ini- tialized ini- tialized held h'0000 h'ffd80028 h'1fd80028 16 input capture register tcpr2 r held held held undefined h'ffd8002c h'1fd8002c 32
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 318 of 1122 rej09b0370-0400 initialization chan- nel name abbre- viation r/w power- on reset manual reset stand- by mode initial value p4 address area 7 address access size 3 timer constant register 3 tcor3 r/w ini- tialized held held h'ffffffff h'fe100008 h'1e100008 32 timer counter 3 tcnt3 r/w ini- tialized held held h'ffffffff h'fe10000c h'1e10000c 32 timer control register 3 tcr3 r/w ini- tialized held held h'0000 h'fe100010 h'1e100010 16 4 timer constant register 4 tcor4 r/w ini- tialized held held h'ffffffff h'fe100014 h'1e100014 32 timer counter 4 tcnt4 r/w ini- tialized held held h'ffffffff h'fe100018 h'1e100018 32 timer control register 4 tcr4 r/w ini- tialized held held h'0000 h'fe10001c h'1e10001c 16 notes: 1. not initialized in module standby mode when the input clock is the on-chip rtc output clock. 2. counts in module standby mode when the in put clock is the on-chip rtc output clock. 12.2 register descriptions 12.2.1 timer output co ntrol register (tocr) tocr is an 8-bit readable/writable register that specifies whether external pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. tocr is initialized to h'00 by a power-on or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? tcoe initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 7 to 1?reserved: these bits are always read as 0. a wr ite to these bits is invalid, but the write value should always be 0.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 319 of 1122 rej09b0370-0400 bit 0?timer clock pin control (tcoe): specifies whether timer cloc k pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. bit 0: tcoe description 0 timer clock pin (tclk) is used as external clock input or input capture control input pin (initial value) 1 timer clock pin (tclk) is used as on-chip rtc output clock output pin * note: * low-level output in standby mode; high- impedance output in hardware standby mode. 12.2.2 timer start register (tstr) tstr is an 8-bit readable/writable register that specifies whether the channel 0?2 timer counters (tcnt) are operated or stopped. tstr is initialized to h'00 by a power-on or manual reset. in module standby mode, tstr is not initialized when the input clock selected by each channel is the on-c hip rtc output clock (rtcclk), and is initialized only when the input cl ock is the external clock (tclk) or internal clock (pck). bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? str2 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 3?reserved: these bits are always read as 0. a wr ite to these bits is invalid, but the write value should always be 0. bit 2?counter start 2 (str2): specifies whether timer counter 2 (tcnt2) is operated or stopped. bit 2: str2 description 0 tcnt2 count operation is stopped (initial value) 1 tcnt2 performs count operation
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 320 of 1122 rej09b0370-0400 bit 1?counter start 1 (str1): specifies whether timer counter 1 (tcnt1) is operated or stopped. bit 1: str1 description 0 tcnt1 count operation is stopped (initial value) 1 tcnt1 performs count operation bit 0?counter start 0 (str0): specifies whether timer counter 0 (tcnt0) is operated or stopped. bit 0: str0 description 0 tcnt0 count operation is stopped (initial value) 1 tcnt0 performs count operation 12.2.3 timer start register 2 (tstr2) tstr2 is an 8-bit readable/writable register th at specifies whether the channel 3 and 4 timer counters (tcnt) are operated or stopped. tstr2 is initialized to h'00 by a power-on reset. tstr retain their contents in standby mode. when standby mode is entered when the value of either str3 or str4 is 1, the count halts when the peripheral module clock stops and restarts when the clock supply is resumed. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? str4 str3 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bits 7 to 2?reserved: these bits are always read as 0. a wr ite to these bits is invalid, but the write value should always be 0. bit 1?counter start 4 (str4): specifies whether timer counter 4 (tcnt4) is operated or stopped. bit 1: str4 description 0 tcnt4 count operation is stopped (initial value) 1 tcnt4 performs count operation
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 321 of 1122 rej09b0370-0400 bit 0?counter start 3 (str3): specifies whether timer counter 3 (tcnt3) is operated or stopped. bit 0: str3 description 0 tcnt3 count operation is stopped (initial value) 1 tcnt3 performs count operation 12.2.4 timer constant registers (tcor) the tcor registers are 32-bit read able/writable registers. there are five tcor registers, one for each channel. when a tcnt counter underflows while counting down, the tcor value is set in that tcnt, which continues counting down from the set value. the tcor registers in channels 0 to 2 are in itialized to h'ffffffff by a power-on or manual reset, but are not initialized and retain their contents in standby mode. the tcor registers in channels 3 and 4 are init ialized to h'ffffffff by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode. bit: 31 30 29 2 1 0 initial value: 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w 12.2.5 timer counters (tcnt) the tcnt registers are 32-bit read able/writable registers. there are five tcnt registers, one for each channel. each tcnt counts down on the input clock sel ected by tpsc2?tpsc0 in the timer control register (tcr). when a tcnt counter underflows while counting down, the underflow flag (unf) is set in the corresponding timer contro l register (tcr). at the same time, the timer constant register (tcor) value is set in tcnt, and the count-down operation continues from the set value. the tcnt registers in channels 0 to 2 are in itialized to h'ffffffff by a power-on or manual reset, but are not initialized and retain their contents in standby mode.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 322 of 1122 rej09b0370-0400 the tcnt registers in channels 3 and 4 are in itialized to h'ffffffff by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode. bit: 31 30 29 2 1 0 initial value: 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w in channels 0 to 2, when the input clock is the on-chip rtc output clock (rtcclk), tcnt counts even in module standby mode (that is, when the clock for the tmu is stopped). when the input clock is the external clock (tclk) or intern al clock (pck), tcnt contents are retained in standby mode. 12.2.6 timer control registers (tcr) the tcr registers are 16-bit readab le/writable registers. there are five tcr registers, one for each channel. each tcr selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (tcnt) underflow is set to 1. tcr2 is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture. the tcr registers in channels 0 to 2 are initialized to h'0000 by a power-on or manual reset, but are not initialized in standby mode. the tcr registers in channels 3 and 4 are initialized to h'0000 by a power-on reset, but are not initialized by a manual reset or in standby mode.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 323 of 1122 rej09b0370-0400 1. channel 0 and 1 tcr bit configuration bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w 2. channel 2 tcr bit configuration bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? icpf unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 3. channel 3 and 4 tcr bit configuration bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? unie ? ? tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r r r/w r/w r/w
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 324 of 1122 rej09b0370-0400 bits 15 to 9, 7, and 6 (channels 0 and 1); bits 15 to 10 (channel 2)?reserved: these bits are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit 9?input capture interrupt flag (icpf) (channel 2 only): status flag, provided in channel 2 only, that indicates th e occurrence of input capture. bit 9: icpf description 0 input capture has not occurred (initial value) [clearing condition] when 0 is written to icpf 1 input capture has occurred [setting condition] when input capture occurs * note: * writing 1 does not change the value. bit 8?underflow flag (unf): status flag that indicates the occurrence of underflow. bit 8: unf description 0 tcnt has not underflowed (initial value) [clearing condition] when 0 is written to unf 1 tcnt has underflowed [setting condition] when tcnt underflows * note: * writing 1 does not change the value. bits 7 and 6?input capture control (icpe1, icpe0) (channel 2 only): these bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. when the input capture function is used, a data transfer request is sent to the dmac in the event of input capture. when using the input capture function, the tclk pin must be designated as an input pin with the tcoe bit in the tocr register. the ckeg bits specify whether the rising edge or falling edge of the tclk signal is used to set the tcnt2 value in the input capture register (tcpr2).
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 325 of 1122 rej09b0370-0400 the tcnt2 value is set in tcpr2 only when the tcr2.icpf bit is 0. when the tcr2.icpf bit is 1, tcpr2 is not set in the event of input captur e. when input capture oc curs, a dmac transfer request is generated regardless of the value of the tcr2.icpf bit. however, a new dmac transfer request is not generated until proces sing of the previous request is finished. bit 7: icpe1 bit 6: icpe0 description 0 0 input capture function is not used (initial value) 1 reserved (do not set) 1 0 input capture function is used, but interrupt due to input capture (ticpi2) is not enabled data transfer request is sent to dmac in the event of input capture 1 input capture function is used, and interrupt due to input capture (ticpi2) is enabled data transfer request is sent to dmac in the event of input capture bit 5?underflow interrupt control (unie): controls enabling or disabling of interrupt generation when the unf status flag is set to 1, indicating tcnt underflow. bit 5: unie description 0 interrupt due to underflow (tuni) is not enabled (initial value) 1 interrupt due to underflow (tuni) is enabled bits 4 and 3?clock edge 1 and 0 (ckeg1, ckeg0): in channels 0 to 2, these bits select the external clock input edge when an external clock is selected or th e input capture function is used. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count/input capture register set on rising edge (initial value) 1 count/input capture register set on falling edge 1 x count/input capture register set on both rising and falling edges note: x: 0 or 1 (don't care)
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 326 of 1122 rej09b0370-0400 bits 2 to 0?timer prescaler 2 to 0 (tpsc2?tpsc0): in channels 0 to 2, these bits select the tcnt count clock. when the on-chip rtc output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. when another clock is selected, the channel does not operate in standby mode. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 counts on pck/4 (initial value) 1 counts on pck/16 1 0 counts on pck/64 1 counts on pck/256 1 0 0 counts on pck/1024 1 reserved (do not set) 1 0 counts on on-chip rtc output clock (do not set in channels 3 and 4) 1 counts on external clock (do not set in channels 3 and 4) 12.2.7 input captur e register 2 (tcpr2) tcpr2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. the input capture function is controlled by means of the input capture control bits (icpe1, icpe0) and clock edge bits (ckeg1, ckeg0) in tcr2. when input capture occurs, the tcnt2 value is copied into tcpr2. the value is set in tcpr2 only when the icpf bit in tcr2 is 0. tcpr2 is not initialized by a power-on or manual reset, or in standby mode. bit: 31 30 29 2 1 0 initial value: undefined r/w: r r r r r r
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 327 of 1122 rej09b0370-0400 12.3 operation each channel has a 32-bit timer counter (tcnt) th at performs count-down operations, and a 32- bit timer constant register (tcor). the channels have an auto-reload function that allows cyclic count operations, and can also pe rform external event counting. channel 2 also has an input capture function. 12.3.1 counter operation when one of bits str0?str4 is set to 1 in the timer start register (tstr, tstr2), the timer counter (tcnt) for the corresponding channel starts counting. when tcnt underflows, the unf flag is set in the corresponding timer control register (tcr). if the unie bit in tcr is set to 1 at this time, an interrupt request is sent to the cpu. at the same time, the value is copied from tcor into tcnt, and the count-down continues (auto-reload function). example of count operation setting procedure: figure 12.2 shows an example of the count operation setting procedure. 1. select the count clock with bits tpsc2?tpsc0 in the timer control register (tcr). when an external clock in channels 0 to 2 is selected, set the tclk pin to input mode with the tcoe bit in tocr, and select the external clock edge with bits ckeg1 and ckeg0 in tcr. 2. specify whether an interrupt is to be generated on tcnt underflow with the unie bit in tcr. 3. when the input capture function is used, set the icpe bits in tcr, including specification of whether the interrupt function is to be used. 4. set a value in the timer constant register (tcor). 5. set the initial value in the timer counter (tcnt). 6. set the str bit to 1 in the timer start re gister (tstr, tstr2) to start the count.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 328 of 1122 rej09b0370-0400 1 2 operation selection select count clock underflow interrupt g eneration settin g when input capture function is used 3 4 5 6 input capture interrupt g eneration settin g timer constant re g ister settin g set initial timer counter value start count note: when an interrupt is g enerated, clear the source fla g in the interrupt handler. if the interrupt enabled state is set without clearin g the fla g , another interrupt will be g enerated. figure 12.2 example of coun t operation setting procedure
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 329 of 1122 rej09b0370-0400 auto-reload count operation: figure 12.3 shows the tcnt auto-reload operation. tcor h'00000000 str0?str4 unf tcnt value tcor value set in tcnt on underflow time figure 12.3 tcnt auto-reload operation tcnt count timing: ? operating on internal clock any of five count clocks (pck/4, pck/16, pck/64, pck/256, or pck/1024) scaled from the peripheral module clock can be selected as the count clock by means of the tpsc2?tpsc0 bits in tcr. figure 12.4 shows the timing in this case. pck internal clock tcnt n + 1 n n ? 1 figure 12.4 count timing when operating on internal clock
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 330 of 1122 rej09b0370-0400 ? operating on external clock in channels 0 to 2, external clock pin (tclk) input can be selected as the timer clock by means of the tpsc2?tpsc0 bits in tcr. the detected edge (rising, falling, or both edges) can be selected with the ckeg1 and ckeg0 bits in tcr. figure 12.5 shows the timing for both-edge detection. n + 1 n ? 1 n pck external clock input pin tcnt figure 12.5 count timing when operating on external clock ? operating on on-chip rtc output clock in channels 0 to 2, the on-chip rtc output clock can be selected as the timer clock by means of the tpsc2?tpsc0 bits in tcr. figure 12.6 shows the timing in this case. n + 1 n n ? 1 rtc output clock tcnt figure 12.6 count timing when op erating on on-chip rtc output clock 12.3.2 input ca pture function channel 2 has an input capture function. the procedure for using the input capture function is as follows: 1. use the tcoe bit in the timer output control register (tocr) to set the tclk pin to input mode. 2. use bits tpsc2?tpsc0 in the timer control register (tcr) to set an internal clock or the on- chip rtc output clock as the timer operating clock. 3. use bits ipce1 and ipce0 in tcr to specify use of the input capture function, and whether interrupts are to generated when this function is used.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 331 of 1122 rej09b0370-0400 4. use bits ckeg1 and ckeg0 in tcr to specify whether the rising or falling edge of the tclk signal is to be used to set the timer count er (tcnt) value in the input capture register (tcpr2). this function cannot be used in standby mode. when input capture occurs, the tcnt2 value is set in tcpr2 only when the icpf bit in tcr2 is 0. also, a new dmac transfer request is not generated until processing of the previous request is finished. figure 12.7 shows the operation timing when the input capture function is used (with tclk rising edge detection). tcor h'00000000 tclk tcpr2 ticpi2 tcnt value tcor value set in tcnt on underflow tcnt value set time figure 12.7 operation timing wh en using input capture function
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 332 of 1122 rej09b0370-0400 12.4 interrupts there are six tmu interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). underflow interrupts are generated on channels 0 to 4, and input capture interrupts on channel 2 only. an underflow interrupt request is generated (on an individual channel basis) when tcr.unf = 1 and the channel's interrupt enable bit is 1. when the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (icpf) in tcr2 is 1 and the input capture control bits (icpe1, icpe0) in tcr2 are 11. the tmu interrupt sources ar e summarized in table 12.3. table 12.3 tmu interrupt sources channel interrupt source description 0 tuni0 underflow interrupt 0 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 ticpi2 input capture interrupt 2 3 tuni3 underflow interrupt 3 4 tuni4 underflow interrupt 4 12.5 usage notes 12.5.1 register writes when performing a tmu register write, timer count operation must be stopped by clearing the start bit (str0?str4) for the relevant channel in the timer start regi ster (tstr, tstr2). note that the timer start register (tstr, tstr2) can be written to, and the underflow flag (unf) and input capture flag (icpf) of the timer contro l registers (trcr0 to tcr4) can be cleared while the count is in progress. when the flags (unf and icpf) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 333 of 1122 rej09b0370-0400 12.5.2 tcnt register reads when performing a tcnt register read, processing for synchronization with the timer count operation is performed. if a timer count operation and register read processing are performed simultaneously, the tcnt counter value prior to the count-down operation is read by means of the synchronization processing. 12.5.3 resetting the rtc frequency divider when the on-chip rtc output clock is selected as the count clock, the rtc frequency divider should be reset. 12.5.4 external clock frequency ensure that the external clock frequency for any channel does not exceed pck/8.
12. timer unit (tmu) rev.4.00 oct. 10, 2008 page 334 of 1122 rej09b0370-0400
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 335 of 1122 rej09b0370-0400 section 13 bus state controller (bsc) 13.1 overview the functions of the bus state co ntroller (bsc) include division of the external me mory space, and output of control signals in accordance with various types of me mory and bus interface specifications. the bsc functions allow dram, synchronous dram, sram, rom, etc., to be connected to this lsi and also support the pcmcia interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system. 13.1.1 features the bsc has the following features: ? external memory space is managed as 7 independent areas ? maximum 64 mbytes for each of areas 0 to 6 ? bus width of each area can be set in a register (except area 0, which uses an external pin setting) ? wait state insertion by rdy pin ? wait state insertion can be controlled by program ? specification of types of memo ry connectable to each area ? output the control signals of memory to each area ? automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas , or a read access followed by a write access to the same area ? write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to lo w-speed memory ? sram interface ? wait state insertion can be controlled by program ? wait state insertion by rdy pin connectable areas: 0 to 6 settable bus widths: 32, 16, 8 ? dram interface ? row address/column address multiplexing according to dram capacity ? burst operation (fast page mode, edo mode) ? cas-before-ras refresh and self-refresh ? 4-cas byte control for power-down operation
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 336 of 1122 rej09b0370-0400 ? dram control signal timing can be controlled by register settings ? consecutive accesses to the same row address connectable area: 3 settable bus widths: 32, 16 ? synchronous dram interface ? row address/column address multiplexing according to synchronous dram capacity ? burst operation ? auto-refresh and self-refresh ? synchronous dram control signal timing can be controlled by register settings ? consecutive accesses to the same row address connectable areas: 2, 3 settable bus widths: 32 ? burst rom interface ? wait state insertion can be controlled by program ? burst operation, executin g the number of transfers set in a register connectable areas: 0, 5, 6 settable bus widths: 32, 16, 8 ? mpx interface ? address/data multiplexing connectable areas: 0 to 6 settable bus widths: 32 ? byte control sram interface ? sram interface with byte control connectable areas: 1, 4 settable bus widths: 32, 16 ? pcmcia interface ? wait state insertion can be controlled by program ? bus sizing function for i/o bus width ? fine refreshing control ? supports refresh operation immediately after self-refresh operation in low-power dram by means of refresh counter overflow interrupt function ? refresh counter can be used as interval timer ? interrupt request generated by compare-match ? interrupt request generated by refresh counter overflow
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 337 of 1122 rej09b0370-0400 13.1.2 block diagram figure 13.1 shows a block diagram of the bsc. cs6 ? cs0 ce2a ? ce2b bs rd rd/ wr we3 ? we0 ras cass , casxx cke iciord , iciowr reg iois16 internal bus bus interface wcr1 rtcnt rtcor rtcsr comparator refresh control unit memory control unit area control unit wait control unit interrupt controller bsc peripheral bus le g end: wcr: wait control re g ister bcr: bus control re g ister mcr: memory control re g ister pcr: pcmcia control re g ister note: * sh7751r only wcr2 wcr3 bcr1 bcr2 bcr3 * bcr4 * pcr rfcr mcr rdy module bus rfcr: refresh count re g ister rtcnt: refresh timer count re g ister rtcor: refresh time constant re g ister rtcsr: refresh timer control/status re g ister figure 13.1 block diagram of bsc
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 338 of 1122 rej09b0370-0400 13.1.3 pin configuration table 13.1 shows the bsc pin configuration. table 13.1 bsc pins name signals i/o description address bus a25 ? a0 o address output data bus d31 ? d0 i/o data input/output bus cycle start bs o signal that indicates the start of a bus cycle when setting synchronous dram interface or mpx interface: asserted once for a burst transfer for other burst transfers: asserted each data cycle chip select 6?0 cs6 ? cs0 o chip select signals that indicate the area being accessed cs5 and cs6 are also used as pcmcia ce1a and ce1b read/write rd/ wr o data bus input/output direction designation signal also used as the dram/synchronous dram/pcmcia interface write designation signal row address strobe ras o ras signal when setting dram/synchronous dram interface read/column address strobe/ cycle frame rd / cass / frame o strobe signal that indicates a read cycle when setting synchronous dram interface: cas signal when setting mpx interface: frame signal data enable 0 we0 / reg o when setting pcmcia interface: reg signal when setting sram interface: write strobe signal for d7?d0 data enable 1 we1 o when setting pcmcia interface: write strobe signal when setting sram interface: write strobe signal for d15?d8 data enable 2 we2 / iciord o when setting pcmcia interface: iciord signal when setting sram interface: write strobe signal for d23?d16 data enable 3 we3 / iciowr o when setting pcmcia interface: iciowr signal when setting sram interface: write strobe signal for d31?d24
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 339 of 1122 rej09b0370-0400 name signals i/o description column address strobe 0 cas0 /dqm0 o when setting dram interface: cas signal for d7?d0 when setting synchronous dram interface: selection signal for d7?d0 column address strobe 1 cas1 /dqm1 o when setting dram interface: cas signal for d15?d8 when setting synchronous dram interface: selection signal for d15?d8 column address strobe 2 cas2 /dqm2 o when setting dram interface: cas signal for d23?d16 when setting synchronous dram interface: selection signal for d23?d16 column address strobe 3 cas3 /dqm3 o when setting dram interface: cas signal for d31?d24 when setting synchronous dram interface: selection signal for d31?d24 ready rdy i wait state request signal area 0 mpx interface specification/ 16-bit i/o md6/ iois16 i in power-on reset: designates area 0 bus as mpx interface (1: sram, 0: mpx) when setting pcmcia interface: 16-bit i/o designation signal. valid only in little-endian mode. clock enable cke o synchronous dram clock enable control signal bus release request breq / bsack i bus release request signal/bus acknowledge signal bus use permission back / bsreq o bus use permission signal/bus request area 0 bus width/pcmcia card select md3/ ce2a * 1 md4/ ce2b * 2 i/o in power-on reset: area 0 bus width specification signal when using pcmcia: ce2a , ce2b endian switchover md5 i endian specification in a power-on reset master/slave switchover md7/ cts2 i/o indicates master/slave status in a power-on reset serial interface cts2 dmac0 acknowledge signal dack0 o dmac channel 0 data acknowledge dmac1 acknowledge signal dack1 o dmac channel 1 data acknowledge
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 340 of 1122 rej09b0370-0400 notes: 1. md3/ ce2a input/output switching is performed by bcr1.a56pcm. output is selected when bcr1.a56pcm = 1. 2. md4/ ce2b input/output switching is performed by bcr1.a56pcm. output is selected when bcr1.a56pcm = 1. 13.1.4 register configuration the bsc has the 11 registers shown in table 13.2. in addition, the synchronous dram mode register incorporated in synchronous dram can also be accessed as this lsi register. the functions of these registers include control of interfaces to various types of memory, wait states, and refreshing. table 13.2 bsc registers name abbrevia- tion r/w initial value p4 address area 7 address access size bus control register 1 bcr1 r/ w h'0000 0000 h'ff80 0000 h'1f80 0000 32 bus control register 2 bcr2 r/ w h'3ffc h'ff80 0004 h'1f80 0004 16 bus control register 3 * 2 bcr3 r/w h'0001 h 'ff80 0050 h'1f80 0050 16 bus control register 4 * 2 bcr4 r/w h'0000 0000 h 'fe0a 00f0 h'1e0a 00f0 32 wait state control register 1 wcr1 r/w h'7777 7777 h'ff80 0008 h'1f80 0008 32 wait state control register 2 wcr2 r/w h'fffe efff h'ff80 000c h'1f80 000c 32 wait state control register 3 wcr3 r/w h'0777 7777 h'ff80 0010 h'1f80 0010 32 memory control register mcr r/ w h'0000 0000 h'ff80 0014 h'1f80 0014 32 pcmcia control register pcr r/w h'0000 h'ff80 0018 h'1f80 0018 16 refresh timer control/status register rtcsr r/w h'0000 h'ff 80 001c h'1f80 001c 16 refresh timer counter rtcnt r/ w h'0000 h'ff80 0020 h'1f80 0020 16 refresh time constant counter rtcor r/w h'0000 h 'ff80 0024 h'1f80 0024 16 refresh count register rfcr r/ w h'0000 h'ff80 0028 h'1f80 0028 16 for area 2 sdmr2 w ? h'ff90 xxxx * 1 h'1f90 xxxx 8 synchronous dram mode registers for area 3 sdmr3 h'ff94 xxxx * 1 h'1f94 xxxx notes: 1. for details, see section 13.2.10, synchronous dram mode register (sdmr). 2. sh7751r only
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 341 of 1122 rej09b0370-0400 13.1.5 overview of areas space divisions: the architecture of this lsi provides a 32-bit virtual address space. the virtual address space is divided into five areas accordin g to the upper address value. external memory space comprises a 29-bit address sp ace, divided into eight areas. the virtual address can be allocated to any external address by means of the memory management unit (mmu). details are given in section 3, memory management unit (mmu). this section describes the areas into which the external address is divided. with this lsi, various kinds of memory or pc cards can be connected to the seven areas of external address as shown in tabl e 13.3, and chip select signals ( cs0 ? cs6 , ce2a , ce2b ) are output for each of these areas. cs0 is asserted when accessing area 0, and cs6 when accessing area 6. when dram or synchronous dram is connected to area 2 or 3, signals such as ras , cas , rd/ wr , and dqm are also asserted. when the pcmc ia interface is selected for area 5 or 6, ce2a , ce2b is asserted in addition to cs5 , cs6 for the byte to be accessed. h'0000 0000 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff h'e400 0000 h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1fff ffff h'1c00 0000 area 0 ( cs0 ) area 1 ( cs1 ) area 2 ( cs2 ) area 3 ( cs3 ) area 4 ( cs4 ) area 5 ( cs5 ) area 6 ( cs6 ) area 7 (reserved area) p0 and u0 areas p1 area p2 area p3 area physical address space (mmu off) virtual address space (mmu on) external memory space store queue area p4 area p0 and u0 areas 256 p1 area p2 area p3 area store queue area p4 area notes: 1. when the mmu is off (mmucr.at = 0), the top 3 bits of the 32-bit address are i g nored, and memory is mapped onto a fixed 29-bit external address. 2. when the mmu is on (mmucr.at = 1), the p0, u0, p3, and store queue areas can be mapped onto any external space usin g the tlb. for details, see section 3, memory mana g ement unit (mmu). figure 13.2 correspondence between virtual address space and external memory space
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 342 of 1122 rej09b0370-0400 table 13.3 external memory space map area external addresses size connectable memory settable bus widths access size 0 64 mbytes sram 8, 16, 32 * 1 burst rom 8, 16, 32 * 1 h'00000000 ? h'03ffffff mpx 32 * 1 8 , 16 , 32 , 64 * 6 bits, 32 bytes 1 64 mbytes sram 8, 16, 32 * 2 mpx 32 * 2 h'04000000 ? h'07ffffff byte control sram 16, 32 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes 2 64 mbytes sram 8, 16, 32 * 2 synchronous dram 32 * 2 , * 3 h'08000000 ? h'0bffffff mpx 32 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes 3 64 mbytes sram 8, 16, 32 * 2 synchronous dram 32 * 2 , * 3 dram 16, 32 * 2 , * 3 h'0c000000 ? h'0fffffff mpx 32 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes 4 64 mbytes sram 8, 16, 32 * 2 mpx 32 * 2 h'10000000 ? h'13ffffff byte control ram 16, 32 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes 5 64 mbytes sram 8, 16, 32 * 2 mpx 32 * 2 burst rom 8, 16, 32 * 2 h'14000000 ? h'17ffffff pcmcia 8, 16 * 2 , * 4 8 , 16 , 32 , 64 * 6 bits, 32 bytes 6 64 mbytes sram 8, 16, 32 * 2 mpx 32 * 2 burst rom 8,16, 32 * 2 h'18000000 ? h'1bffffff pcmcia 8,16 * 2 , * 4 8 , 16 , 32 , 64 * 6 bits, 32 bytes 7 * 5 h'1c000000 ? h'1fffffff 64 mbytes ? ? notes: 1. memory bus width specified by external pins 2. memory bus width specified by register 3. with synchronous dram interface, bus width is 32 bits only with dram interface, bus width is 16 or 32 bits only 4. with pcmcia interface, bus width is 8 or 16 bits only 5. do not access a reserved area, as operation cannot be guaranteed in this case
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 343 of 1122 rej09b0370-0400 6. a 64-bit access size applies only to transfer by the dmac (chcrn.ts = 000). in the case of access to ex ternal memory by means of fmov (fpscr.sz = 1), two 32-bit access size transfers are performed. area 0: h'00000000 area 1: h'04000000 area 2: h'08000000 area 3: h'0c000000 area 4: h'10000000 area 5: h'14000000 area 6: h'18000000 sram/burst rom/mpx sram/mpx/byte control sram sram/synchronous dram/mpx sram/synchronous dram/dram/ mpx sram/mpx/byte control sram sram/burst rom/pcmcia/mpx sram/burst rom/pcmcia/mpx the pcmcia interface is for memory and i/o card use figure 13.3 external memory space allocation memory bus width: in this lsi, the memory bus width ca n be set independently for each space. for area 0, a bus size of 8, 16, or 32 bits can be selected in a power-on reset by means of the reset pin, using external pins. the relationship between the external pins (md4 and md3) and the bus width in a power-on reset is shown below. md4 md3 bus width 0 0 reserved 1 8 bits 1 0 16 bits 1 32 bits when sram interface or rom is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be selected with bus control register 2 (bcr2). when burst rom is used, a bus width of 8, 16, or 32 bits can be selected. when byte control sram interface is used, a bus width of 16, or 32 bits can be selected. when the mpx interface is used, a bu s width of 32 bit can be set. when the dram interface is used, a bus width of 16, or 32 bits can be selected with the memory control register (mcr). for the synchronous dram interface, set a bus width of 32 bit in the mcr register.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 344 of 1122 rej09b0370-0400 when using the pcmcia interface, set a bus width of 8 or 16 bits. for details, see section 13.3.7, pcmcia interface. for details, see section 13.2.2, bus control re gister 2 (bcr2), and section 13.2.8, memory control register (mcr). the area 7 address range, h'1c000000 to h'1fffff fff, is a reserved space and must not be used. 13.1.6 pcmcia support this lsi supports pcmcia interf ace specifications for external memory space ar eas 5 and 6. the interfaces supported are the ic memory car d interface and i/o card interface stipulated in jeida specifications version 4.2 (pcmcia2.1). external memory space areas 5 and 6 support both the ic memory card interface and the i/o card interface. the pcmcia interface is supporte d only in little-endian mode. table 13.4 pcmcia interface features item features access random access data bus 8/16 bits memory type mask rom, otprom, eprom, eeprom, flash memory, sram common memory capacity max. 64 mbytes attribute memory capacity max. 64 mbytes others dynamic bus sizing for i/o bus width, access to pcmcia interface from address translation areas
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 345 of 1122 rej09b0370-0400 table 13.5 pcmcia support interfaces ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 1 gnd ground gnd ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable cs5 or cs6 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we / pgm i write enable we / pgm i write enable we1 16 rdy / bsy o ready/busy ireq o interrupt request sensed on port 17 vcc operating power supply vcc operating power supply ? 18 vpp1 programming power supply vpp1 programming/ peripheral power supply ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 346 of 1122 rej09b0370-0400 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp * o write protect iois16 o 16-bit i/o port iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection sensed on port 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2a or ce2b 43 rfsh i refresh request rfsh i refresh request output from port 44 rfu reserved iord i i/o read iciord 45 rfu reserved iowr i i/o write iciowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 vcc power supply vcc power supply ? 52 vpp2 programming power supply vpp2 programming/ peripheral power supply ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address a25
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 347 of 1122 rej09b0370-0400 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 57 rfu reserved rfu reserved ? 58 reset i reset reset i reset output from port 59 wait o wait request wait o wait request rdy * 2 60 rfu reserved inpack o input acknowledge ? 61 reg i attribute memory space select reg i attribute memory space select reg 62 bvd2 o battery voltage detection spkr o digital speech signal sensed on port 63 bvd1 o battery voltage detection stschg o card status change sensed on port 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection sensed on port 68 gnd ground gnd ground ? notes: 1. wp is not supported. 2. input an external wait request with correct polarity.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 348 of 1122 rej09b0370-0400 13.2 register descriptions 13.2.1 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 32-bit readable/w ritable register that specifies the function, bus cycle status, etc., of each area. bcr1 is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. external memory space other th an area 0 should not be accessed until register initialization is completed. bit: 31 30 29 28 27 26 25 24 endian master a0mpx ? ? dpup ipup opup initial value: 0/1 * 0/1 * 0/1 * 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? ? a1mbc a4mbc breqen ? memmpx dmabst initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r r/w r/w bit: 15 14 13 12 11 10 9 8 hizmem hizcnt a0bst2 a0bst1 a0bst0 a5bst2 a5bst1 a5bst0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a6bst2 a6bst1 a6bst0 dramtp2 dramtp1 dramtp0 ? a56pcm initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r/w note: * these bits sample external pin values in a power-on reset by means of the reset pin.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 349 of 1122 rej09b0370-0400 bit 31?endian flag (endian): samples the value of the endi an specification external pin (md5) in a power-on reset by means of the reset pin. the endian mode of all spaces is determined by this bit. endian is a read-only bit. bit 31: endian description 0 in a power-on reset, the endian setting external pin (md5) is low, designating big-endian mode for this lsi 1 in a power-on reset, the endian setting external pin (md5) is high, designating little-endian mode for this lsi bit 30?master/slave flag (master): samples the value of the master/slave specification external pin (md7) in a powe r-on reset by means of the reset pin. the master/slave status of all spaces is determined by this b it. master is a read-only bit. bit 30: master description 0 in a power-on reset, the master/slave setting external pin (md7) is high, designating master mode for this lsi 1 in a power-on reset, the master/slave setting external pin (md7) is low, designating slave mode for this lsi bit 29?area 0 memory type (a0mpx): samples the value of the area 0 memory type specification external pin (md6) in a power-on reset by means of the reset pin. the memory type of area 0 is determined by th is bit. a0mpx is a read-only bit. bit 29: a0mpx description 0 in a power-on reset, the external pin specifying the area 0 memory type (md6) is high, designating the area 0 as sram interface 1 in a power-on reset, the external pin specifying the area 0 memory type (md6) is low, designating the area 0 as mpx interface bits 28, 27, 23, 22, 18, and 1?reserved: these bits are always read as 0, and the write value should always be 0.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 350 of 1122 rej09b0370-0400 bit 26?data pin pullup resistor control (dpup): controls the pullup resistance of the data pins (d31 to d0). it is initialized at a power-on reset. the pins are not pulled up when access is performed or when the bus is released, even if the on setting is selected. bit 26: dpup description 0 sets pullup resistance of data pins (d31 to d0) on (initial value) 1 sets pullup resistance of data pins (d31 to d0) off bit 25?control input pin pull-up resistor control (ipup): specifies the pul l-up resistor status for control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , sleep , rdy ). ipup is initialized by a power-on reset. bit 25: ipup description 0 pull-up resistor is on for control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , sleep , rdy ) (initial value) 1 pull-up resistor is off fo r control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , sleep , rdy ) bit 24?control output pin pull-up resistor control (opup): specifies the pull-up resistor status for control output pins (a[25:0], bs , csn , rd , wen , casn , rd/ wr , ras , ce2a , ce2b , md5) when high-impedance. opup is initialized by a power-on reset. bit 24: opup description 0 pull-up resistor is on for control output pins (a[25:0], bs , csn , rd , wen , casn , rd/ wr , ras , ce2a , ce2b , md5) (initial value) 1 pull-up resistor is off for control output pins (a[25:0], bs , csn , rd , wen , casn , rd/ wr , ras , ce2a , ce2b , md5) bit 21?area 1 sram byte control mode (a1mbc): mpx interface has priority when an mpx interface is set. this bit is initialized by a power-on reset. bit 21: a1mbc description 0 area 1 sram is set to normal mode (initial value) 1 area 1 sram is set to byte control mode
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 351 of 1122 rej09b0370-0400 bit 20?area 4 sram byte control mode (a4mbc): mpx interface has priority when an mpx interface is set. this bit is initialized by a power-on reset. bit 20: a4mbc description 0 area 4 sram is set to normal mode (initial value) 1 area 4 sram is set to byte control mode bit 19?breq enable (breqen): indicates whether external re quests and bus requests from pcic can be accepted. bre qen is initialized to the external request and bus request from pcic acceptance disabled state by a power- on reset. it is ignored in th e case of a slave mode startup. the bus request from the pcic is alwa ys accepted in a slave mode start up. bit 19: breqen description 0 external requests and bus requests from pcic are not accepted (initial value) 1 external requests and bus requests from pcic are accepted bit 17?area 1 to 6 mpx bu s specification (memmpx): sets the mpx interface when areas 1 to 6 are set as sram interface (or burst rom in terface). memmpx is initialized by a power-on reset. bit 17: memmpx description 0 sram interface (or burst rom interface) is selected when areas 1 to 6 are set as sram interface (or burst rom interface) (initial value) 1 mpx interface is selected when areas 1 to 6 are set as sram interface (or burst rom interface) bit 16?dmac burst mode transf er priority setting (dmabst): specifies the priority of burst mode transfers by the dmac. when off, the priority is as follows: bus privilege released, refresh, dmac, cpu. when on, th e bus privileges are released and refresh operations are not performed until the end of the dmac 's burst transfer. this bit is initialized at a power-on reset. bit 16: dmabst description 0 dmac burst mode transfer priority specification off (initial value) 1 dmac burst mode transfer priority specification on
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 352 of 1122 rej09b0370-0400 bit 15?high impedance control (hizmem): specifies the state of address and other signals (a[25:0], bs , csn , rd/ wr , ce2a , ce2b ) in standby mode. bit 15: hizmem description 0 the a[25:0], bs , csn , rd/ wr , ce2a , and ce2b signals go to high- impedance (hi-z) in standby mode and when the bus is released (initial value) 1 the a[25:0], bs , csn , rd/ wr , ce2a , and ce2b signals drive in standby mode bit 14?high impedance control (hizcnt): specifies the state of the ras and cas signals in standby mode and when the bus is released. bit 14: hizcnt description 0 the ras , wen , casn /dqmn, and rd / cass / frame signals go to high- impedance (hi-z) in standby mode and when the bus is released (initial value) 1 the ras , wen , casn /dqmn, and rd / cass / frame signals drive in standby mode and when the bus is released
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 353 of 1122 rej09b0370-0400 bits 13 to 11?area 0 burst rom control (a0bst2?a0bst0): these bits specify whether burst rom interface is used in area 0. when burs t rom interface is used, they also specify the number of accesses in a burst. if area 0 is an mpx interface area, th ese bits are ignored. bit 13: a0bst2 bit 12: a0bst1 bit 11: a0bst0 description 0 0 0 area 0 is accessed as sram interface (initial value) 1 area 0 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 0 area 0 is accessed as burst rom interface (8 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 area 0 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 0 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 354 of 1122 rej09b0370-0400 bits 10 to 8?area 5 burst enable (a5bst2?a5bst0): these bits specify whether burst rom interface is used in area 5. wh en burst rom interface is used, th ey also specify the number of accesses in a burst. if area 5 is an mpx interface area, these bits are ignored. bit 10: a5bst2 bit 9: a5bst1 bit 8: a5bst0 description 0 0 0 area 5 is accessed as sram interface (initial value) 1 area 5 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 0 area 5 is accessed as burst rom interface (8 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 area 5 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 5 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved note: clear to 0 when pc mcia interface is set.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 355 of 1122 rej09b0370-0400 bits 7 to 5?area 6 burst enable (a6bst2?a6bst0): these bits specify whether burst rom interface is used in area 6. when burst rom is us ed, they also specify the number of accesses in a burst. if area 6 is an mpx inte rface area, these bits are ignored. bit 7: a6bst2 bit 6: a6bst1 bit 5: a6bst0 description 0 0 0 area 6 is accessed as sram interface (initial value) 1 area 6 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 0 area 6 is accessed as burst rom interface (8 consecutive accesses) can be used with 8-, 16-, or 32-bit bus width 1 area 6 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 6 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved note: clear to 0 when pcmcia is used.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 356 of 1122 rej09b0370-0400 bits 4 to 2?area 2 and 3 memory type (dramtp2?dramtp0): these bits specify the type of memory connected to areas 2 and 3. rom, sram, flash rom, etc., can be connected as sram interface. dram and synchronous dr am can also be directly connected. bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 0 0 0 areas 2 and 3 are accessed as sram interface or mpx interface * (initial value) 1 reserved (cannot be set) 1 0 area 2 is accessed as sram interface or mpx interface * , area 3 is synchronous dram interface 1 areas 2 and 3 are accessed as synchronous dram interface 1 0 0 area 2 is accessed as sram interface or mpx interface * , area 3 is dram interface 1 reserved (cannot be set) 1 0 reserved (cannot be set) 1 reserved (cannot be set) note: * selection of sram interface or mpx inte rface is determined by the setting of the memmpx bit bit 0?area 5 and 6 bus type (a56pcm): specifies whether areas 5 and 6 are accessed as pcmcia interface. the setting of these bits has priority over the memmpx and anbst bit settings. bit 0: a56pcm description 0 areas 5 and 6 are accessed as sram interface (initial value) 1 areas 5 and 6 are accessed as pcmcia interface * note: * the md3 pin is desig nated for output as the ce2a pin. the md4 pin is desig nated for output as the ce2b pin.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 357 of 1122 rej09b0370-0400 13.2.2 bus control register 2 (bcr2) bus control register 2 (bcr2) is a 32-bit readable/w ritable register that specifies the bus width for each area, and whether a 16-bit port is used. bcr2 is initialized to h'3ffc by a power-on reset, but is not initialized by a manual reset or in standby mode. external memory space other than area 0 should not be accessed until register initialization is completed. bit: 15 14 13 12 11 10 9 8 a0sz1 a0sz0 a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 initial value: 0/1 * 0/1 * 1 1 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3sz1 a3sz0 a2sz1 a2sz 0 a1sz1 a0sz0 ? porten initial value: 1 1 1 1 1 1 0 0 r/w: r/w r/w r/w r/w r/w r/w ? r/w note: * these bits sample the values of the exte rnal pins that specify the area 0 bus size. bits 15 and 14?area 0 bus width (a0sz1, a0sz0): these bits sample the external pins (md3 and md4) that specify the bus size in a power-on reset. they are read-only bits. bit 15: md4 bit 14: md3 bus width 0 0 reserved (setting prohibited) 1 8 bits 1 0 16 bits 1 32 bits
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 358 of 1122 rej09b0370-0400 bits 2n + 1, 2n?area n (1 to 6) bus width specification (ansz1, ansz0): these bits specify the bus width of area n (n = 1 to 6). (bit 0): porten bit 2n + 1: ansz1 bit 2n: ansz0 description 0 0 0 reserved (setting prohibited) 1 bus width is 8 bits 1 0 bus width is 16 bits 1 bus width is 32 bits (initial value) 1 0 0 reserved (setting prohibited) 1 bus width is 8 bits 1 0 bus width is 16 bits 1 bus width is 32 bits bit 1?reserved: this bit is always read as 0, and should only be written with 0. bit 0?port function enable (porten): specifies whether pins ad31 to ad0 are used as a 32-bit port. however, select pci-disable mode when using this function. bit 0: porten description 0 ad31 to ad0 are not used as a port (initial value) 1 ad31 to ad0 are used as a port
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 359 of 1122 rej09b0370-0400 13.2.3 bus control register 3 (bcr3) (sh7751r only) bus control register 3 (bcr3) is a 16-bit readable/w ritable register that specifies the selection of either the mpx interface or th e sram interface and specifies the burst length when the synchronous dram interface is used. bcr3 is initialized to h'0001 by a power-on reset, but is not initialized by a manual reset or in standby mode. no external memory space other th an area 0 should be accessed before register initialization has been completed. bit: 15 14 13 12 11 10 9 8 bit name: memmode a1mpx a4mpx ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r r r r r bit: 7 6 5 4 3 2 1 0 bit name: ? ? ? ? ? ? ? sdbl initial value: 0 0 0 0 0 0 0 1 r/w: r r r r r r r r/w bit 15 ? a1mpx/a4mpx enable (memmode): determines whether or not the selection of either the mpx interface or th e sram interface is by a1mpx and a4mpx rather than by memmpx. bit 15: memmode description 0 mpx or sram interface is selected by memmpx (initial value) 1 mpx or sram interface is selected by a1mpx and a4mpx
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 360 of 1122 rej09b0370-0400 bits 14 and 13 ? mpx-interface specification for area 1 and 4 (a1mpx, a4mpx): these bits specify the types of memory co nnected to areas 1 and 4. thes e settings are validated by memmode. bit 14: a1mpx description 0 sram/byte control sram interface is selected for area 1 (initial value) 1 mpx interface is selected for area 1 bit 13: a4mpx description 0 sram/byte control sram interface is selected for area 4 (initial value) 1 mpx interface is selected for area 4 bit 0 ? burst length (sdbl): sets the burst length when th e synchronous dram interface is used. the burst-length setting is only valid when the bus width is 32 bits. bit 0: sdbl description 0 burst length is 8 1 burst length is 4 (initial value)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 361 of 1122 rej09b0370-0400 13.2.4 bus control register 4 (bcr4) (sh7751r only) bus control register 4 (bcr4) is a register that enables asynchronous input for pins corresponding to individual bits. the bcr4 register is a 32-bit readable/writable register. it is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. when asynchronous input is set (asyncn = 1), the sampling timing is one cycle earlier than when synchronous input is set (asyncn = 0) * (see figure 13.4) the timings shown in this section and section 23 , electrical characteristics, are all for the case where synchronous input is set (asyncn = 0). note: * with the synchronous input setting, ensure that setup and hold times are observed. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? async4 async3 async2 async1 async0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r/w r/w r/w r/w bits 31 to 5?reserved: these bits are always read as 0, and the write value should always be 0.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 362 of 1122 rej09b0370-0400 bits 4 to 0?asynchronous input: these bits enable asynchronous input for the corresponding pins. bit 4?0: asyncn description 0 corresponding pin is synchronous input with respect to ckio (initial value) 1 asynchronous input with respect to ckio is enabled for corresponding pin bit 4 iois16 3 dreq1 2 dreq0 1 breq 0 rdy t1 tw tw twe t2 ckio rdy rdy (bcr4.async0 = 0) (bcr4.async0 = 1) figure 13.4 example of rdy sampling timing at which bcr4 is set (two wait cycles are inserted by wcr2)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 363 of 1122 rej09b0370-0400 13.2.5 wait control register 1 (wcr1) wait control register 1 (wcr1) is a 32-bit readab le/writable register that specifies the number of idle state insertion cycles for each area. with some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off. as a result, there is a possibility of a data bus collision when consecu tive memory accesses are performed on memory in different areas, or when a memory write is performed immediately after a read. in this lsi, the number of idle cycles set in the wcr1 register ar e inserted automatically if there is a possibility of this kind of data bus collision. wcr1 is initialized to h'77777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 ? dmaiw2 dmaiw1 dmaiw0 ? a6iw2 a6iw1 a6iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? a5iw2 a5iw1 a5iw0 ? a4iw2 a4iw1 a4iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ? a3iw2 a3iw1 a3iw0 ? a2iw2 a2iw1 a2iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? a1iw2 a1iw1 a1iw0 ? a0iw2 a0iw1 a0iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bits 31, 27, 23, 19, 15, 11, 7, and 3?reserved: these bits are always read as 0, and the write value should always be 0.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 364 of 1122 rej09b0370-0400 bits 30 to 28? dmaiw-dack device in ter-cycle idle specification (dmaiw2? dmaiw0): these bits specify the number of idle cycl es between bus cycles to be inserted when switching from a dack device to another space, or from a read access to a write access on the same device. the dmaiw bits are valid only for dma single address transfer; with dma dual address transfer, inter-area idle cycles are inserted. bits 4n + 2 to 4n?area n (6 to 0) inte r-cycle idle specification (anlw2?anlw0): these bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another sp ace, or from a read access to a write access in the same space. dmaiw2/aniw2 dmaiw1/aniw1 dmai w0/aniw0 inserted idle cycles 0 0 0 0 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 (initial value)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 365 of 1122 rej09b0370-0400 table 13.6 idle insertion between accesses following cycle same area different area same area different area read write read write preceding cycle cpu dma cpu dma cpu dma cpu dma mpx address output mpx address output read m m m m m m m (1) m (1) write m m m m * 2 m dma read (memory device) m m m m m m ? m (1) dma write (device memory) d d d d * 1 d d d d ? d (1) notes: "dma" in the table indicates dma single-address transfer. dma dual-address transfer is in accordance with the cpu. m, d: idle wait always inserted by wcr1 (m(1): once cycle inserted in mpx a ccess even if wcr1 is cleared to 0) m: idle cycles according to setting of aniw2-aniw0 (areas 0 to 6) d: idle cycles according to setting of dmaiw2-dmaiw0 1. inserted when device is switched 2. on the mpx interface, a wcr1 idle wait may be inserted before an access (either read or write) to the same area after a write a ccess. the specific conditions for idle wait insertion in accesses to the same area are shown below. (a) synchronous dram set to ras down mode (b) synchronous dram accessed by on-chip dmac apart from use under above conditions (a) a nd (b), an idle wait is also inserted between an mpx interface write access and a following access to the same area. even under the above conditions, an idle wait may be inserted in a same-area access following an interface write access, depending on the synch ronous dram pipeline access situation. an idle wait is not inserted when the wcr1 register setting is 0. the setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set. when synchronous dram is used in ras down mode, set bits dmaiw2-dmaiw0 to 000 and bits a3iw2-a3iw0 to 000.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 366 of 1122 rej09b0370-0400 13.2.6 wait control register 2 (wcr2) wait control register 2 (wcr2) is a 32-bit readab le/writable register that specifies the number of wait states to be inserted for each area. it al so specifies the data access pitch when performing burst memory access. this enables low-speed memo ry to be connected w ithout using external circuitry. wcr2 is initialized to h'fffeefff by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 a6w2 a6w1 a6w0 a6b2 a6b1 a6b0 a5w2 a5w1 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 a5w0 a5b2 a5b1 a5b0 a4w2 a4w1 a4w0 ? initial value: 1 1 1 1 1 1 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r bit: 15 14 13 12 11 10 9 8 a3w2 a3w1 a3w0 ? a2 w2 a2w1 a2w0 a1w2 initial value: 1 1 1 0 1 1 1 1 r/w: r/w r/w r/w r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a1w1 a1w0 a0w2 a0w1 a0w0 a0b2 a0b1 a0b0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 367 of 1122 rej09b0370-0400 bits 31 to 29?area 6 wait control (a6w2?a6w0): these bits specify the number of wait states to be inserted for area 6. for the case wh ere an mpx interface setting is made, see table 13.7. description first cycle bit 31: a6w2 bit 30: a6w1 bit 29: a6w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 28 to 26?area 6 burst pitch (a6b2?a6b0): these bits specify the nu mber of wait states to be inserted from the second data access onward at the time of setting the burst rom in a burst transfer. description burst cycle (excluding first cycle) bit 28: a6b2 bit 27: a6b1 bit 26: a6b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 368 of 1122 rej09b0370-0400 bits 25 to 23?area 5 wait control (a5w2?a5w0): these bits specify the number of wait states to be inserted for area 5. for the case wh ere an mpx interface setting is made, see table 13.7. description first cycle bit 25: a5w2 bit 24: a5w1 bit 23: a5w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 22 to 20?area 5 burst pitch (a5b2?a5b0): these bits specify the nu mber of wait states to be inserted from the second data access onward at the time of setting the burst rom in a burst transfer. description burst cycle (excluding first cycle) bit 22: a5b2 bit 21: a5b1 bit 20: a5b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 369 of 1122 rej09b0370-0400 bits 19 to 17?area 4 wait control (a4w2?a4w0): these bits specify the number of wait states to be inserted for area 4. for the case wh ere an mpx interface setting is made, see table 13.7. description bit 19: a4w2 bit 18: a4w1 bit 17: a4w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 16 and 12?reserved: these bits are always read as 0, and should only be written with 0. bits 15 to 13?area 3 wait control (a3w2?a3w0): these bits specify the number of wait states to be inserted for area 3. external wait input is only enabled when the sram interface or mpx interface is used, and is ignored when dr am or synchronous dram is used. for the case where an mpx interface setting is made, see table 13.7. ? when sram interface is set description bit 15: a3w2 bit 14: a3w1 bit 13: a3w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 370 of 1122 rej09b0370-0400 ? when dram or synchronous dram interface is set * note: * external wait input is always ignored description bit 15: a3w2 bit 14: a3w1 bit 13: a3w0 dram cas assertion width synchronous dram cas latency cycles 0 0 0 1 inhibited 1 2 1 * 1 0 3 2 1 4 3 1 0 0 7 4 * 1 10 5 * 1 0 13 inhibited 1 16 inhibited note: * inhibited in ras down mode bits 11 to 9?area 2 wait control (a2w2?a2w0): these bits specify the number of wait states to be inserted for area 2. exte rnal wait input is only enabled when the sram interface or mpx interface is used, and is ignored when synchron ous dram is used. for the case where an mpx interface setting is made, see table 13.7. ? when sram interface is set description bit 11: a2w2 bit 10: a2w1 bit 9: a2w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 371 of 1122 rej09b0370-0400 ? when synchronous dram interface is set * 1 description bit 11: a2w2 bit 10: a2w1 bit 9: a2w0 synchronous dram cas latency cycles 0 0 0 inhibited 1 1 * 2 1 0 2 1 3 1 0 0 4 * 2 1 5 * 2 1 0 inhibited 1 inhibited notes: 1. external wait input is always ignored 2. inhibited in ras down mode bits 8 to 6?area 1 wait control (a1w2?a1w0): these bits specify the number of wait states to be inserted for area 1. for the case where an mpx interface se tting is made, see table 13.7. description bit 8: a1w2 bit 7: a1w1 bit 6: a1w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 372 of 1122 rej09b0370-0400 bits 5 to 3?area 0 wait control (a0w2 to a0w0): these bits specify th e number of wait states to be inserted for area 0. for the case wh ere an mpx interface setting is made, see table 13.7. description first cycle bit 5: a0w2 bit 4: a0w1 bit 3: a0w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 2 to 0?area 0 burst pitch (a0b2?a0b0): these bits specify the nu mber of wait states to be inserted from the second data access onward at the time of setting the burst rom in a burst transfer. description burst cycle (excluding first cycle) bit 2: a0b2 bit 1: a0b1 bit 0: a0b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 373 of 1122 rej09b0370-0400 table 13.7 when mpx interf ace is set (areas 0 to 6) description inserted wait states 1st data anw2 anw1 anw0 read write 2nd data onward rdy pin 0 0 0 1 0 0 enabled 1 1 enabled 1 0 2 2 enabled 1 3 3 enabled 1 0 0 1 0 1 enabled 1 1 enabled 1 0 2 2 enabled 1 3 3 enabled note: n = 6 to 0
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 374 of 1122 rej09b0370-0400 13.2.7 wait control register 3 (wcr3) wait control register 3 (wcr3) is a 32-bit readab le/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. this enables low-speed memory to be connected without using external circuitry. wcr3 is initialized to h'07777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? a6s0 a6h1 a6h0 initial value: 0 0 0 0 0 1 1 1 r/w: r r r r r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? a5s0 a5h1 a5h0 a4rdh * a4s0 a4h1 a4h0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r/w * r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: ? a3s0 a3h1 a3h0 ? a2s0 a2h1 a2h0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a1rdh * a1s0 a1h1 a0h0 ? a0s0 a0h1 a0h0 initial value: 0 1 1 1 0 1 1 1 r/w: r/w * r/w r/w r/w r r/w r/w r/w note: * these bits can be set only in the sh7751r. bits 31 to 27, 23, 19*, 15, 11, 7*, and 3 (sh7751) bits 31 to 27, 23, 15, 11, and 3 (sh7751r) reserved: these bits are always read as 0, and should only be written with 0. note: * these bits can be set only in the sh7751r.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 375 of 1122 rej09b0370-0400 bit 4n + 2?area n (6 to 0) write strobe setup time (ans0): specifies the nu mber of cycles inserted in the setup time from the address until assertion of the read/write strobe. valid only for sram interface, byte control sram interface, and burst rom interface: bit 4n + 2: ans0 waits inserted in setup 0 0 1 1 (initial value) note: n = 6 to 0 bits 4n + 1 and 4n?area n (6 to 0) data hold time (anh1, anh0): when writing, these bits specify the number of cycles to be inserted in the hold time from negation of the write strobe. when reading, they specify the nu mber of cycles to be inserted in the hold time from the data sampling timing. valid only fo r sram interface, byte control sram interface, and burst rom interface: bit 4n + 1: anh1 bit 4n: anh0 waits inserted in hold 0 0 0 1 1 1 0 2 1 3 (initial value) note: n = 6 to 0 bits 4n + 3 ? area n (4 or 1) read-strobe negate ti ming (anrdh) (setting only possible in the sh7751r): when reading, these bits specify the timin g for the negation of read strobe. these bits should be cleared to 0 when a byte control sram setting is made. valid only for the sram interface. bit 4n + 3: anrdh read-strobe negate timing 0 read strobe negated after hold wait cycles specified by wcr3.anh bits (initial value) 1 read strobe negated according to data sampling timing note: n = 4 or 1
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 376 of 1122 rej09b0370-0400 13.2.8 memory control register (mcr) the memory control register (mcr) is a 32-b it readable/writable register that specifies ras and cas timing and burst control for dram and synchronous dram (areas 2 and 3), address multiplexing, and refresh control. this enables dram and synchronous dram to be connected without using external circuitry. mcr is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bits rasd, mrset, trc2?0, tpc2?0, rcd1?0, trwl2?0, tras2?0, be, sz1?0, amxext, amx2?0, and edomode are written in the initialization following a power- on reset, and should not be modified subseque ntly. when writing to bits rfsh and rmode, the same values should be written to the other bits so that they remain unchanged. when using dram or synchronous dram, areas 2 and 3 should not be accessed until register initialization is completed. bit: 31 30 29 28 27 26 25 24 rasd mrset trc2 trc1 trc0 ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r r r bit: 23 22 21 20 19 18 17 16 tcas ? tpc2 tpc1 tpc0 ? rcd1 rcd0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r/w r/w r r/w r/w bit: 15 14 13 12 11 10 9 8 trwl2 trwl1 trwl0 tras2 tras1 tras0 be sz1 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 sz0 amxext amx2 amx1 amx0 rfsh rmode edo mode initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 377 of 1122 rej09b0370-0400 bit 31?ras down (rasd): sets ras down mode. when ras down mode is used, set be to 1. do not set ras down mode in slave mode or when areas 2 and 3 are both designated as synchronous dram interface. bit 31: rasd description 0 auto-precharge mode (initial value) 1 ras down mode note: when synchronous dram is used in ras down mode, set bits dmaiw2?dmaiw0 to 000 and bits a3iw2?a3iw0 to 000. bit 30?mode regi ster set (mrset): set when a synchronous dram mode register setting is used. see power-on sequence in sectio n 13.3.5, synchronous dram interface. bit 30: mrset description 0 all-bank precharge (initial value) 1 mode register setting bits 26 to 24, 22, and 18?reserved: these bits should only be written with 0. bits 29 to 27?ras precharge time at end of refresh (trc2?trc0) (synchronous dram: auto- and self-refresh both enabled, dram: auto- and self-refresh both enabled) note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. bit 29: trc2 bit 28: trc1 bit 27: trc0 ras precharge time immediately after refresh 0 0 0 0 (initial value) 1 3 1 0 6 1 9 1 0 0 12 1 15 1 0 18 1 21
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 378 of 1122 rej09b0370-0400 bit 23?cas negation period (tcas): this bit is valid only when dram interface is set. bit 23: tcas cas negation period 0 1 (initial value) 1 2 bits 21 to 19?ras precharge period (tpc2?tpc0): when the dram interface is selected, these bits specify the minimu m number of cycles until ras is asserted again after being negated. when the synchronous dram interface is select ed, these bits specify the minimum number of cycles until the next bank active command after precharging. note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. ras precharge time bit 21: tpc2 bit 20: tpc1 bit 19: tpc0 dram synchronous dram 0 0 0 0 1 * (initial value) 1 1 2 1 0 2 3 1 3 4 * 1 0 0 4 5 * 1 5 6 * 1 0 6 7 * 1 7 8 * note: * inhibited in ras down mode bits 17 and 16?ras-cas delay (rcd1, rcd0): when the dram interface is set, these bits set the ras - cas assertion delay time. when the synchrono us dram interface is set, these bits set the bank active-read/write command delay time. description bit 17: rcd1 bit 16: rcd0 dram synchronous dram 0 0 2 cycles reserved (setting prohibited) 1 3 cycles 2 cycles 1 0 4 cycles 3 cycles 1 5 cycles 4 cycles * note: * inhibited in ras down mode
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 379 of 1122 rej09b0370-0400 bits 15 to 13?write precharge delay (trwl2?trwl0): these bits set the synchronous dram write precharge delay time. in auto-precharge mode, they specify the time until the next bank active command is issued afte r a write cycle. after a write cy cle, the next active command is not issued for a period set by tpc[2:0] and trwl[2:0] bits * . in ras down mode, they specify the time until the next precharge command is i ssued. after a write cycle, the next precharge command is not issued for a period of trwl. this setting is valid only when synchronous dram interface is set. note: * for setting values and the period during which no command is issued, see 23.3.3, bus timing. bit 15: trwl2 bit 14: trwl1 bit 13: tr wl0 write precharge act delay time 0 0 0 1 (initial value) 1 2 1 0 3 * 1 4 * 1 0 0 5 * 1 reserved (setting prohibited) 1 0 reserved (setting prohibited) 1 reserved (setting prohibited) note: * inhibited in ras down mode
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 380 of 1122 rej09b0370-0400 bits 12 to 10?cas-before-ras refresh ras assertion period (tras2?tras0): when the dram interface is set, these bits set the ras assertion period in cas-before-ras refreshing. when the synchronous dram interface is set, the bank active command is not issued for a period set by tpc[2:0] and tras[2:0] bits after an auto-refresh command is issued. note: for setting values and the period during which no command is issued, see 23.3.3, bus timing. bit 12: tras2 bit 11: tras1 bit 10: tras0 ras /dram assertion time command interval after synchronous dram refresh 0 0 0 2 4 + trc (initial value) 1 3 5 + trc 1 0 4 6 + trc 1 5 7 + trc 1 0 0 6 8 + trc 1 7 9 + trc 1 0 8 10 + trc 1 9 11 + trc note: trc (bits 29 to 27): ras precharge interval at end of refresh bit 9?burst enable (be): specifies whether burst access is pe rformed on dram interface. in synchronous dram access, burst access is always performed regardless of the specification of this bit. the dram transfer mode depends on edomode. be edomode 8/16/32/64-bit transfer 32-byte transfer 0 0 single single 1 setting prohibited setting prohibited 1 0 single/fast page * fast page 1 edo edo note: * in fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 381 of 1122 rej09b0370-0400 bits 8 and 7?memory data size (sz1, sz0): these bits specify the bus width of dram and synchronous dram. this setting has priority over the bcr2 register setting. description bit 8: sz1 bit 7: sz0 dram sdram 0 0 reserved (setting prohibited) reserved (setting prohibited) 1 reserved (setting prohibited) reserved (setting prohibited) 1 0 16 bits reserved (setting prohibited) 1 32 bits 32 bits bits 6 to 3?address multiple xing (amxext, amx2?amx0): these bits specify address multiplexing for dram and synchronous dram. th e address shift value is different for the dram interface and the synchronous dram interface. ? for dram interface: description bit 6: amxext bit 5: amx2 bit 4: amx1 bit 3: amx0 dram 0 * 0 0 0 8-bit column address product (initial value) 1 9-bit column address product 1 0 10-bit column address product 1 11-bit column address product 1 0 0 12-bit column address product 1 reserved (setting prohibited) 1 0 reserved (setting prohibited) 1 reserved (setting prohibited) note: * when the dram interface is used, clear the amxext bit to 0.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 382 of 1122 rej09b0370-0400 ? for synchronous dram interface: amx amxext sz example synchronous dram configurations bank 0 0 (16m: 512k 16 bits 2) 2 a[21] * 1 (16m: 512k 16 bits 2) 2 a[20] * 1 0 (16m: 1m 8 bits 2) 4 a[22] * 1 (16m: 1m 8 bits 2) 4 a[21] * 2 ? (64m: 1m 16 bits 4) 2 a[23:22] * 3 ? (64m: 2m 8 bits 4) 4 a[24:23] * 4 ? (64m: 512k 32 bits 4) 1 a[22:21] * 5 ? (64m: 1m 32 bits 2) 1 a[22] * 6 0 (64m: 4m 4 bits 4) 8 a[25:24] * 1 32 (256m: 4m 16 bits 4) 2 a[25:24] * 7 ? (16m: 256k 32 bits 2) 1 a[20] * note: * a[x]: external address, not address pin bit 2?refresh control (rfsh): specifies refresh control. selects whether refreshing is performed for dram and synchronous dram. when the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. bit 2: rfsh description 0 refreshing is not performed (initial value) 1 refreshing is performed
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 383 of 1122 rej09b0370-0400 bit 1?refresh mode (rmode): specifies whether normal refres hing or self-refreshing is performed when the rfsh bit is set to 1. when the rfsh bit is 1 and this bit is cleared to 0, cas- before-ras refreshing or auto-refreshing is performed for dram and synchronous dram, using the cycle set by refresh-related registers rtcnt, rtcor, and rt csr. if a refresh request is issued during an external bus cycl e, the refresh cycle is executed when the bus cycle ends. when the rfsh bit is 1 and this bit is set to 1, the self-refresh state is set for dram and synchronous dram, after waiting for the end of any currently executing external bus cycle. all refresh requests for memory in the self-refresh state are ignored. bit 1: rmode description 0 cas-before-ras refreshing is performed (when rfsh = 1) (initial value) 1 self-refreshing is performed (when rfsh = 1) bit 0?edo mode (edomode): used to specify the data sampling timing for data reads when using edo mode dram interface. the setting of th is bit does not affect the operation timing of memory other than dram. set this bit to 1 only when dram is used. 13.2.9 pcmcia cont rol register (pcr) the pcmcia control register (pcr) is a 16-bit readable/writable regist er that specifies the oe and we signal assertion/negation timing for the pc mcia interface connected to areas 5 and 6. the oe and we signal assertion width is set by the wait control bits in the wcr2 register. pcr is initialized to h'0000 by a power-on rese t, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: a5pcw1 a5pcw0 a6pcw1 a6 pcw0 a5ted2 a5ted1 a5ted0 a6ted2 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: a6ted1 a6ted0 a5teh2 a5 teh1 a5teh0 a6teh2 a6teh1 a6teh0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 384 of 1122 rej09b0370-0400 bits 15 and 14?pcmcia wait (a5pcw1, a5pcw0): these bits specify the number of waits to be added to the number of waits specified by wcr2 in a low-speed pc mcia wait cycle. the setting of these bits is selected when the pcmcia interface access tc bit is 0. bit 15: a5pcw1 bit 14: a5pcw0 waits inserted 0 0 0 (initial value) 1 15 1 0 30 1 50 bits 13 and 12?pcmcia wait (a6pcw1, a6pcw0): these bits specify the number of waits to be added to the number of waits specified by wcr2 in a low-speed pc mcia wait cycle. the setting of these bits is selected when the pcmcia interface access tc bit is 0. bit 13: a6pcw1 bit 12: a6pcw0 waits inserted 0 0 0 (initial value) 1 15 1 0 30 1 50 bits 11 to 9?address-oe/we assertion delay (a5ted2?a5ted0): these bits set the delay time from address output to oe / we assertion on the connected pc mcia interface. the setting of these bits is selected when the pcmcia interface access tc bit is 0. bit 11: a5ted2 bit 10: a5ted1 bit 9: a5ted0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 385 of 1122 rej09b0370-0400 bits 8 to 6?address-oe/we assertion delay (a6ted2?a6ted0): these bits set the delay time from address output to oe / we assertion on the connected pc mcia interface. the setting of these bits is selected when the pcmcia interface access tc bit is 0. bit 8: a6ted2 bit 7: a6ted1 bit 6: a6ted0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 bits 5 to 3?oe/we negation-address delay (a5teh2?a5teh0): these bits set the address hold delay time from oe / we negation in a write on the connect ed pcmcia interface or in an i/o card read. in the case of a memory card read, the address hold delay time from the data sampling timing is set. the setting of these bits is select ed when the pcmcia interface access tc bit is 0. bit 5: a5teh2 bit 4: a5teh1 bit 3: a5teh0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 386 of 1122 rej09b0370-0400 bits 2 to 0?oe/we negation-address delay (a6teh2?a6teh0): these bits set the address hold delay time from oe / we negation in a write on the connect ed pcmcia interface or in an i/o card read. in the case of a memory card read, th e address hold delay time from the data sampling timing is set. the setting of these bits is sele cted when the pcmcia interface access tc bit is 0. bit 2: a6teh2 bit 1: a6teh1 bit 0: a6teh0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 13.2.10 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is a write-only virtual 16-bit register that is written to via the synchronous dram address bu s, and sets the mode of the area 2 and area 3 synchronous dram. settings for the sdmr register must be made before accessing synchronous dram. bit: 15 14 13 12 11 10 9 8 initial value: ? ? ? ? ? ? ? ? r/w: w w w w w w w w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: w w w w w w w w since the address bus, not the data bus, is used to write to the synchronous dram mode register, if the value to be set is ?x? and the sdmr regist er address is ?y?, valu e ?x? is written to the synchronous dram mode register by performing a write to address x + y. when the synchronous dram bus width is set to 32 bits, as a0 of the synchronous dram is connected to
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 387 of 1122 rej09b0370-0400 a2 of this lsi, and a1 of the synchronous dram is connected to a3 of this lsi, the value actually written to the synchronous dram is the value of ?x? shifted 2 bits to the right. for example, to write h'0230 to the area 2 sdmr register, arbitr ary data is written to address h'ff900000 (address ?y?) + h'08c0 (value ?x?) (= h'ff9008c0). as a result, h'0230 is written to the sdmr register. the range of value ?x? is h'0000 to h'0ffc. similarly, to write h'0230 to the area 3 sdmr register, arbitrary data is written to address h'ff940000 (address ?y?) + h'08c0 (value ?x?) (= h'ff9408c0). as a result, h'0230 is written to the sdmr register. the range of value ?x? is h'0000 to h'0ffc. the lower 16 bits of the address are set in the synchronous dram mode register. the burst length is 4 and 8 * . setting to sdmr writes into the following addresses in byte size. bus width burst length cas latency area 2 area 3 32 4 1 h'ff900048 h'ff940048 2 h'ff900088 h'ff940088 3 h'ff9000c8 h'ff9400c8 32 8 * 1 h'ff90004c h'ff94004c 2 h'ff90008c h'ff94008c 3 h'ff9000cc h'ff9400cc note: * sh7751r only for a 32-bit bus: 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 0 0 0 0 0 0 0 0 0 lmo de2 lmo de1 lmo de0 wt bl2 bl1 bl0 ???????????????????? 10 bits set in case of 32-bit bus width lmode: cas latency bl: burst length wt: wrap type (0: sequential)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 388 of 1122 rej09b0370-0400 bl lmode 000: reserved 000: reserved 001: reserved 001: 1 010: 4 010: 2 011: 8 * 011: 3 100: reserved 100: reserved 101: reserved 101: reserved 110: reserved 110: reserved 111: reserved 111: reserved note: * sh7751r only 13.2.11 refresh timer cont rol/status register (rtcsr) the refresh timer control/status register (rtcsr) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. rtscr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. for the write values, see section 13.2.15, notes on accessing refresh control registers.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 389 of 1122 rej09b0370-0400 bit 7?compare-match flag (cmf): status flag that indicates a match between the refresh timer counter (rtcnt) and refresh time constant register (rtcor) values. bit 7: cmf description 0 rtcnt and rtcor values do not match (initial value) [clearing condition] when 0 is written to cmf 1 rtcnt and rtcor values match [setting condition] when rtcnt = rtcor * note: * if 1 is written, the original value is retained. bit 6?compare-match interrupt enable (cmie): controls generation or suppression of an interrupt request when the cmf flag is set to 1 in rtcsr. do not set this bit to 1 when cas- before-ras refreshing or auto-refreshing is used. bit 6: cmie description 0 interrupt requests initiated by cmf are disabled (initial value) 1 interrupt requests initiated by cmf are enabled bits 5 to 3?clock select bits (cks2?cks0): these bits select the in put clock for rtcnt. the base clock is the external bus clock (ckio). the rtcnt count clock is obtained by scaling ckio by the specified factor. bit 5: cks2 bit 4: cks1 bit 3: cks0 description 0 0 0 clock input disabled (initial value) 1 bus clock (ckio)/4 1 0 ckio/16 1 ckio/64 1 0 0 ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 390 of 1122 rej09b0370-0400 bit 2?refresh count overflow flag (ovf): status flag that indicat es that the number of refresh requests indicated by th e refresh count register (rfcr) has exceeded the number specified by the lmts bit in rtcsr. bit 2: ovf description 0 rfcr has not overflowed t he count limit indicated by lmts (initial value) [clearing condition] when 0 is written to ovf 1 rfcr has overflowed the count limit indicated by lmts [setting condition] when rfcr overflows the count limit set by lmts * note: * if 1 is written, the original value is retained. bit 1?refresh count overflow interrupt en able (ovie): controls generation or suppression of an interrupt request when the ovf flag is set to 1 in rtcsr. bit 1: ovie description 0 interrupt requests initiated by ovf are disabled (initial value) 1 interrupt requests initiated by ovf are enabled bit 0?refresh count overflow limit select (lmts): specifies the count li mit to be compared with the refresh count indicated by the refresh co unt register (rfcr). if the rfcr register value exceeds the value specified by lm ts, the ovf flag is set. bit 0: lmts description 0 count limit is 1024 (initial value) 1 count limit is 512 13.2.12 refresh time r counter (rtcnt) the refresh timer counter (rtcnt) is an 8-bit re adable/writable counter that is incremented by the input clock (selected by bits cks2?cks0 in the rtcsr register). when the rtcnt counter value matches the rtcor register value, the cm f bit is set in the rtcsr register and the rtcnt counter is cleared.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 391 of 1122 rej09b0370-0400 rtcnt is initialized to h'0000 by a power-on reset, but continues to count when a manual reset is performed. in standby mode, rtcnt is not initialized, and retains its contents. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.13 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a readable/writable re gister that specifies the upper limit of the rtcnt counter. the rtcor register and rtcnt counter values (lower 8 bits) are constantly compared, and when they match the cmf bit is set in the rtcsr register and the rtcnt counter is cleared to 0. if the refresh bit (rfsh) has been set to 1 in the memory control register (mcr) and cas-before-ras has been se lected as the refresh mode, a memory refresh cycle is generated when the cmf bit is set. rtcor is initialized to h'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 392 of 1122 rej09b0370-0400 13.2.14 refresh count register (rfcr) the refresh count register (rfcr) is a 10-bit read able/writable counter that counts the number of refreshes by being incremented each time the rtcor register and rtcnt counter values match. if the rfcr register value exceeds the count lim it specified by the lmts bit in the rtcsr register, the ovf flag is set in the rtcsr register and the rfcr register is cleared. rfcr is initialized to h'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.15 notes on accessing refresh control registers when the refresh timer control/status register (rtcsr), refresh timer counter (rtcnt), refresh time constant register (rtcor), and refresh count register (rfcr) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. the following procedures should be used for read/write operations. writing to rtcsr, rtcnt, rtcor, and rfcr: a word transfer instruction must always be used when writing to rtcsr, rtcnt, rtcor, or rfcr. a write cannot be performed with a byte transfer instruction. when writing to rtcsr, rtcnt, or rtcor, set b'10100101 in the upper byte and the write data in the lower byte, as shown in figure 13.5. when writing to rfcr, set b'101001 in the 6 bits starting from the msb in the upper byte, and the write data in the remaining bits.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 393 of 1122 rej09b0370-0400 15 14 13 12 11 10 9 8 10 100 101 76543210 15 14 13 12 11 10 9 8 10 100 1 76543210 write data write data rtcsr, rtcnt, rtcor rfcr figure 13.5 writing to rtcsr, rtcnt, rtcor, and rfcr reading rtcsr, rtcnt, rtcor, and rfcr: a 16-bit access must always be used when reading rtcsr, rtcnt, rtcor, or rf cr. undefined bits are read as 0. 13.3 operation 13.3.1 endian/access size and data alignment this lsi supports both big-endian mode, in which the most significant byte (msbyte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (lsbyte) is at the 0 address end. the mode is se t by means of the md5 external pin in a power-on reset by means of the reset pin, big-endian mode being set if the md5 pin is low, and little- endian mode if it is high. a data bus width of 8, 16, or 32 bits can be selected for normal memory, 16 or 32 bits for dram, 32 bit for synchronous dram, and 8 or 16 bits for the pcmcia interface. data alignment is carried out according to the data bus width and endian mode of each device. accordingly, when the data bus width is narrower than the access size, multiple bus cycl es are automatically generated to reach the access size. in this case, access is performed by auto matically incrementing addresses to the bus width. for ex ample, when a long word access is performed at the area with an 8-bit bus width in the sram inte rface, each address is incremente d one by one, and then access is performed four times. in the 32-byt e transfer, a total of 32-byte da ta is continuously transferred according to the set bus width. the first access is performed on the data for which there was an access request, and the remaining accesses are performed in 32-byte boundary data using waparound. during these transfers, the bus is not released and refresh operation is not performed. in this lsi, data alignment and data length conversion between the different interfaces is performed automatically. quadword access is used only in transfer by the dmac. the relationship between the endian mode, device data length, and access unit, is shown in tables 13.8 to 13.13.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 394 of 1122 rej09b0370-0400 data configuration msb lsb byte data 7?0 msb lsb word data 15?8 data 7?0 msb lsb longword data 31?24 data 23?16 data 15?8 data 7?0 msb lsb quadword data 63?56 data 55?48 data 47?40 data 39?32 data 31?24 data 23?16 data 15?8 data 7?0 table 13.8 32-bit extern al device/big-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 4n 1 data 7?0 ? ? ? asserted 4n + 1 1 ? data 7?0 ? ? asserted 4n + 2 1 ? ? data 7?0 ? asserted 4n + 3 1 ? ? ? data 7?0 asserted word 4n 1 data 15?8 data 7?0 ? ? asserted asserted 4n + 2 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted quad- word 8n 1 data 63?56 data 55?48 data 47?40 data 39?32 asserted asserted asserted asserted 8n + 4 2 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 395 of 1122 rej09b0370-0400 table 13.9 16-bit extern al device/big-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 2n 1 ? ? data 7?0 ? asserted 2n + 1 1 ? ? ? data 7?0 asserted word 2n 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 ? ? data 31?24 data 23?16 asserted asserted 4n + 2 2 ? ? data 15?8 data 7?0 asserted asserted quad- word 8n 1 ? ? data 63?56 data 55?48 asserted asserted 8n + 2 2 ? ? data 47?40 data 39?32 asserted asserted 8n + 4 3 ? ? data 31?24 data 23?16 asserted asserted 8n + 6 4 ? ? data 15?8 data 7?0 asserted asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 396 of 1122 rej09b0370-0400 table 13.10 8-bit external device/big-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte n 1 ? ? ? data 7?0 asserted word 2n 1 ? ? ? data 15?8 asserted 2n + 1 2 ? ? ? data 7?0 asserted long- word 4n 1 ? ? ? data 31?24 asserted 4n + 1 2 ? ? ? data 23?16 asserted 4n + 2 3 ? ? ? data 15?8 asserted 4n + 3 4 ? ? ? data 7?0 asserted quad- word 8n 1 ? ? ? data 63?56 asserted 8n + 1 2 ? ? ? data 55?48 asserted 8n + 2 3 ? ? ? data 47?40 asserted 8n + 3 4 ? ? ? data 39?32 asserted 8n + 4 5 ? ? ? data 31?24 asserted 8n + 5 6 ? ? ? data 23?16 asserted 8n + 6 7 ? ? ? data 15?8 asserted 8n + 7 8 ? ? ? data 7?0 asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 397 of 1122 rej09b0370-0400 table 13.11 32-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 4n 1 ? ? data 7?0 asserted 4n + 1 1 ? ? data 7?0 ? asserted 4n + 2 1 ? data 7?0 ? ? asserted 4n + 3 1 data 7?0 ? ? ? asserted word 4n 1 ? ? data 15?8 data 7?0 asserted asserted 4n + 2 1 data 15?8 data 7?0 ? ? asserted asserted long- word 4n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted quad- word 8n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted 8n + 4 2 data 63?56 data 55?48 data 47?40 data 39?32 asserted asserted asserted asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 398 of 1122 rej09b0370-0400 table 13.12 16-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 2n 1 ? ? ? data 7?0 asserted 2n + 1 1 ? ? data 7?0 ? asserted word 2n 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 ? ? data 15?8 data 7?0 asserted asserted 4n + 2 2 ? ? data 31?24 data 23?16 asserted asserted quad- word 8n 1 ? ? data 15?8 data 7?0 asserted asserted 8n + 2 2 ? ? data 31?24 data 23?16 asserted asserted 8n + 4 3 ? ? data 47?40 data 39?32 asserted asserted 8n + 6 4 ? ? data 63?56 data 55?48 asserted asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 399 of 1122 rej09b0370-0400 table 13.13 8-bit external device/little-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte n 1 ? ? ? data 7?0 asserted word 2n 1 ? ? ? data 7?0 asserted 2n + 1 2 ? ? ? data 15?8 asserted long- word 4n 1 ? ? ? data 7?0 asserted 4n + 1 2 ? ? ? data 15?8 asserted 4n + 2 3 ? ? ? data 23?16 asserted 4n + 3 4 ? ? ? data 31?24 asserted quad- word 8n 1 ? ? ? data 7?0 asserted 8n + 1 2 ? ? ? data 15?8 asserted 8n + 2 3 ? ? ? data 23?16 asserted 8n + 3 4 ? ? ? data 31?24 asserted 8n + 4 5 ? ? ? data 39?32 asserted 8n + 5 6 ? ? ? data 47?40 asserted 8n + 6 7 ? ? ? data 55?48 asserted 8n + 7 8 ? ? ? data 63?56 asserted
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 400 of 1122 rej09b0370-0400 13.3.2 areas area 0: for area 0, external addres s bits 28 to 26 are 000. sram, mpx, and burst rom can be set for this area. a bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins md4 and md3. for details, see memory bus width in section 13.1.5, overview of areas. when area 0 is accessed, the cs0 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected w ith bits a0w2 to a0w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst rom interface is used, the number of burst cycle transfer states is selected in the range 2 to 9 according to the number of waits. the read/write strobe signal address and the cs setu p/hold time can be set, respectively, to 0 or 1 and to 0 to 3 cycles using the a0s0, a0h1, and a0h0 bits in the wcr3 register. area 1: for area 1, external addres s bits 28 to 26 are 001. sram, mpx, and byte control sram can be set for this area. a bus width of 8, 16, or 32 bits can be selected with bits a1sz1 and a1sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 bit should be sel ected with bits a1sz1 and a1sz0 in the bcr2 register. when byte co ntrol sram interface is set, select a bus width of 16 or 32 bits. when area 1 is accessed, the cs1 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected w ith bits a1w2 to a1w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a1s0 and bits a1h1 and a1h0 in the wcr3 register.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 401 of 1122 rej09b0370-0400 area 2: for area 2, external addres s bits 28 to 26 are 010. sram, mpx, and synchronous dram can be set to this area. when sram interface is set, a bus width of 8, 16, or 32 bits can be selected with bits a2sz1 and a2sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 bit should be selected with bits a2sz1 and a2sz0 in the bcr2 register . when synchronous dram interface is set, select 32 bit with the sz bits in the mcr regi ster. for details, see memory bus width in section 13.1.5, overview of areas. when area 2 is accessed, the cs2 signal is asserted. when sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a2w2 to a2w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a2s0 and bits a2h1 and a2h0 in the wcr3 register. when synchronous dram interface is set, the ras and cas signals, rd/ wr signal, and byte control signals dqm0 to dqm3 are asserted, and address multiplexing is performed. ras , cas , and data timing control, and address multiplexing control, can be set using the mcr register. area 3: for area 3, external addres s bits 28 to 26 are 011. sram, mpx, dram, and synchronous dram, can be set to this area. when sram interface is set, a bus width of 8, 16, or 32 bits can be selected with bits a3sz1 and a3sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 bit should be selected with bits a3sz1 and a3sz0 in the bcr2 register. wh en dram interface is set, 16 or 32 bits can be selected with the sz bits in the mcr register . when synchronous dram interface is set, select 32 bit with the sz bits in mcr. for details, see memory bus width in section 13.1.5, overview of areas. when area 3 is accessed, the cs3 signal is asserted. when sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 402 of 1122 rej09b0370-0400 as regards the number of bus cycles, from 0 to 15 waits can be selected w ith bits a3w2 to a3w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a3s0 and bits a3h1 and a3h0 in the wcr3 register. when synchronous dram interface is set, the ras and cas signals, rd/ wr signal, and byte control signals dqm0 to dqm3 are asserted, and address multiplexing is performed. when dram interface is set, the ras signal, cas0 to cas3 signals, and rd/ wr signal are asserted, and address multiplexing is performed. ras , cas , and data timing control, and address multiplexing control, can be set using the mcr register. area 4: for area 4, physical addres s bits 28 to 26 are 100. sram, mpx, and byte control sram can be set to this area. a bus width of 8, 16, or 32 bits can be selected with bits a4sz1 and a4sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 bit should be sel ected with bits a4sz1 and a4sz0 in the bcr2 register. when byte co ntrol sram interface is set, select a bus width of 16 or 32 bits. for details, see memory bus width in section 13.1.5, overview of areas. when area 4 is accessed, the cs4 signal is asserted, and the rd signal, which can be used as oe , and write control signals we0 to we3 , are also asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected w ith bits a4w2 to a4w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a4s0 and bits a4h1 and a4h0 in the wcr3 register.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 403 of 1122 rej09b0370-0400 area 5: for area 5, external addres s bits 28 to 26 are 101. sram, mpx, burst rom, and a pcmcia interface can be set to this area. when sram interface is set, a bus width of 8, 16, or 32 bits can be selected with bits a5sz1 and a5sz0 in the bcr2 register. when bur st rom interface is set, a bus wi dth of 8, 16 or 32 bits can be selected with bits a5sz1 and a5sz0 in bcr2. when mpx interface is set, a bus width of 32 bit should be selected with bits a5sz1 and a5sz0 in bcr2. when a pc mcia interface is set, either 8 or 16 bits should be selected with bits a5sz1 and a5sz0 in bcr2. for details, see memory bus width in section 13.1.5, overview of areas. when area 5 is accessed with sram interface set, the cs5 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted. when a pcmcia interface is connected, the ce1a and ce2a signals, the rd signal, which can be used as oe , and the we1 , we2 , we3 , and we0 signals, which can be used as we , iciord , iciowr , and reg , respectively, are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected wi th bits a5w2 to a5w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst function is used, the number of bu rst cycle transfer states is determined in the range 2 to 9 according to the number of waits. the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a5s0 and bits a5h1 and a5h0 in the wcr3 register. when a pcmcia interface is used, the address ce1a and ce2a setup and hold times with respect to the read/write strobe si gnals can be set in the range of 0 to 15 cycles with bits anted1 and anted0, and bits anteh1 and anteh0, in th e pcr register. in addition, the number of wait cycles can be set in the range 0 to 50 with bits anpcw1 and anpcw0. the number of waits set in pcr is added to the number of waits set in wcr2.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 404 of 1122 rej09b0370-0400 area 6: for area 6, external addres s bits 28 to 26 are 110. sram, mpx, burst rom, and a pcmcia interface can be set to this area. when sram interface is set, a bus width of 8, 16, or 32 bits can be selected with bits a6sz1 and a6sz0 in the bcr2 register. when bur st rom interface is set, a bus wi dth of 8, 16 or 32 bits can be selected with bits a6sz1 and a6sz0 in bcr2. when mpx interface is set, a bus width of 32 bit should be selected with bits a6sz1 and a6sz0 in bcr2. when a pc mcia interface is set, either 8 or 16 bits should be selected with bits a6sz1 and a6sz0 in bcr2. for details, see memory bus width in section 13.1.5, overview of areas. when area 6 space is accessed with sram interface set, the cs6 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 , are asserted. when a pcmcia interf ace is connected, the ce1b and ce2b signals, the rd signal, which can be used as oe , and the we1 , we2 , we3 , and we0 signals, which can be used as we , iciord , iciowr , and reg , respectively, are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected w ith bits a6w2 to a6w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst function is used, the number of bu rst cycle transfer states is determined in the range 2 to 9 according to the number of waits. the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a6s0 and bits a6h1 and a6h0 in the wcr3 register. when a pcmcia interface is used, the address / ce1b / ce2b setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits anted1 and anted0, and bits anteh1 and anteh0, in the pcr register. in addition, the number of wait cycles can be set in the range 0 to 50 with bits anpcw1 and anpcw0. the number of waits set in pcr is added to the number of waits set in wcr2.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 405 of 1122 rej09b0370-0400 13.3.3 sram interface basic timing: the sram interface of this lsi uses strobe signal output in consideration of the fact that mainly sram will be connected. figu re 13.6 shows the sram timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. the csn signal is asserted on the t1 rising edge, and negated on the next t2 clock risi ng edge. therefore, there is no negation period in case of access at minimum pitch. there is no access size specification when readin g. the correct access address is output to the address pins (a[25:0]), but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit de vice. when wri ting, only the we signal for the byte to be written is asserted. fo r details, see section 13.3 .1, endian/access size and data alignment. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wraparound mode on the data at the 32-byte boundary. the bus is not released during this transfer.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 406 of 1122 rej09b0370-0400 t1 ckio a25?a0 csn rd/ wr rd d31?d0 (read) wen d31?d0 (write) bs t2 rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) le g end: sa: da: sin g le address dma dual address dma figure 13.6 basic timi ng of sram interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 407 of 1122 rej09b0370-0400 figures 13.7, 13.8, and 13.9 show examples of connection to 32-, 16-, and 8-bit data width sram. ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 sh7751/sh7751r 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? figure 13.7 example of 32-bi t data width sram connection
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 408 of 1122 rej09b0370-0400 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 d7 d0 we0 sh7751/sh7751r 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? figure 13.8 example of 16-bi t data width sram connection
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 409 of 1122 rej09b0370-0400 a16 a0 csn rd d7 d0 we0 sh7751/sh7751r 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? ???? figure 13.9 example of 8-bi t data width sram connection wait state control: wait state insertion on the sram inte rface can be controlled by the wcr2 settings. if the wcr2 wait speci fication bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. for details, see section 13.2.6, wait control register 2 (wcr2). the specified number of tw cycl es are inserted as wait cycles using the sram interface wait timing shown in figure 13.10.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 410 of 1122 rej09b0370-0400 t1 ckio a25?a0 csn rd/ wr rd d31?d0 (read) wen d31?d0 (write) bs tw t2 rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.10 sram interface wa it timing (software wait only)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 411 of 1122 rej09b0370-0400 when software wait insertion is specified by wcr2, the external wait input rdy signal is also sampled. rdy signal sampling is shown in figure 13.1 1. a single-cycle wait is specified as a software wait. sampling is performed at the transiti on from the tw state to the t2 state; therefore, the rdy signal has no effect if asserted in th e t1 cycle or the first tw cycle. the rdy signal is sampled on the rising edge of the clock. t1 ckio a25?a0 csn rd/ wr rd (read) d31?d0 (read) wen (write) d31?d0 (write) bs tw twe t2 rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.11 sram interface wait st ate timing (wait state insertion by rdy signal)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 412 of 1122 rej09b0370-0400 read-strobe negate timing (setting only possible in the sh7751r): when the sram interface is used, timing for the negation of the stro be during read operatio ns can be specified by the setting of the a1rdh and a4rdh bits of the wcr3 register. for information about this setting, see the description of the wcr3 register. when a byte control sram setting is made, anrdh should be cleared to 0. ts1 ckio a25?a0 csn rd/ wr rd d31?d0 bs t1 tw tw tw tw t2 th1 th2 * ts1: setup wait wcr3.ans (0 to 1) tw: access wait wcr2.anw (0 to 15) th1, th2: hold wait wcr3.anh (0 to 3) note: * when anrdh is set to 1 figure 13.12 sram interface read strobe negate timing (ans = 1, anw = 4, and anh = 2)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 413 of 1122 rej09b0370-0400 13.3.4 dram interface direct connection of dram: when the memory type bits (dramtp2?0) in bcr1 are set to 100, area 3 becomes dram interface. the dram interface function can then be used to connect dram to this lsi. 16 or 32 bits can be selected as the interface data width. 2-cas 16-bit drams can be connected, since cas is used to control byte access. signals used for connection are cs3 , ras , cas0 to cas3 , and rd/ wr . cas2 to cas3 are not used when the data width is 16 bits. in addition to normal read and write access modes, fast page mode is supported for burst access. edo mode, which enables the dram access time to be increased, is supported. a10 a2 ras cs3 rd/ wr d31 d16 cas3 cas2 d15 d0 cas1 cas0 sh7751/sh7751r 256k 16-bit dram a8 a0 ras oe we i/o15 i/o0 ucas lcas a8 a0 ras oe we i/o15 i/o0 ucas lcas ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? figure 13.13 example of dram connection (32-bit data width, area 3)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 414 of 1122 rej09b0370-0400 address multiplexing: when area 3 is designated as dram interface, address multiplexing is always performed in accesses to dram. this enables dram, wh ich requires row and column address multiplexing, to be connected to this lsi without using an external address multiplexer circuit. any of the five multiplexing methods shown below can be selected, by setting bits amxext and amx2?0 in mcr. the relationship between the amxext and amx2?0 bits and address multiplexing is shown in table 13.14. the address output pins subject to address multiplexing are a17 to a1. the address signals output by pins a25 to a18 are undefined. table 13.14 relationship between amxext a nd amx2?0 bits and address multiplexing setting external address pins amxext amx2 amx1 amx0 number of column address bits output timing a1?a13 a14 a15 a16 a17 0 0 0 0 8 bits column address a1?a13 a14 a15 a16 a17 row address a9?a21 a22 a23 a24 a25 1 9 bits column address a1?a13 a14 a15 a16 a17 row address a10?a22 a23 a24 a25 a17 1 0 10 bits column address a1?a13 a14 a15 a16 a17 row address a11?a23 a24 a25 a16 a17 1 11 bits column address a1?a13 a14 a15 a16 a17 row address a12?a24 a25 a15 a16 a17 1 0 0 12 bits column address a1?a13 a14 a15 a16 a17 row address a13?a25 a14 a15 a16 a17 other settings reserved ? ? ? ? ? ?
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 415 of 1122 rej09b0370-0400 basic timing: the basic timing for dram access is 4 cycles. this basic timing is shown in figure 13.14. tpc is the precharge cycle, tr the ras assert cycle, tc1 the cas assert cycle, and tc2 the read data latch cycle. tr1 ckio address csn rd/ wr ras d31?d0 (read) casn d31?d0 (write) bs tr2 tc1 tc2 tpc row column dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer the dack is in the hi g h-active settin g note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.14 basi c dram access timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 416 of 1122 rej09b0370-0400 wait state control: as the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. therefore, provision is made for stat e extension by using the setting bits in wcr2 and mcr. the timing with state extension using these settings is shown in figure 13.15. additional tpc cycles (cycles used to secure the ras precharge time) can be inserted by means of the tpc bit in mcr, giving from 1 to 7 cycles. the number of cycles from ras assertion to cas assertion can be set to between 2 and 5 by inserting trw cycles by means of the rcd bit in mcr. also, th e number of cycles from cas assertion to the end of the access can be varied between 1 and 16 according to the setting of a3w2 to a3w0 in wcr2. tr1 ckio address csn rd/ wr ras d31?d0 (read) casn d31?d0 (write) bs tr2 trw tc1 tcw tc2 tpc tpc dackn (sa: io memory) dackn (sa: io memory) column row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.15 dram wait state timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 417 of 1122 rej09b0370-0400 burst access: in addition to the normal dram access mo de in which a row address is output in each data access, a fast page mode is also pr ovided for the case where consecutive accesses are made to the same row. this mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. normal access or burst access using fast page mode can be selected by means of the burst enable (be) bit in mcr. the timing for burst access using fast page mode is shown in figure 13.16. if the access size exceeds the set bus width, burst access is performed. in a 32-byte transfer, the first access comprises a longword that includes the data requiring access. the remaining accesses are performed on 32-byte boundary data that includes the relevant data. in burst transfer, wraparound writing is performed for 32-byte data. tr2 tc1 tc2 tc1 tc2 tc2 tr1 row c1 c2 c8 tc1 tpc tc2 tc1 ckio address csn rd/ wr ras casn d31?d0 (read) d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) d8 d2 d2 d1 d1 d8 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.16 dram burst access timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 418 of 1122 rej09b0370-0400 edo mode: with dram, in addition to the mode in which data is output to the data bus only while the cas signal is asserted in a data read cycle, an edo (extended data out) mode is also provided in which, once the cas signal is asserted while the ras signal is asserted, even if the cas signal is negated, data is output to the data bus until the cas signal is next asserted. in this lsi, the edo mode bit (edomode) in mcr enable s either normal access/burst access using fast page mode, or edo mode norm al access/burst access, to be selected for dram. when edo mode is set, be must be set to 1 in mcr. ed o mode normal access is show n in figure 13.17, and burst access in fi gure 13.18. cas negation period: the cas negation period can be set to 1 or 2 by means of the tcas bit in the mcr register. tr1 tc1 tc2 tce tpc tr2 ckio address csn rd/ wr ras casn d31?d0 (read) bs dackn (sa: io memory) row column note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.17 dram bus cycle (edo mode, rcd = 0, anw = 0, tpc = 1)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 419 of 1122 rej09b0370-0400 tr1 c1 c2 c8 tc1 tc2 tc1 tc2 tc1 tc1 tr2 tc2 tc2 tpc tce ckio address csn rd/ wr ras casn d31?d0 (read) bs dackn (sa: io memory) d8 d2 d1 row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.18 burst access timing in dram edo mode ras down mode: this lsi has an address comparator for detecting row address matches in burst mode. by using this address comparator, and also setting ras down mode specification bit rasd to 1, it is possible to select ras down mode, in which ras remains asserted after the end of an access. when ras down mode is used, if the re fresh cycle is longer than the maximum dram ras assert time, the refresh cycle must be d ecreased to or below th e maximum value of t ras . in ras down mode, in the event of an access to an address with a different row address, an access to a different area, a refresh request, or a bus release request, ras is negated and the necessary operation is performed. when dram access is resume d after this, since this is the start of ras down mode, the operation starts with row address output. timing charts are shown in figures 13.19 (1), (2), (3), and (4).
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 420 of 1122 rej09b0370-0400 tr1 tr2 tc1 tc2 tc1 tc1 tpc row c1 c2 c8 tc2 tc2 tc1 tc2 ckio address csn rd/ wr ras casn d31?d0 (read) d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) d8 d2 d1 d8 d2 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.19 (1) dram burst bu s cycle, ras down mode start (fast page mode, rcd = 0, anw = 0)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 421 of 1122 rej09b0370-0400 tnop tc1 tc2 tc1 tc2 tc1 tc1 tc2 tc2 ckio address csn rd/ wr ras casn d31?d0 (read) d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) c1 c2 c8 d1 d1 d2 d8 d2 d8 end of ras down mode note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.19 (2) dram burst bus cy cle, ras down mode continuation (fast page mode, rcd = 0, anw = 0)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 422 of 1122 rej09b0370-0400 tpc tr2 tc1 tc2 tc1 tc2 tc2 tr1 c1 c2 c8 tc1 tc1 tce tc2 ckio address csn rd/ wr ras casn d31?d0 (read) bs dackn (sa: io memory) d8 d2 d1 row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.19 (3) dram burst bu s cycle, ras down mode start (edo mode, rcd = 0, anw = 0)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 423 of 1122 rej09b0370-0400 tc2 tc1 tc2 tc1 tc2 tc2 tc1 c1 c2 c8 tc1 tnop tce ckio address csn rd/ wr ras casn d31?d0 (read) bs dackn (sa: io memory) d8 d2 d1 end of ras down mode note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.19 (4) dram burst bus cy cle, ras down mode continuation (edo mode, rcd = 0, anw = 0)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 424 of 1122 rej09b0370-0400 refresh: the bus state controller includes a f unction for controlling dram refreshing. distributed refreshing using a cas-before-ras cycle can be performed for dram by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. self-refresh mode is also supported. ? cas-before-ras refresh when cas-before-ras refresh cycles are execu ted, refreshing is performed at intervals determined by the input clock selected by bits cks2?cks0 in rtcsr, and the value set in rtcor. the value of bits cks2?cks0 in rt cor should be set so as to satisfy the specification for the dram refresh interval. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2?cks0 setting. when the clock is selected by cks2?cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and the back pin goes high. if this lsi external bus can be used, cas-before-ras refreshing is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 13.20 shows the operation of cas-before-ras refreshing. rtcnt value rtcor-1 h'00000000 rtcsr.cks2?0 external bus refresh request cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor cas-before-ras refresh cycle time refresh request figure 13.20 cas-before -ras refresh operation figure 13.21 shows the timing of the cas-before-ras refresh cycle. the number of ras assert cycles in the refresh cycle is speci fied by bits tras2?tras0 in mcr. the specification of the ras precharge time in the refresh cycle is determined by the setting of bits trc2?trc0 in mcr.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 425 of 1122 rej09b0370-0400 trr2 trr3 trr4 trr5 trc trr1 trc trc ckio a25?a0 csn rd/ wr ras cas d31?d0 bs figure 13.21 dram cas-before-ras ref resh cycle timing (tras = 0, trc = 1) ? self-refresh the self-refreshing supported by this lsi is shown in figure 13.22. after the self-refresh is cleared, the refresh c ontroller immediately generates a refresh request. the ras precharge time immediately after the end of the self-refreshing can be set by bits trc2?trc0 in mcr. cas-before-ras refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. when the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the ras and cas signals become high-impedance or continue to be output can be controlled by the hizcnt bit in bcr1. this enables the dram to be kept in the self-refreshing state.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 426 of 1122 rej09b0370-0400 ? relationship between refresh requests and bus cycle requests if a refresh request is generated during executio n of a bus cycle, execu tion of the refresh is deferred until the bus cycle is completed. refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width me mory) and during a 32-b yte transfer such as a cache fill or write-back, and al so between read and write cycl es during execu tion of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a ma tch between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refr eshing to be performed normally, care must be taken to ensure that no bus cycle or bus master ship occurs that is longer than the refresh interval. when a refresh request is generated, the back pin is negated (driven high). therefore, normal refreshing can be performed by having the back pin monitored by a bus master other than this lsi requesting the bus, or the bus arbiter, and returning the bus to this lsi. trr2 trr3 trr4 trr5 trc trr1 trc trc ckio a25?a0 csn rd/ wr ras cas d31?d0 bs figure 13.22 dram se lf-refresh cycle timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 427 of 1122 rej09b0370-0400 power-on sequence: regarding use of dram after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy cas-before-ras refresh cycles. as the bus state controller does not perfor m any special operations for a powe r-on reset, the necessary power- on sequence must be carried out by the initializa tion program executed after a power-on reset. 13.3.5 synchronous dram interface direct connection of synchronous dram: since synchronous dram can be selected by the cs signal, it can be connected to exte rnal memory space areas 2 and 3 using ras and other control signals in common. if the memory type bits (dramtp2?0) in bcr1 are set to 010, area 3 is synchronous dram interface; if set to 011, areas 2 and 3 are both synchronous dram interface. this lsi supports burst read and burst write operations with a burst length of 4 as a synchronous dram operating mode. the data bus width is 32 bit, and the sz size bits in mcr must be set to 11. the burst enable bit (be) in mcr is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle. in write-through area write operations and non-cacheable area read/write operations, 16-byte data is read even in a single read because accessing synchronous dram is by burst-length 4 burst read/write operations. 16-byte data transfer is also performed in a single write, but dqmn is not asserted when un necessary data is transferred. in the sh7751r, an 8-burst-length burst read/burst write mode is also supported as a synchronous dram operating mode. the data bus width is 32 bits, and the sz size bits in mcr must be set to 11. burst enable bit be in mcr is ignored, and a 32-byte burst transfer is performed in a cache fill/copy-back cycle. for write -through area write s and non-cacheable ar ea reads/writes, synchronous dram is accessed with an 8-burst-length bu rst read/write, and therefore 32 bytes of data are read even in the case of a single read. in the case of a single write, 32-byte data transfer is performed but dqmn is not asserted in the case of an unnecessary data transfer. for a description of the case where an 8-burst-length setting is made, see section 13.3.6, burst rom interface. for information on the burst length, see section 13.2.10, synchronous dram mode register (sdmr), and section 13.3 .5, power-on sequence. the control signals for connection of synchronous dram are ras , cass , rd/ wr , cs2 or cs3 , dqm0 to dqm3, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and latched only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (driven low) when the frequency is changed, when the clock is unstable after the clock supply is stopped and restarted, or when self-refreshing is performed, an d is always asserted (high) at other times.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 428 of 1122 rej09b0370-0400 commands for synchronous dram are specified by ras , cass , rd/ wr , and specific address signals. the commands are nop, au to-refresh (ref), self-refresh (self), precharge all banks (pall), precharge specified bank (pre), row address strobe bank active (actv), read (read), read with precharge (reada), wr ite (writ), write with precharg e (writa), and mode register setting (mrs). byte specification is performed by dqm0 to dqm3. a read/write is performed for the byte for which the corresponding dqm signal is low. when the bus width is 32 bits, in big-endian mode dqm3 specifies an access to address 4n, and dqm0 specifies an access to address 4n + 3. in little-endian mode, dqm3 specifies an access to address 4n + 3, and dqm0 specifies an access to address 4n. figure 13.23 shows examples of the connection of 16m 16-bit synchronous drams. a11?a2 ckio cke cs3 ras cass rd/ wr d31?d16 dqm3 dqm2 sh7751/sh7751r 512k 16-bit 2-ban k synchronous dram a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml d15?d0 dqm1 dqm0 a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml figure 13.23 example of 32-bit data wi dth synchronous dram connection (area 3)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 429 of 1122 rej09b0370-0400 address multiplexing: synchronous dram can be connect ed without external multiplexing circuitry in accordance with the address multiplex specification bits amxext and amx2? amx0 in mcr. table 13.15 shows the relationship between the address multiplex specification bits and the bits output at the address pins. see appendix e, synchronous dram address multiplexing tables. the address signals output at address pins a25?a18, a1, and a0 are not guaranteed. when a0, the lsb of the synchronous dram addr ess, is connected to this lsi, it makes a longword address specification. connection should therefore be made in this order: connect pin a0 of the synchronous dram to pin a2 of this lsi, then connect pin a1 to pin a3. table 13.15 example of correspondence be tween lsi and synchronous dram address pins (32-bit bus width, amx2?amx0 = 000, amxext = 0) lsi address pin synchronous dram address pin ras cycle cas cycle function a13 a21 a21 a11 bank select bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 address a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 a1 not used not used not used a0 not used not used not used burst read: the timing chart for a burst read is shown in figure 13.24. in the following example it is assumed that two 512k 16-bit 2-bank synchronous drams are connected, and a 32-bit data width is used. the burst length is 4. after the tr cycle in which the actv command is output, a read command is issued in the tc1 cy cle and, 4 cycles after that, a reada command is issued and read data is fetched on the rising edge of the external command clock (ckio) from cycle td1 to cycle td8. the tpc cycle is used to wait for completion of auto-precharge based on
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 430 of 1122 rej09b0370-0400 the reada command inside the synchronous dr am; no new access command can be issued to the same bank during this cycle. in this lsi, the number of tpc cycles is determined by the specification of bits tpc2?tpc 0 in mcr, and commands are not issued for the synchronous dram during this interval. the example in figure 13.24 sh ows the basic cycle. to connect slower synchronous dram, the cycle can be extended by setting wcr2 and mcr bits. the number of cycles from the actv command output cycle, tr, to the read command output cycle, tc 1, can be specified by bits rcd1 and rcd0 in mcr, with a value of 0 to 3 sp ecifying 2 to 4 cycles, re spectively. in the case of 2 or more cycles, a trw cycle, in which an nop command is issued for the synchronous dram, is inserted between the tr cycle and the tc cycle. the number of cycles from read command output cycle tc1 to the first read data latc h cycle, td1, can be speci fied as 1 to 5 cycles independently for areas 2 and 3 by means of bits a2w2?a2w0 and a3w2?a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 431 of 1122 rej09b0370-0400 tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank precharge-sel address csn rd/ wr ras cass d31?d0 (read) dqmn bs dackn (sa: io memory) cke h/l c5 td5 td6 td8 td7 tpc c1 c1 c2 c3 c4 c5 c6 row row row c7 c8 h/l note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.24 basic timing for synchronous dram burst read
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 432 of 1122 rej09b0370-0400 in a synchronous dram cycle, the bs signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a read or reada command. data are accessed in the following sequence: in the fill op eration for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial read command; after that, the data between 16-bit boundaries data that include the missing data are read in a wraparound way. the subsequently issued reada command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries. single read: with this lsi, as synchronous dram is set to burst read/burst write mode, read data output continues after the required data has been read. to prevent data collisions, after the required data is read in td1, empty read cycles td2 to td4 are performed, and this lsi waits for the end of the synchronous dram operation. the bs signal is asserted only in td1. there are 4 burst tr ansfers in a read. in cache-through and other dma read cycles, of cycles td1 to td4. since such empty cycles increase the memory acce ss time, and tend to reduce program execution speed and dma transfer speed, it is importan t both to avoid unnece ssary cache-through area accesses, and to use a data structure that will allo w data to be placed at a 32-byte boundary, and to be transferred in 32-byte units, when carrying out dma transfer with synchronous dram specified as the source.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 433 of 1122 rej09b0370-0400 tr tc1 tc2 c1 tc3 tc4/td1 td2 td4 trw c1 td3 tpc ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke dackn (sa: io memory) row row row h/l note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.25 basic timing for synchronous dram single read burst write: the timing chart for a burst write is shown in figure 13.26. in this lsi, a burst write occurs only in the event of 32-byte transfer. in a burst write operation, the writ command is issued in the tc1 cycle following the tr cycle in which the actv command is output and, 4 cycles later, the writa command is issued. in the write cy cle, the write data is output at the same time as the write command. in the case of the wr ite with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for th e same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the wr ite command. issuance of a new command for the synchronous dram is postponed during this interval. the number of trwl cycles can be specified by bits trwl 2?trwl0 in mcr. access starts from 16-byte
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 434 of 1122 rej09b0370-0400 boundary data, and 32-byte boundary data is written in wraparound mode. dack is asserted two cycles before the data write cycle. tr tc1 tc2 tc3 tc4 tc5 tc7 trw c1 tc6 ckio bank prechar g e-sel address csn dqmn rd/wr ras cass d31?d0 (write) bs cke dackn (sa: io memory) c1 c2 c3 c4 c5 c6 c7 c8 row row tc8 trw1 tpc trw1 h/l h/l c5 row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.26 basic timing fo r synchronous dram burst write
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 435 of 1122 rej09b0370-0400 single write: the basic timing chart for write access is sh own in figure 13.27. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto -precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write comman d. in the case of a write with auto-precharge, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the synchronous dram until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by bits trwl2?trwl0 in mcr. dack is asserted two cycles before the data write cycle. this lsi supports burst-length 4 burst read and burst write operations of synchronous dram. a wait cycle is therefore generated ev en with single write operations.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 436 of 1122 rej09b0370-0400 tr tc1 tc2 tc3 tc4 trwl tpc trw h/l c1 trwl ckio bank precharge-sel address csn dqmn rd/wr ras cass d31?d0 (write) bs cke dackn (sa: io memory) c1 row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.27 basic timing for synchronous dram single write
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 437 of 1122 rej09b0370-0400 ras down mode: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the rasd bit in mcr is 1, read/write command accesses are performed using commands without auto-precharge (read, writ). in this case, precharging is not performed when the access ends. when accessing the same row addr ess in the same bank, it is possible to issue the read or writ command immediately, without issuing an actv command, in the same way as in the dram ras down state. as synchronous dram is internally divided into two or four banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is pe rformed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharg ing performed after the access request is issued. in a write, when auto-precharge is performed, a command cannot be issued for a period of trwl + tpc cycles after issuance of the writa comman d. when ras down mode is used, read or writ commands can be issued successively if the row address is the same. the number of cycles can thus be reduced by trwl + tpc cycles for each write . the number of cycl es between issuance of the pre command and the actv command is determined by bits tpc2?tpc0 in mcr. there is a limit on t ras , the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another ro w address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more th an the maximum value of t ras . in this way, it is possible to observe the restrictions on the maximum activ e state time for each bank. if auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. a burst read cycle without auto-precharge is shown in figure 13.28, a burst read cycle for the same row address in figure 13.29, and a burst read cy cle for different row addresses in figure 13.30. similarly, a burst write cycle without auto-precharge is shown in figure 13.31, a burst write cycle for the same row address in figure 13.32, and a burst write cycle for different row addresses in figure 13.33. when synchronous dram is read, there is a 2-cycle latency for the dmqn signal that performs the byte specification. as a result, when the read command is issued in figure 13.28, if the tc cycle is executed immediately, the dmqn signal sp ecification for td1 cycle data output cannot be carried out. therefore, the cas latency should not be set to 1. when ras down mode is set, if only accesses to the respective bank s in area 3 are considered, as long as accesses to the same row address continue, the operation star ts with the cycle in figure 13.28 or 13.31, followed by re petition of the cycle in figure 13.29 or 13.32. an access to a different area during this time has no effect. if th ere is an access to a different row address in the bank active state, after this is de tected the bus cycle in figure 13.3 0 or 13.33 is executed instead of
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 438 of 1122 rej09b0370-0400 that in figure 13.29 or 13.32. in ras down mode, too, a pall command is issued before a refresh cycle or before bus releas e due to bus arbitration. c2 c3 c4 tr tc1 tc2 c1 c6 c7 c8 c5 tc3 tc4/td1 td2 td4 td5 trw h/l c1 h/l c5 td3 td6 td8 td7 ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.28 burst read timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 439 of 1122 rej09b0370-0400 c2 c3 c4 tc1 tc3 tc4/td1 c1 c5 c6 c7 c8 td2 td3 td4 tc2 h/l c1 h/l c5 td5 td6 td7 td8 ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.29 burst read timing (ras down, same row address)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 440 of 1122 rej09b0370-0400 tpr tr trw c1 c2 c3 c4 c5 c6 c7 c8 tc1 tc2 tc3 td2 tpc h/l h/l c1 c5 tc4/td1 td3 td4 td5 td6 td7 td8 ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.30 burst read timing (ras down, differen t row addresses)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 441 of 1122 rej09b0370-0400 tr tc1 tc2 tc3 tc4 tc5 trw h/l h/l c1 c5 tc6 tc7 tc8 trwl trwl ckio bank precharge-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke c1 c2 c3 c4 c5 c6 c7 c8 row row row dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.31 burst write timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 442 of 1122 rej09b0370-0400 (tnop) tc2 tc3 tc4 tc5 tc6 tc1 h/l h/l c1 c5 tnop tc7 tc8 trwl trwl ckio bank precharge-sel address csn dqmn rd/ wr ras cass d31?d0 (write) bs cke c1 c2 c3 c4 c5 c6 dackn (sa: io memory) note: c8 c7 normal write single address dma the (tnop) cycle is inserted only for sa-dma. the dackn signal is output as indicated by the solid line. in the case of a normal write, the (tnop) cycle is deleted and the dackn signal is output as indicated by the dotted line. for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.32 burst write timing (same row address)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 443 of 1122 rej09b0370-0400 tpr tr trw tc1 tc2 tc3 tpc h/l h/l c1 c5 tc4 tc5 tc6 tc7 tc8 trwl trwl ckio bank precharge-sel address csn dqmn rd/ wr ras cass d31?d0 (write) bs cke dackn (sa: io memory) c1 c2 c3 c4 c5 c6 c7 c8 row h/l row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.33 burst write timi ng (different row addresses)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 444 of 1122 rej09b0370-0400 pipelined access: when the rasd bit is se t to 1 in mcr, pipelined access is performed between an access by the cpu and an access by the dmac, or in the case of consecutive accesses by the dmac, to provide faster access to synchronous dram. as synchronous dram is internally divided into two or four banks, after a read or writ command is issued for one bank it is possible to issue a pre, actv, or other command during the cas latency cycle or data latch cycle, or during the da ta write cycle, and so shorten the access cycle. when a read access is followed by another read access to the same row address, after a read command has been issued, another read command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously. when an access is made to another row address and the bank is different, the pre command or actv command can be issued during the cas latency cycle or data latch cycle. if th ere are consecutive access requests for different row addresses in the same bank, the pre command cannot be issued until the last-but-one data latch cycle. if a read access is followed by a write acce ss, it may be possible to issue a pre or actv command, depending on the bank and row address, but since the write data is output at the same time as the writ command, the pre, actv, and writ commands are issued in such a way that one or two empty cycles occur automatically on the data bus. similarly, with a read access following a write access, or a write access followi ng a write access, the pre, actv, read, or writ command is issued during the data write cycle for the preceding ac cess; however, in the case of different row addresses in the same bank, a pre command cannot be issued, and so in this case the pre command is issued fo llowing the number of trwl cycl es specified by the trwl bits in mcr, after the end of the last data write cycle. figure 13.34 shows a burst read cycle for a different bank and row address following a preceding burst read cycle. pipelined access is enabled only fo r consecutive access to area 3, an d will be discontinued in the event of an access to another area. pipelined access is also discontinued in the event of a refresh cycle, or bus release due to bus arbitration. the cases in which pipelined access is available are shown in table 13.16. in this table, ?dmac dual? indicates transfer in dmac dual address mode, and ?dmac single?, transfer in dmac single address mode.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 445 of 1122 rej09b0370-0400 table 13.16 cycles in which pipelined access can be used following access cpu dmac dual dmac single preceding access read write read write read write cpu read x x o x o o write x x o x o o dmac dual read x x x x x x write o o o x o o dmac single read o o o x o o write o o o x o o legend: o: pipelined access possible x: pipelined access not possible
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 446 of 1122 rej09b0370-0400 tc1_a tc1_b h/l h/l h/l ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (read) bs cke a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 c1_a c5_a c1_b c5_b h/l figure 13.34 burst read cy cle for different bank and ro w address following preceding burst read cycle
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 447 of 1122 rej09b0370-0400 refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. ? auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2? cks0 in rtcsr, and the value set in rtco r. the value of bits cks2?cks0 in rtcor should be set so as to satisfy the refresh interval specification for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2?cks0 setting last of all. when the clock is selected by cks2?cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the tw o values are the same, a refresh request is generated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 13.36 shows the au to-refresh cycle timing. first, an ref command is issued in the trr cy cle. after the trr cycle, new command output cannot be performed for the duration of the numb er of cycles specified by bits tras2?tras0 in mcr plus the number of cycles specifi ed by bits trc2?trc0 in mcr. the tras2? tras0 and trc2?trc0 bits must be set so as to satisfy the synchronous dram refresh cycle time specification (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. when both areas 2 and 3 are set to the sy nchronous dram, auto-refreshing of area 2 is performed subsequent to area 3.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 448 of 1122 rej09b0370-0400 rtcnt value rtcor-1 h'00000000 rtcsr.cks2?0 external bus refresh request cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor auto-refresh cycle time refresh request figure 13.35 auto-refresh operation trr2 trr3 trr4 trr5 trc trr1 trc trrw trc ckio csn rd/ wr ras dqmn bs cke d31?d0 cass figure 13.36 synchronous dram auto-refresh timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 449 of 1122 rej09b0370-0400 ? self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. synchronous dram cannot be accessed wh ile in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled fo r the number of cycles specified by bits trc2?trc0 in mcr. self-refresh timing is shown in figure 13.37. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-re freshing is activated from the st ate in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if rfsh is set to 1 and rmode is clear ed to 0 when self-refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto-refre shing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will en able refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this lsi standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in the case of a power-on reset, the bus state c ontroller's registers are initialized, and therefore the self-refresh state is cleared. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 450 of 1122 rej09b0370-0400 trs2 trs3 trs4 trs5 trc trs1 trc trc ckio csn rd/ wr ras dqmn bs cke d31?d0 cass figure 13.37 synchronous dram self-refresh timing ? relationship between refresh requests and bus cycle requests if a refresh request is generated during executio n of a bus cycle, executi on of the refresh is deferred until the bus cycle is completed. refres h operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width me mory) and during a 32-b yte transfer such as a cache fill or write-back, and al so between read and write cycl es during execu tion of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a ma tch between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refr eshing to be performed normally, care must be taken to ensure that no bus cycle or bus master ship occurs that is longer than the refresh interval. when a refresh request is generated, the back pin is negated (driven high). therefore, normal refreshing can be performed by having the back pin monitored by a bus master other than this lsi requesting the bus, or the bus arbiter, and returning the bus to this lsi.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 451 of 1122 rej09b0370-0400 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the addr ess signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ff900000 + x for area 2 synchronous dram, and to address h'ff940000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/burst write, cas latency 1 to 3, wrap type = sequential, and burst length 4, 8 * , supported by this lsi, arbitrary data is written by byte-size access to the following addresses. bus width cas latency area 2 area 3 32 4 1 h'ff900048 h'ff940048 2 h'ff900088 h'ff940088 3 h'ff9000c8 h'ff9400c8 32 8 * 1 h'ff90004c h'ff94004c 2 h'ff90008c h'ff94008c 3 h'ff9000cc h'ff9400cc note: * sh7751r only the value set in mcr.mrset is used to select whether a precharge all banks command or a mode register setting command is issued. the timing for the precharge all banks command is shown in figure 13.38 (1), and the timing for the mode register setting command in figure 13.38 (2). before mode register, a 200 s idle time (depending on the memory manufacturer) must be guaranteed after the power required for the synchronous dram is turned on. if the reset signal pulse width is greater than this idle time, there is no problem in making the precharge all banks setting immediately. first, a precharge all banks (pall) command is issu ed in the trp1 cycle by performing a write to address h'ff900000 + x or h'ff940000 + x while mcr.mrset = 0. next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. this is achieved automatically while various kinds of initialization are being performed after auto- refresh setting, but a way of carrying this out more dependably is to change the rtcor register value to set a short refresh request generation in terval just while these dummy cycles are being executed. with simple read or write access, the address counter in the synchronous dram used for auto-refreshing is not initialized, and so the cycl e must always be an auto-refresh cycle. after auto-refreshing has been executed at least the pres cribed number of times, a mode register setting
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 452 of 1122 rej09b0370-0400 command is issued in the tmw1 cycle by setti ng mcr.mrset to 1 and performing a write to address h'ff900000 + x or h'ff940000 + x. synchronous dram mode register setting should be executed once only after power-on reset and before synchronous dram access, and no subsequent changes should be made. ckio bank prechar g e-sel address csn rd/ wr ras cass d31?d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (hi g h) tmw5 figure 13.38 (1) synchronous dram mode write timing (pall)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 453 of 1122 rej09b0370-0400 ckio bank prechar g e-sel address csn rd/ wr ras cass d31?d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (hi g h) tmw5 figure 13.38 (2) synchronous dram mode write timing (mode register setting) changing the burst length (sh7751r only): when synchronous dram is connected with the 32-bit memory bus of the sh7751r, a burst length of either 4 or 8 can be selected by the setting of the sdbl bit of the bcr3 register. for more deta ils, see the description of the bcr3 register. ? burst read figure 13.39 is the timing chart for burst-read operations. for the example shown below, we assume that two synchronous drams of 512k 16 bits 2 banks are connected and are used with a 32-bit data width and a burst length of 8. following the tr cycle, during which an actv command is output, a reada command is issued during cycle tc1. during the td1 to td8 cycles, the read data are accepted on the rising edges of the external command clock (ckio). tpc is the cycle used to wait for auto-precharging, which is triggered by the reada
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 454 of 1122 rej09b0370-0400 command, to be completed in the synchronous dram. during this cycle, no new command that accesses the same bank can be issued. in this lsi, the number of tpc cycles is determined by the setting of the tpc2 to tpc0 bits of the mcr, and no command that operates on the synchronous dram is issu ed during these cycles. figure 13.39 shows an example of the basic timing of a burst-re ad. to allow the connection of a lower-speed dram, the cycle's period can be extended by the settings of the bits in wcr2 and mcr. the number of cycles from cycle tr on which the actv command is output to cycle tc1 on which the reada command is ou tput can be specified by the rcd1 and rcd0 bits in mcr: the number of cycles is 2, 3, or 4 for the setting value of 1, 2, or 3, respectively. when two or more cycles are specified, the trw cycle, which is for the issuing of nop commands to the synchronous dram, is inserted between the tr and tc cycles. the number of cycles from cycle tc1 on which the reada command is output until cycle td1, in which the first part of the data to be read is recei ved, can be set by the bits a2w2 to a2w0 and a3w2 to a3w0 of wcr2. these independently select a number of cycles between 1 and 5 for areas 2 and 3. note that this nu mber of cycles is equal to the number of cas latency cycles of the synchronous dram.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 455 of 1122 rej09b0370-0400 tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address csn rd/ wr ras cass d31?d0 (read) dqmn bs cke td5 td6 td8 td7 tpc h/l c1 c1 c2 c3 c4 c7 c8 c5 c6 dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.39 basic timing of a burst read from synchronous dram (burst length = 8) in a cycle of access to synchronous dram, the bs signal is asserted fo r one clock cycle at the beginning of a bus cycle. data are accessed in th e following sequence: in the fill operation for a cache miss, the data between the 32-bit boundaries that include the missed data are first read; after that, the data between 32-byte boundaries that include the missed data are read in a wraparound way.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 456 of 1122 rej09b0370-0400 ? burst write figure 13.40 is the timing chart for a burst-write op eration with a burst length of 8. in this lsi, a burst write takes place when a copy-back of th e cache or a 32-byte transfer of data by the dmac takes place. in a burst-write opera tion, a writa command that include auto precharging, is issued during the tc1 cycle that follows the tr cycle in which the actv command is output. during the write cycle, the data to be written is output along with the write command. with a write command that includes an auto precharge, precharging is of the relevant bank of the synchronous dram and takes place on completion of the write command, so no new command that accesses the sa me bank can be issued until precharging has been completed. for this reason, the trwl cycles are added as a period of waiting for precharging to start after the write command has been issued. this is additional to the precharge-waiting cycle as used in read access. the trwl cycles delay the issuing of new commands to the same bank. the setting of th e trwl2 to trwl0 bits of mcr selects the number of trwl cycles. the data between 32-byte boundaries are written in a wraparound way. tr tc1 tc2 tc3 tc4 tc5 tc7 trw c1 tc6 dackn (sa: io memory) c1 c2 c3 c4 c5 c6 c7 c8 row row tc8 trw1 tpc trw1 h/l row ckio bank prechar g e-sel address csn dqmn rd/ wr ras cass d31?d0 (write) bs cke note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.40 basic timing of a burst write to synchronous dram
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 457 of 1122 rej09b0370-0400 13.3.6 burst rom interface setting bits a0bst2?a0bst0, a5bst2?a5bst0, and a6bst2?a6bst0 in bcr1 to a non- zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a burst access function. the timing for burst access to burst rom is shown in figure 13.41. two wait cycl es are set. basically, access is performed in the same way as for sram interface, but when the firs t cycle ends, only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, 16, or 32 with bits a0bst2?a0bst0, a5bst2?a5bst0, or a6bst2? a6bst0. when 16-bit rom is connected, 4, 8, or 16 can be set in the same way. when 32-bit rom is connected, 4 or 8 can be set. rdy pin sampling is always performed when one or more wait states are set. the second and subsequent access cycles also comprise two cycl es when a burst rom setting is made and the wait specification is 0. the timing in this case is shown in figure 13.42. in a burst rom interface write operatio n is performed as sram interface. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed on the data at the 32-byte bo undary. the bus is not released during this period. figure 13.43 shows the timing when a burst rom setting is made, and setup/hold is specified in wcr3.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 458 of 1122 rej09b0370-0400 t1 tb1 tb2 tb1 tb2 tb1 tb2 t2 ckio a25?a5 a4?a0 csn rd/ wr rd d31?d0 (read) bs rdy dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.41 burst rom basic access timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 459 of 1122 rej09b0370-0400 t1 twe tb2 tb1 tw tb2 tw tw tb1 tb2 tw t2 tb1 ckio a25?a5 a4?a0 csn rd/ wr rd d31?d0 (read) bs rdy dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.42 burst rom wait access timing
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 460 of 1122 rej09b0370-0400 ckio a25?a5 a4?a0 csn rd/ wr rd d31?d0 (read) bs rdy dackn (sa: io memory) ts1 tb2 th1 ts1 tb1 tb2 ts1 t1 th1 tb1 th1 ts1 tb1 t2 th1 tb2 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.43 burst rom wait access timing 13.3.7 pcmcia interface in this lsi, setting the a56pcm bit in bcr1 to 1 makes the bus interface for external memory space areas 5 and 6 an ic memory card interface or i/o card interface as stipulated in jeida specification version 4.2 (pcmcia2.1). figure 13.44 shows an example of pcmcia card connection to this lsi. to enable active insertion of the pcmcia cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connect ed between this lsi bus inte rface and the pcmcia cards. as operation in big endian mode is not explicitly stipulated in the jeida/pcmcia standard, this lsi supports only little-endian mode setting and the little-endian mode pcmcia interface. when the mmu is on, pcmcia interface can be se t in mmu page units, and there is a choice of 8-bit common memory, 16-bit common memory, 8- bit attribute memory, 16-bit attribute memory, 8-bit i/o space, 16-bit i/o space, or dynamic bus sizing. see section 3, memory management unit (mmu), for details of the setting method. when the mmu is off, the setting of bits sa2 to sa0 of ptea is always used for access.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 461 of 1122 rej09b0370-0400 sa2 sa1 sa0 description 0 0 0 reserved (setting prohibited) 1 dynamic i/o bus sizing 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory 1 16-bit common memory 1 0 8-bit attribute memory 1 16-bit attribute memory when the mmu is on, wait cycles in a bus access can be set in mmu page units. see section 3, memory management unit (mmu), for details of the setting method. when the mmu is off, access is always performed according to the setting of the tc bit in ptea. wh en tc is cleared to 0, bits a5w2?a5w0 in wait control register 2 (wcr2) and bits a5pcw1?a5pcw0, a5ted2? a5ted0, and a5teh2?a5teh0 in the pcmcia control register (pcr) are selected. when tc is set to 1, bits a6w2?a6w0 in wcr2 and bits a6pcw1?a6pcw0, a6ted2?a6ted0, and a6teh2?a6teh0 in pcr are selected. access to a pcmcia interface area by the dm ac is always performed using the dmac's chcrn.ssan, chcrn.dsan, chcrn .stc, and chcrn.dtc values. anpcw1?anpcw0 specify the number of wait states to be inse rted in a low-speed bus cycle; a value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for insertion specified by wcr2. anted2?anted0 can be set to a value from 0 to 15, enabling the address, cs , ce2a , ce2b , and reg setup times with respect to the rd and we1 signals to be secured. anteh2?anteh0 can also be set to a value from 0 to 15, enabling the address, cs , ce2a , ce2b , and reg data hold times with respect to the rd and we1 signals to be secured. wait cycles between cycles ar e set with bits a5iw2?a5iw0 and a6iw2?a6iw0 in wait control register 1 (wcr1). the inter-cycle write cycles selected depend only on the area accessed (area 5 or 6): when area 5 is accessed, bits a5iw2?a5iw0 are selected, an d when area 6 is accessed, bits a6iw2?a6iw0 are selected. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wraparound mode on the data at the 32-byte boundary. the bus is not released during this operation.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 462 of 1122 rej09b0370-0400 table 13.17 relationship between addre ss and ce when usin g pcmcia interface bus width (bits) read/ write access size (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15?d8 d7?d0 8 read 8 even don't care ? 1 0 0 invalid read data odd don't care ? 1 0 1 invalid read data 16 even don't care first 1 0 0 invalid lower read data even don't care second 1 0 1 invalid upper read data odd don't care ? ? ? ? ? ? write 8 even don't care ? 1 0 0 invalid write data odd don't care ? 1 0 1 invalid write data 16 even don't care first 1 0 0 invalid lower write data even don't care second 1 0 1 invalid upper write data odd don't care ? ? ? ? ? ? 16 read 8 even don't care ? 1 0 0 invalid read data odd don't care ? 0 1 1 read data invalid 16 even don't care ? 0 0 0 upper read data lower read data odd don't care ? ? ? ? ? ? write 8 even don't care ? 1 0 0 invalid write data odd don't care ? 0 1 1 write data invalid 16 even don't care ? 0 0 0 upper write data lower write data odd don't care ? ? ? ? ? ?
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 463 of 1122 rej09b0370-0400 bus width (bits) read/ write access size (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15?d8 d7?d0 read 8 even 0 ? 1 0 0 invalid read data odd 0 ? 0 1 1 read data invalid dynamic bus sizing * 2 16 even 0 ? 0 0 0 upper read data lower read data odd 0 ? ? ? ? ? ? write 8 even 0 ? 1 0 0 invalid write data odd 0 ? 0 1 1 write data invalid 16 even 0 ? 0 0 0 upper write data lower write data odd 0 ? ? ? ? ? ? read 8 even 1 ? 1 0 0 invalid read data odd 1 first 0 1 1 ignored invalid odd 1 second 1 0 1 invalid read data 16 even 1 first 0 0 0 invalid lower read data even 1 second 1 0 1 invalid upper read data odd 1 ? ? ? ? ? ? write 8 even 1 ? 1 0 0 invalid write data odd 1 first 0 1 1 invalid write data odd 1 second 1 0 1 invalid write data 16 even 1 first 0 0 0 upper write data lower write data even 1 second 1 0 1 invalid upper write data odd 1 ? ? ? ? ? ? notes: 1. in 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address incrementing performed automatically according to the bus width, until the transfer data size is reached. 2. pcmcia i/o card interface only
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 464 of 1122 rej09b0370-0400 g a25?a0 d15?d0 cd1, cd2 ce1 g ce2 oe we / pgm ( iord ) ( iowr ) ( iois16 ) wait a25?a0 d15?d0 cd1, cd2 ce1 ce2 oe we / pgm wait a25?a0 sh7751/ sh7751r d15?d0 rd/ wr ce2b ce2a rd we1 ce1b /( cs6 ) ce1a /( cs5 ) iciord iciowr rdy iois16 g dir d7?d0 d15 ? d8 g dir g g g dir g dir d7?d0 d15 ? d8 reg reg reg pc card (memory i/o) pc card (memory i/o) card detection circuit card detection circuit figure 13.44 example of pcmcia interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 465 of 1122 rej09b0370-0400 memory card interface basic timing: figure 13.45 shows the basic timing for the pcmcia memory card interface, and figure 13.46 shows the wait timing for the pcmcia memory card interface. ckio tpcm1 tpcm2 a25?a0 cexx rd/ wr d15?d0 (read) d15?d0 (write) rd (read) we1 (write) bs dackn (da) reg note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.45 basic timing for pcmcia memory card interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 466 of 1122 rej09b0370-0400 ckio tpcm0 a25?a0 rd/ wr cexx reg rd (read) d15?d0 (read) d15?d0 (write) we1 (write) bs rdy dackn (da) tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.46 wait timing for pcmcia me mory card interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 467 of 1122 rej09b0370-0400 common memory 1 common memory (64 mb) attribute memory (64 mb) i/o space (64 mb) attribute memory i/o space 1 i/o space 2 virtual address space card 1 on cs5 card 2 on cs6 access by cs5 wait controller virtual address space external i/o addresses io 1 io 1 different virtual pages mapped to the same physical page example of i/o spaces with different cycle times (less than 1 kb) the page size can be 1 kb, 4 kb, 64 kb, or 1 mb. example of pcmcia interface mapping io 2 io 2 1 kb page 1 kb page common memory 2 access by cs6 wait controller . . . . . . figure 13.47 pcmcia space allocation i/o card interface timing: figures 13.48 and 13.49 show the timing for the pcmcia i/o card interface. when an i/o card interface access is made to a pcmcia card, dynamic sizing of the i/o bus width is possible using the iois16 pin. when a 16-bit bus width is set, if the iois16 signal is high during a word-size i/o bus cycle, th e i/o port is recognized as being 8 bits in width. in this case, a data access for only 8 bits is performed in the i/o bus cycle being executed, followed automatically by a data access for the remaining 8 bits. dynamic bus sizing is also performed in the case of byte-size access to address 2n + 1. figure 13.50 shows the basic timing for dynamic bus sizing.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 468 of 1122 rej09b0370-0400 ckio tpci1 tpci2 a25?a0 rd/ wr cexx iciord (read) d15?d0 (read) iciowr (write) d15?d0 (write) bs dackn (da) reg note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.48 basic timing fo r pcmcia i/o card interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 469 of 1122 rej09b0370-0400 ckio a25?a0 rd/ wr cexx iciord (read) iciowr (write) dackn (da) d15?d0 (read) d15?d0 (write) bs rdy iois16 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w reg note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.49 wait timing fo r pcmcia i/o card interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 470 of 1122 rej09b0370-0400 tpci tpci0 tpci1w tpci2 tpci2w tpci0 tpci tpci2 tpci1w tpci2w ckio a25?a1 a0 rd/ wr iord ( we2 ) (read) iowr ( we3 ) (write) d15?d0 (write) d15?d0 (read) bs iois16 cexx reg rdy dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.50 dynamic bus sizing ti ming for pcmcia i/ o card interface
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 471 of 1122 rej09b0370-0400 13.3.8 mpx interface if the md6 pin is cleared to 0 in a power-on reset by means of the reset pin, the mpx interface is selected for area 0. the mpx interface is select ed for areas 1 to 6 by means of the mpx bit in bcr1 and memmode, a4mp x, and a1mpx in bcr3. the mpx interface offers a multiplexed address/data type bus protocol, and permits easy connection to an external memory controller chip that uses a single 32-bit multiplexed address/data bus. a bus cycle consists of an address phase and a data phase, with addres s information output to d25?d0 and the access size output to d31? d29 in the address phase. the bs signal is asserted for one cycl e to indicate the address phase. the csn signal is asserted at the rise of tm1 and negated after the end of the last data transfer in the data phase. therefore, a negation period doe s not occur in the case of minimum pitch access. the frame signal is asserted at the rise of tm1 and negated when the last data transfer cycle starts in the data phase. therefore, an external device for the mpx interfac e must hold the address information and access size output in the address pha se within itself, and peripheral function data input/output for the data phase. for details of access sizes and data alignment, see section 13.3.1, endian/access size and data alignment. values output to address pins a25?a0 are not guaranteed. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed on 32-byte boundary data. if the access size exceeds the set bus width in this case, burst access is perform ed with a number of data cycles following one address output. the bus is not released during this period. d31 d30 d29 access size 0 0 0 byte 1 word 1 0 longword 1 quadword 1 x x 32-byte burst legend: x: don't care
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 472 of 1122 rej09b0370-0400 ckio csn bs rd / frame rd/ wr d31?d0 rdy sh7751/sh7751r mpx device clk cs bs frame we i/o31?i/o0 rdy figure 13.51 example of 32-bit data width mpx connection the mpx interface timing is shown below. when the mpx interface is used for areas 1 to 6, a bus size of 32 bit shou ld be specified in bcr2. for wait control, waits specified by wcr2 and wait insertion by means of the rdy pin can be used. in a read, one wait cycle is automatically inserted after address output, even if wcr2 is cleared to 0.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 473 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.52 mpx interface timing 1 (singl e read cycle, anw = 0, no external wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 474 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.53 mpx interface timing 2 (single read, anw = 0, one external wait inserted)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 475 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.54 mpx interface timing 3 (singl e write cycle, anw = 0, no external wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 476 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.55 mpx interface timing 4 (single write, anw = 1, on e external wait inserted)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 477 of 1122 rej09b0370-0400 tm1 ckio rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 rdy dackn (da) d2 d3 d4 d6 d7 d8 d5 a d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.56 mpx interface timing 5 (burst read cycle, anw = 0, no external wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 478 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 rdy dackn (da) d7 d8 d2 d3 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.57 mpx interface timing 6 (burst re ad cycle, anw = 0, ex ternal wait control)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 479 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 rdy dackn (da) d1 d2 d3 d4 d5 d6 d7 d8 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.58 mpx interface timing 7 (burst write cycle, anw = 0, no external wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 480 of 1122 rej09b0370-0400 d3 d2 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 rdy dackn (da) d1 d7 d8 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.59 mpx interface timing 8 (burst write cycle, anw = 1, external wait control)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 481 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.60 mpx interface timing 9 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 482 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1w tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.61 mpx interface timing 10 (burst read cycle, anw = 0, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 483 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.62 mpx interface timing 11 (burst write cycle, anw = 0, no ex ternal wait, bus width: 32 bits, transfer data size: 64 bits)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 484 of 1122 rej09b0370-0400 tm1 ckio a rd / frame csn rd/ wr d31?d0 bs tmd1w tmd1w tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.63 mpx interface timing 12 (burst write cycle, anw = 1, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 485 of 1122 rej09b0370-0400 13.3.9 byte contro l sram interface the byte control sram interface is a memory interface that outputs a byte select strobe ( wen ) in both read and write bus cycles. it has 16 bit data pins, and can be connected to sram which has an upper byte select strobe and lower byte select strobe function such as ub and lb. areas 1 and 4 can be designated as byte contro l sram interface. however, when these areas are set to mpx mode, mpx mode has priority. the byte control sram interface write timing is the same as fo r the normal sram interface. in read operations, the wen pin timing is different. in a read access, only the we signal for the byte being read is asserted. assertion is synchronized with the fall of the ckio clock, as for the we signal, while negation is synchronized with the rise of the ckio clock, using the same timing as the rd signal. 32-byte transfer is performed co nsecutively for a total of 32 bytes according to the set bus width. the first access is performed on the data for wh ich there was an access request. the remaining accesses are performed in wrap-around fashio n on the data at th e 32-byte boundary. the bus is not released during this period. figure 13.64 shows an example of byte control sram connection to this lsi, and figures 13.65 to 13.67 show examples of byte control sram read cycles. a17?a2 csn rd rd/wr sh7751/sh7751r 64k 16-bit sram d15?d0 we1 we0 a15?a0 cs oe we i/o15?i/o0 ub lb a15?a0 cs oe we i/o15?i/o0 ub lb d31?d16 we3 we2 figure 13.64 example of 32-bit data width byte control sram
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 486 of 1122 rej09b0370-0400 t1 t2 ckio a25?a0 csn rd/ wr rd d31?d0 (read) bs dackn (sa: io memory) dackn (da) rdy wen note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.65 byte control sram basic re ad cycle (no wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 487 of 1122 rej09b0370-0400 t1 tw t2 ckio a25?a0 csn rd/ wr rd d31?d0 (read) bs dackn (sa: io memory) dackn (da) rdy wen note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.66 byte contro l sram basic read cycle (o ne internal wait cycle)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 488 of 1122 rej09b0370-0400 t1 tw twe t2 ckio a25?a0 csn rd/ wr rd d31?d0 (read) bs dackn (sa: io memory) dackn (da) rdy wen note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.67 byte contro l sram basic read cycle (one internal wait + one external wait)
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 489 of 1122 rej09b0370-0400 13.3.10 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulti ng in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write, and if there is a possibi lity of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. wait cycle inser tion consists of insertin g idle cycles between access cycles, as shown in section 13.2.5, wait control register 1 (wcr1). when this lsi performs consecutive write cycles, the data transfer direction is fixed (f rom this lsi to other memory) and there is no problem. with read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed. if there is originally space between accesses, according to the setting of bits an iw2?aniw0 (n = 0 to 6) in wcr1 , the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. when bus arbitration is performed, the bus is re leased after waits are inserted between cycles. in single address mode dma transfer, when data transfer is performed from an i/o device to memory the data on the bus is determined by the speed of the i/o device. with a low-speed i/o device, an inter-cycle idle wait e quivalent to the output buffer turn-off time must be inserted. even with high-speed memory, when dma transfer is cons idered, it may be necessary to insert an inter- cycle wait to adjust to the speed of a low-speed device, preventing the memo ry from being used at full speed. bits dmaiw2?dmaiw0 in wait control register 1 (wcr1) allow an inter-cycle wait setting to be made when transferring data from an i/o device to memory using single address mode dma transfer. from 0 to 15 waits can be inserted. the number of waits specified by dmaiw2? dmaiw0 are inserted in single ad dress dma transfers to all areas. in dual address mode dma transf er, the normal inter-cycle wait specified by aniw2?aniw0 (n = 0 to 6) is inserted.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 490 of 1122 rej09b0370-0400 t1 ckio csm csn a25?a0 bs rd/ wr rd d31?d0 t2 twait t1 t2 twait t1 t2 area m space read area m inter-access wait specification area n inter-access wait specification area n space read area n space write figure 13.68 waits between access cycles 13.3.11 bus arbitration this lsi is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. there are two bus arbitration modes: master mode, and slave mode. in master mode the bus is held on a constant basis, and is released to another device in response to a bus request. in slave mode the bus is not held on a constant basis; a bus request is issued each tim e an external bus cycle occurs, and the bus is released again at the end of the access. master mode and slave mode can be specified by the external mode pins. see appendix c, mode pin settings, for the external mode pin settings. in master mode and slave mode, the bus goes to the high-impedance state when not being held. in stead of a slave mode chip. in the following description, an external device that issues bus requests is also referred to as a slave. this lsi has three internal bus masters: the cpu, dmac, and pcic. when synchronous dram or dram is connected and refresh control is performed, refresh requests constitute a fourth bus master. in addition to these are bus requests from external devices in master mode. if requests
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 491 of 1122 rej09b0370-0400 occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the dmac, and the cpu. see section 13.3.15, notes on usage. to prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated befo re the bus is released. when mastership of the bus is received, also, bus contro l signals begin driving the bus from the negate d state. since signals are driven to the same value by the mast er and slave exchanging the bus, output buffer collisions can be avoided. bus transfer is executed between bus cycles. when the bus release request signal ( breq ) is asserted, this lsi releases the bus as soon as the currently executin g bus cycle ends, and outputs the bus use permission signal ( back ). however, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing long word access to 8-bit bus width memory) or during a 32-byte transf er such as a cache fill or write-b ack. in addition, bus release is not performed between read and write cycles duri ng execution of a tas in struction, or between read and write cycles when dmac dual address transfer is executed. when breq is negated, back is negated and use of the bus is resumed. see appendix d, pin functions, for the pin states when the bus is released. when a refresh request is generated, this lsi perf orms a refresh operation as soon as the currently executing bus cycle ends. however, refresh operations are deferred during multiple bus cycles generated because the data bus width is smal ler than the access size (for example, when performing longword access to 8-bit bus width memo ry) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. refresh operations are also deferr ed in the bus-released state. if the synchronous dram interface is set to the ras down mode the pall command is issued before a refresh cycle occurs or before the bus is released by bus arbitration. as the cpu in this lsi is connected to cache me mory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside this lsi. when writing from the cpu, an external write cycle is generated when write- through has been set for the cache in this lsi, or when an access is made to a cache-off area. there is consequently a delay until the bus is returned. when this lsi wants to take back the bus in resp onse to an internal memory refresh request, it negates back . on receiving the back negation, the device that asse rted the external bus release request negates breq to release the bus. the bus is thereb y returned to this lsi, which then carries out the necessary processing.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 492 of 1122 rej09b0370-0400 asserted for at least 2 cycles * master mode device access ckio breq back a25?a0 csn rd/ wr rd wen breq / bsack back / bsreq a25?a0 csn rd/ wr rd wen d31?d0 (read) hi-z hi-z hi-z hi-z hi-z hi-z negated within 2 cycles asserted for at least 2 cycles slave mode device access negated within 2 cycles hi-z hi-z hi-z hi-z hi-z master access master access slave access note: * for the sh7751, refer to the usage note in section 13.3.15. figure 13.69 arbitration sequence
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 493 of 1122 rej09b0370-0400 13.3.12 master mode the master mode processor holds the bus itself unless it receives a bus request. on receiving an assertion (low level) of the bus request signal ( breq ) from off-chip, the master mode processor releases the bus and asserts (d rives low) the bus use permission signal ( back ) as soon as the currently executing bu s cycle ends. if a bus release reque st due to a refresh request has not been issued, on receiving the breq negation (high level) indicating that the slave has released the bus, the processor negates (drives high) the back signal and resumes use of the bus. if a bus request is issued due to a memory refresh request in the bus-releas ed state, the processor negates the bus use permission signal ( back ), and on receiving the breq negation indicating that the slave has released the bus, resumes use of the bus. when the bus is released, all bus interface related output signals and input/ output signals go to the high-impedance state, except for the synchronous dram interface cke signal and bus arbitration back signal, and dack0 and dack1 which control dma transfers. with dram, the bus is released after prechargin g is completed. with synchronous dram, also, a precharge command is issued for the active bank and the bus is released after precharging is completed. the actual bus release sequence is as follows. first, the bus use permission signal is asserted in synchronization with the rising edge of the clock. the address bus and data bus go to the high-impedance state in synchronization after this back assertion. at the same time, the bus control signals ( bs , csn , ras1 , wen , rd , rd/ wr , ce2a , and ce2b ) go to the high-impedance state. these bus control signals are negated no later than one cycle before going to high-impedance. bus request signal sampling is performed on the rising edge of the clock. the sequence for re-acquiring the bus from the slave is as follows. as soon as breq negation is detected on the rising edge of the clock, back is negated and from next rising edge of the clock, bus control signal driving is started. driving of the address bus and data bus starts at the next rising edge of an in-phase clock. the bus control signals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. in order to reacquire the bus and start executi on of a refresh operation or bus access, the breq signal must be negated for at least two cycles.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 494 of 1122 rej09b0370-0400 if a refresh request is generated when back has been asserted and the bus has been released, the back signal is negated even while the breq signal is asserted to request the slave to relinquish the bus. when this lsi is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitra tion in the case of a slave design ed independently by the user. when connecting a slave for which the total du ration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the back signal is detected. 13.3.13 slave mode in slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence. in a reset, also, the bus-released state is established and the bus arbitration sequence is started from the reset vector fetch. to acquire the bus, the slave device asserts (drives low) the bsreq signal in synchronization with the rising edge of the clock. the bus use permission bsack signal is sampled for assertion (low level) in synchronization with the rising edge of the clock. when bsack assertion is detected, the bus control signals are driven at th e negated level after two cycles. the bus cycle is started at the next rising edge of the clock. the last signal negated at the end of the access cycle is synchronized with the rising edge of the clock. when the bus cycle ends, the bsreq signal is negated and the release of the bus is reported to the master. on the next rising edge of the clock, the control signals are set to high-impedance. in order for the slave mode processor to begin access, the bsack signal must be asserted for at least two cycles. for a slave access cycle in dram or synchronous dram, the bus is released on completion of precharging, as in the case of the master. refresh control is left to the master mode device, and any refresh control settings made in slave mode are ignored. do not use dram/synchronous dram ras down mode in slave mode. synchronous dram mode register settings should be made by the master mode device. do not use the dmac's ddt mode in slave mode.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 495 of 1122 rej09b0370-0400 13.3.14 cooperation between master and slave to enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. before dram or synchronous dram is used, initialization operations must be carried out. resp onsibility must also be assigned when a standby operation is performed to implement the power-down state. the design of this lsi provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device. if this lsi is specified as the master in a power- on reset, it will not accep t bus requests from the slave until the breq enable bit (bcr1.breqen) is set to 1. to ensure that the slave processo r does not access memory requiring initialization before use, such as dram and synchronous dram, until initialization is completed, write 1 to the breq enable bit after initialization ends. before setting self-refresh mode in standby mode, etc., write 0 to the breq enable bit to invalidate the breq signal from the slave. write 1 to the breq enable bit only after the master has performed the necessary pro cessing (refresh settings, etc.) for exiting self-refresh mode. 13.3.15 notes on usage refresh: auto refresh operations stop when a transition is made to standby mode, hardware standby mode, or deep-sleep mode. if the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode, ha rdware standby mode, or deep-sleep mode. bus arbitration: on transition to standby mode or deep-sleep mode, the processor in master mode does not release bus privileges. in systems performing bus arbitration, make the transition to standby mode or deep-sleep mode only after setting the bus privilege release enable bit (bcr1.breqen) to 0 for the processor in master mode. if the bus privilege release enable bit remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. simultaneous use of refresh and bus arbitration: with the sh7751, when performing bus arbitration using the external device and breq signal, the following two failures may occur. ? when a breq signal is input from the external de vice while using dma transfer or target transfer by the pcic, and dram/synchronous dram is set to cas-before-ras refresh and auto-refresh in master mode (md7 = 1), bus arbitration may not be performed correctly and this lsi may hang up.
13. bus state controller (bsc) rev.4.00 oct. 10, 2008 page 496 of 1122 rej09b0370-0400 ? when a breq signal is input from the external device while dram/synchronous dram is set to cas-before-ras refresh and auto-refresh in master mode (md7 = 1), assertion of the back signal (low-level) in response to the breq signal may be for on ly one cycle at ckio. both above phenomena can be avoided by not using the breq signal. if the breq signal is to be used, disable refresh operations during normal operation. if refresh operations are required, carry them out at one time with the breqen bit in bcr1 cleared to 0. synchronous dram mode register settings (sh7751 only): the following conditions must be satisfied when setting the synchronous dram mode register. ? the dmac must not be activated until synchronous dram mode register setting is completed. * 1 ? register setting for the on-chip peripheral modules * 2 must not be performed until synchronous dram mode register setting is completed. * 3 notes: 1. if a conflict occurs between synchronous dram mode register setting and memory access using the dmac, neither operation can be guaranteed. 2. this applies to the following on-chip peripheral modules: cpg, rtc, intc, tmu, sci, scif, and h-udi. 3. if synchronous dram mode register setting is performed immediately following write access to the on-chip peripheral modules * 2 , the values written to the on-chip peripheral modules cannot be guaranteed. note that following power-on, synchronous dram mode register settings should be perf ormed before accessing synchronous dram. after making mode register settings, do not change them.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 497 of 1122 rej09b0370-0400 section 14 direct memory access controller (dmac) 14.1 overview the sh7751 includes an on-chi p four-channel dir ect memory access controller (dmac). the sh7751r has an on-chip eight-channel dmac. th e dmac can be used in place of the cpu to perform high-speed data transfers among external devices equipped with dack (dma transfer end notification), external memories, memory-m apped external devices, and on-chip peripheral modules (tmu, rtc, sci, scif, cpg, and intc). using the dmac reduces the burden on the cpu and increases the operating efficiency of the chip. when using th e sh7751r, see section 14.6, configuration of the dmac (sh7751r), section 14.7, register descriptions (sh7751r), and section 14.8, operation (sh7751r). 14.1.1 features the dmac has the following features. ? four channels (sh7751), eight channels (sh7751r) ? physical address space ? choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length ? maximum of 16 m (16,777,216) transfers ? choice of single or dual address mode ? single address mode: either the transfer source or the transfer destination (external device) is accessed by a dack signal while the other is accessed by address. one data transfer is completed in one bus cycle. ? dual address mode: both the transfer source and transfer destination are accessed by address. values set in dmac internal regi sters indicate the accessed address for both the transfer source and the transf er destination. two bus cycles are required for one data transfer. ? choice of bus mode: cycle steal mode or burst mode ? two types of dmac channel priority ranking: ? fixed priority mode: channel pr iorities are permanently fixed. ? round robin mode: sets the lowe st priority for the channel th at last received an execution request. ? an interrupt request can be sent to the cpu on completion of the specified number of transfers.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 498 of 1122 rej09b0370-0400 ? the following kinds of dm ac transfer activation requests are provided ? external request (1) normal dma mode two dreq pins. low level detection or falling edge detection can be specified. external requests can only be accep ted on channel 0 and channel 1. (2) on-demand data transfer mode (ddt mode) the sh7551 performs interfacing between an external device and the dmac using the dbreq , bavl , tr , tdack , id [1:0], and d[31:0] pins. the sh7551r performs interfacing between an external device and the dmac using the dbreq , bavl , tr , tdack , id [2:0], and d[31:0] pins. external requests can be accepted on all eight channels. channel 0 does not have a request queue, but channels 1 to 3 in the sh7751 and channels 1 to 7 in the sh7751r each have four request queues. ? on-chip peripheral modules request transfer requests from the sci, scf, and tmu. these can be accepted on all channels. ? auto-request a transfer request is generated automatically within the dmac. ? channel functions: transfer modes that can be set are different for each channel. (1) normal dma mode ? channel 0: single or dual address mode. external requests are accepted. ? channel 1: single or dual address mode. external requests are accepted. ? channel 2: dual ad dress mode only ? channel 3: dual ad dress mode only ? channel 4 (sh7751r only): dual address mode only ? channel 5 (sh7751r only): dual address mode only ? channel 6 (sh7751r only): dual address mode only ? channel 7 (sh7751r only): dual address mode only (2) ddt mode ? channel 0: single or dual address mode. external requests are accepted. ? channel 1: single or dual address mode. external requests are accepted. ? channel 2: single or dual address mode. external requests are accepted. ? channel 3: single or dual address mode. external requests are accepted. ? channel 4 (sh7751r only): single or dual address mode. external requests are accepted. ? channel 5 (sh7751r only): single or dual address mode. external requests are accepted.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 499 of 1122 rej09b0370-0400 ? channel 6 (sh7751r only): single or dual address mode. external requests are accepted. ? channel 7 (sh7751r only): single or dual address mode. external requests are accepted. ? in ddt mode, data transfer is carried out by the sh7751 using the dbreq , bavl , tr , tdac k, id [1:0], and d[31:0] signals to perform handshaking between the external device and the dmac, and data transfer is carried out by the sh7751r using the dbreq , bavl , tr , tdack , id [2:0], and d[31:0] signals to perform handshaking between the external device and the dmac. ? request-queue clear for each channel (sh7751r only) request queues can be cleared on a channel-by -channel basis in either of the following two ways. ? clearing a request queue by dtr format the request queues of the relevant channe l are cleared when it receives dtr.sz = 110, dtr.id = 00, dtr.md = 11, and dtr.count [7:4]* = [1?8]. ? using software to clear the request queue the request queues of the relevant cha nnel are cleared by writing a 1 to the chcrn.qcl bit (reques t-queue clear bit) of each channel. note: * dtr.count [7:4] (dtr [23:20]): sets the port as not used. in ddt mode on the sh7751, an external device and the dmac perform handshaking using the dbreq , bavl , tr , tdack , id[1:0], and d[31:0] signals during data transfer. on th e sh7751r, the dbreq , bavl , tr , tdack , id[2:0], and d[31:0] signals are used for handshaking during data transfer between an external device and the dmac.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 500 of 1122 rej09b0370-0400 14.1.2 block diagram (sh7751) figure 14.1 shows a block diagram of the dmac. sarn darn dmatcrn chcrn dmaor tmu sci, scif dack0, dack1 drak0, drak1 le g end: dmaor: dmac operation re g ister sarn: dmac source address re g ister darn: dmac destination address re g ister dmatcrn: dmac transfer count re g ister chcrn: dmac channel control re g ister note: n = 0 to 3 on-chip peripheral module peripheral bus internal bus dmac module count control re g ister control activation control request priority control bus interface 32b data buffer bus state controller ch0 ch1 ch2 ch3 request controller dtr command buffer ddt module sar0, dar0, dmatcr0, chcr0 only external bus bavl tdack id[1:0] d[31:0] ddtmode dbreq bavl dreq0-3 4 48 bits tr dbreq tdack id[1:0] ddtd dreq0 , dreq1 external address/on-chip peripheral module address figure 14.1 block diagram of dmac
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 501 of 1122 rej09b0370-0400 14.1.3 pin configuration (sh7751) tables 14.1 and 14.2 show the dmac pins. table 14.1 dmac pins channel pin name a bbreviation i/o function 0 dma transfer request dreq0 input dma transfer request input from external device to channel 0 dreq acceptance confirmation drak0 output acceptance of request for dma transfer from channel 0 to external device notification to exte rnal device of start of execution dma transfer end notification dack0 output strobe output to external device of dma transfer request from channel 0 to external device 1 dma transfer request dreq1 input dma transfer request input from external device to channel 1 dreq acceptance confirmation drak1 output acceptance of request for dma transfer from channel 1 to external device notification to exte rnal device of start of execution dma transfer end notification dack1 output strobe output to external device of dma transfer request from channel 1 to external device
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 502 of 1122 rej09b0370-0400 table 14.2 dmac pins in ddt mode pin name abbreviation i/o function data bus request dbreq ( dreq0 ) input data bus release request from external device for dtr format input data bus available bavl (drak0) output data bus release notification data bus can be used 2 cycles after bavl is asserted transfer request signal tr ( dreq1 ) input if asserted 2 cycles after bavl assertion, dtr format is sent only tr asserted: dma request dbreq and tr asserted simultaneously: direct request to channel 2 dmac strobe tdack (dack0) output reply strobe signal for external device from dmac channel number notification id [1:0] (drak1, dack1) output notification of channel number to external device at same time as tdack output (id [1] = drak1, id [0] = dack1) 14.1.4 register configuration (sh7751) table 14.3 summarizes the dmac re gisters. the dmac has a total of 17 registers: four registers are allocated to each channel, and an additional co ntrol register is shared by all four channels.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 503 of 1122 rej09b0370-0400 table 14.3 dmac registers chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size 0 dma source address register 0 sar0 r/w undefined h'ffa00000 h'1fa00000 32 dma destination address register 0 dar0 r/w undefined h'ffa00004 h'1fa00004 32 dma transfer count register 0 dmatcr0 r/w undefined h'ffa00008 h'1fa00008 32 dma channel control register 0 chcr0 r/w * h'00000000 h'ffa0000c h'1fa0000c 32 1 dma source address register 1 sar1 r/w undefined h'ffa00010 h'1fa00010 32 dma destination address register 1 dar1 r/w undefined h'ffa00014 h'1fa00014 32 dma transfer count register 1 dmatcr1 r/w undefined h'ffa00018 h'1fa00018 32 dma channel control register 1 chcr1 r/w * h'00000000 h'ffa0001c h'1fa0001c 32 2 dma source address register 2 sar2 r/w undefined h'ffa00020 h'1fa00020 32 dma destination address register 2 dar2 r/w undefined h'ffa00024 h'1fa00024 32 dma transfer count register 2 dmatcr2 r/w undefined h'ffa00028 h'1fa00028 32 dma channel control register 2 chcr2 r/w * h'00000000 h'ffa0002c h'1fa0002c 32 3 dma source address register 3 sar3 r/w undefined h'ffa00030 h'1fa00030 32 dma destination address register 3 dar3 r/w undefined h'ffa00034 h'1fa00034 32 dma transfer count register 3 dmatcr3 r/w undefined h'ffa00038 h'1fa00038 32 dma channel control register 3 chcr3 r/w * h'00000000 h'ffa0003c h'1fa0003c 32 com- mon dma operation register dmaor r/w * h'00000000 h'ffa 00040 h'1fa00040 32 notes: longword access should be used for all cont rol registers. if a different access width is used, reads will return all 0s and writes will not be possible. * bit 1 of chcr0?chcr3 and bits 2 and 1 of dmaor can only be written with 0 after being read as 1, to clear the flags.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 504 of 1122 rej09b0370-0400 14.2 register descriptions 14.2.1 dma source address registers 0?3 (sar0?sar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 0 initial value: ? ? r/w: r/w r/w dma source address registers 0?3 (sar0?sar3) are 32-bit readable/wri table registers that specify the source address of a dma transfer. these registers have a counter feedback function, and during a dma transfer they indicate the next so urce address. in single address mode, the sar value is ignored when a device with dack has been specified as the transfer source. specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64- bit, or 32-byte data transfer, resp ectively. if a different address is specified, an address error will be detected and the dmac will halt. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode, sleep mode, and deep sleep mode.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 505 of 1122 rej09b0370-0400 14.2.2 dma destination address registers 0?3 (dar0?dar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 0 initial value: ? ? r/w: r/w r/w dma destination address registers 0?3 (dar0?dar3 ) are 32-bit readable/wr itable registers that specify the destination address of a dma transf er. these registers have a counter feedback function, and during a dma transf er they indicate the next destin ation address. in single address mode, the dar value is ignored when a device with dack has been specified as the transfer destination. specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64- bit, or 32-byte data transfer, resp ectively. if a different address is specified, an address error will be detected and the dmac will halt. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode, sleep mode, and deep sleep mode. notes: 1. when a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the setting of bit 0, bits 1?0, bits 2?0, or bits 4?0, respectively. if an address specification that ignores boundary considera tions is made, the dmac will detect an address error and halt operation on all channe ls (dmaor: address error flag ae = 1). the dmac will also detect an address error an d halt if an area 7 address is specified in an external data bus transfer, or if the address of a nonexistent on-chip peripheral module is specified. 2. external addresses are 29 bits in length. sar[31:29] and dar[31:29] are not used in dma transfer, and it is recommended that they both be set to 000.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 506 of 1122 rej09b0370-0400 14.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3) bit: 31 30 29 28 27 26 25 24 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w dma transfer count registers 0? 3 (dmatcr0?dmatcr3) are 32-bit readable/writable registers that specify the transfer count for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). specifying h'000001 gives a transfer count of 1, while h'000000 gives the maximum setting, 16,777,216 (1 6m) transfers. during dmac operation, the remaining number of transfers is shown. bits 31?24 of these registers are reserved; they ar e always read as 0, and should only be written with 0. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode, sleep mode, and deep sleep mode.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 507 of 1122 rej09b0370-0400 14.2.4 dma channel control registers 0?3 (chcr0?chcr3) bit: 31 30 29 28 27 26 25 24 ssa2 ssa1 ssa0 stc dsa2 dsa1 dsa0 dtc initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? ? ? ? ds rl am al initial value: 0 0 0 0 ? ? ? ? r/w: r r r r r/w (r/w) r/w (r/w) bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 tm ts2 ts1 ts0 ? ie te de initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r/(w) r/w notes: the te bit can only be written with 0 after being read as 1, to clear the flag. the rl, am, al, and ds bits may be absent, depending on the channel. dma channel control registers 0?3 (chcr0?chcr3 ) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. bits 31?28 and 27?24 indicate the source address and destination address, resp ectively; these settings are only valid when the transfer involves the cs5 or cs6 space and the relevant space has been specified as a pcmcia interface space. in other cases, thes e bits should be cleared to 0. for details of the pcmcia interface, see section 13 .3.7, pcmcia interface. bits 18 and 16 are not present in chcr2 and chcr3. in chcr2 and chcr3, these bits cannot be modified (for write, a write value of 0 should always be used) and are always read as 0. these registers are initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode, sleep mode, and deep sleep mode.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 508 of 1122 rej09b0370-0400 bits 31 to 29?source address space attribute specification (ssa2?ssa0): these bits specify the space attribute for pcmcia interface area access. bit 31: ssa2 bit 30: ssa1 bit 29: ssa0 description 0 0 0 reserved in pcmcia access (initial value) 1 dynamic bus sizing i/o space 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory space 1 16-bit common memory space 1 0 8-bit attribute memory space 1 16-bit attribute memory space bit 28?source address wait control select (stc): specifies cs5 or cs6 space wait control for pcmcia interface area access. this bit sel ects the wait control register in the bsc that performs area 5 and 6 wait cycle control. bit 28: stc description 0 cs5 space wait cycle sele ction (initial value) settings of bits a5w2?a5w0 in wait control register 2 (wcr2), and bits a5pcw1?a5pcw0, a5ted2?a5ted0, and a5teh2?a5teh0 in the pcmcia control register (pcr), are selected 1 cs6 space wait cycle selection settings of bits a6w2?a6w0 in wait control register 2 (wcr2), and bits a6pcw1?a6pcw0, a6ted2?a6ted0, and a6teh2?a6teh0 in the pcmcia control register (pcr), are selected note: for details, see section 13.3.7, pcmcia interface.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 509 of 1122 rej09b0370-0400 bits 27 to 25?destination address space attribute specification (dsa2?dsa0): these bits specify the space attribute for pcmcia interface area access. bit 27: dsa2 bit 26: dsa1 bit 25: dsa0 description 0 0 0 reserved in pcmcia access (initial value) 1 dynamic bus sizing i/o space 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory space 1 16-bit common memory space 1 0 8-bit attribute memory space 1 16-bit attribute memory space bit 24?destination address wait control select (dtc): specifies cs5 or cs6 space wait cycle control for pcmcia interface area access. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. bit 24: dtc description 0 cs5 space wait cycle sele ction (initial value) settings of bits a5w2?a5w0 in wait control register 2 (wcr2), and bits a5pcw1?a5pcw0, a5ted2?a5ted0, and a5teh2?a5teh0 in the pcmcia control register (pcr), are selected 1 cs6 space wait cycle selection settings of bits a6w2?a6w0 in wait control register 2 (wcr2), and bits a6pcw1?a6pcw0, a6ted2?a6ted0, and a6teh2?a6teh0 in the pcmcia control register (pcr), are selected note: for details, see section 13.3.7, pcmcia interface. bits 23 to 20?reserved: these bits are always read as 0, and should only be written with 0.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 510 of 1122 rej09b0370-0400 bit 19? dreq select (ds): specifies either low level detection or falling edge detection as the sampling method for the dreq pin used in external request mode. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr3. bit 19: ds description 0 low level detection (initial value) 1 falling edge detection notes: level detection burst mode when tm = 1 and ds = 0 edge detection burst mode when tm = 1 and ds = 1 bit 18?request check level (rl): selects whether the drak signal (that notifies an external device of the acceptance of dreq ) is an active-high or active-low output. in normal dma mode, this bit is valid only in chcr0 and chcr1. it is invalid in ddt mode. bit 18: rl description 0 drak is an active-high output (initial value) 1 drak is an active-low output bit 17?acknowledge mode (am): in dual address mode, selects whether dack is output in the data read cycle or write cycle. in single addre ss mode, dack is always output regardless of the setting of this bit. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr1?chcr3. (ddt mode: tdack) bit 17: am description 0 dack is output in read cycle (initial value) 1 dack is output in write cycle
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 511 of 1122 rej09b0370-0400 bit 16?acknowledge level (al): specifies the dack (acknowledge) signal as active-high or active-low. in normal dma mode, this bit is valid only in chcr0 and chcr1. it is invalid in ddt mode. bit 16: al description 0 active-high output (initial value) 1 active-low output bits 15 and 14?destination address mode 1 and 0 (dm1, dm0): these bits specify incrementing/decrementing of th e dma transfer destination addr ess. the specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. bit 15: dm1 bit 14: dm0 description 0 0 destination address fixed (initial value) 1 destination address incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32- byte burst transfer) 1 0 destination address decremented (?1 in 8-bit transfer, ?2 in 16- bit transfer, ?4 in 32-bit transfer, ?8 in 64-bit transfer, ?32 in 32- byte burst transfer) 1 setting prohibited bits 13 and 12?source addre ss mode 1 and 0 (sm1, sm0): these bits specify incrementing/decrementing of the dma transfer source address. the specification of these bits is ignored when data is transferre d from an external device to ex ternal memory in single address mode. bit 13: sm1 bit 12: sm0 description 0 0 source address fixed (initial value) 1 source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32- byte burst transfer) 1 0 source address decremented (?1 in 8-bit transfer, ?2 in 16-bit transfer, ?4 in 32-bit transfer, ?8 in 64-bit transfer, ?32 in 32- byte burst transfer) 1 setting prohibited
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 512 of 1122 rej09b0370-0400 bits 11 to 8?resource select 3 to 0 (rs3?rs0): these bits specify the tr ansfer request source. bit 11: rs3 bit 10: rs2 bit 9: rs1 bit 8: rs0 description 0 0 0 0 external request, dual address mode * 1 * 3 (external address space external address space) (initial value) 1 setting prohibited 1 0 external request, single address mode external address space external device * 1, * 3 1 external request, single address mode external device external address space * 1, * 3 1 0 0 auto-request (external address space external address space) * 2 1 auto-request (external address space on-chip peripheral module) * 2 1 0 auto-request (on-chip peripheral module external address space) * 2 1 setting prohibited 1 0 0 0 sci transmit-data-empty interrupt transfer request (external address space sctdr1) * 2 1 sci receive-data-full interrupt transfer request (scrdr1 external address space) * 2 1 0 scif transmit-data-empty interrupt transfer request (external address space scftdr2) * 2 1 scif receive-data-full interrupt transfer request (scfrdr2 external address space) * 2 1 0 0 tmu channel 2 (input capture interrupt, external address space external address space) * 2 1 tmu channel 2 (input capture interrupt) (external address space on-chip peripheral module) * 2 1 0 tmu channel 2 (input capture interrupt) (on-chip peripheral module external address space) * 2 1 setting prohibited notes: 1. external request specifications are valid only for channels 0 and 1. requests are not accepted for channels 2 and 3 in normal dma mode. 2. dual address mode 3. in ddt mode, an external request specificat ion is possible for channels 0, 1, 2, and 3.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 513 of 1122 rej09b0370-0400 bit 7?transmit mode (tm): specifies the bus mode for transfer. bit 7: tm description 0 cycle steal mode (initial value) 1 burst mode bits 6 to 4?transmit size 2 to 0 (ts2?ts0): these bits specify the tran sfer data size. in access to external memory, the specification is treated as an access size as described in section 13.3, operation. in access to a register, the specifi cation is treated as a register access size. bit 6: ts2 bit 5: ts1 bit 4: ts0 description 0 0 0 quadword size (64-bit) s pecification (initial value) 1 byte size (8-bit) specification 1 0 word size (16-bit) specification 1 longword size (32-bit) specification 1 0 0 32-byte block transfer specification bit 3?reserved: this bit is always read as 0, and should only be written with 0. bit 2?interrupt enable (ie): when this bit is set to 1, an interrupt request (dmte) is generated after the number of data transfer s specified in dmatcr (when te = 1). bit 2: ie description 0 interrupt request not generated afte r number of transfers specified in dmatcr (initial value) 1 interrupt request generated after number of transfers specified in dmatcr
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 514 of 1122 rej09b0370-0400 bit 1?transfer end (te): this bit is set to 1 after the number of transfers specified in dmatcr. if the ie bit is set to 1 at this tim e, an interrupt request (dmte) is generated. if data transfer ends before te is set to 1 (for ex ample, due to an nmi inte rrupt, address error, or clearing of the de bit or the dme bit in dmaor), th e te bit is not set to 1. when this bit is 1, the transfer enabled state is not entere d even if the de bit is set to 1. bit 1: te description 0 number of transfers specified in dmatcr not completed (initial value) [clearing conditions] ? when 0 is written to te after reading te = 1 ? in a power-on or manual reset, and in standby mode 1 number of transfers specified in dmatcr completed bit 0?dmac enable (de): enables operation of the corresponding channel. bit 0: de description 0 operation of corresponding channel is disabled (initial value) 1 operation of corresponding channel is enabled when auto-request is specified (with rs3?rs0), transf er is begun when this bit is set to 1. in the case of an external request or on-chip peripheral module request, transfer is begun when a transfer request is issued after this bit is set to 1. transf er can be suspended midway by clearing this bit to 0. even if the de bit has been set, transfer is no t enabled when te is 1, when dme in dmaor is 0, or when the nmif or ae bit in dmaor is 1.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 515 of 1122 rej09b0370-0400 14.2.5 dma operation register (dmaor) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ddt ? ? ? ? ? pr1 pr0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/(w) r/(w) r/w note: the ae and nmif bits can only be written with 0 after being read as 1, to clear the flags. dmaor is a 32-bit readable/writable register that specifies the dmac transfer mode. dmaor is initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode and deep sleep mode. bits 31 to 16?reserved: these bits are always read as 0, and should only be written with 0. bit 15?on-demand data transfer (ddt): specifies on-demand da ta transfer mode. bit 15: ddt description 0 normal dma mode (initial value) 1 on-demand data transfer mode note: bavl (drak0) is an active-high output in normal dma mode. when the ddt bit is set to 1, the bavl pin function is enabled and this pin becomes an active-low output.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 516 of 1122 rej09b0370-0400 bits 14 to 10?reserved: these bits are always read as 0, and should only be written with 0. bits 9 and 8?priority mode 1 and 0 (pr1, pr0): these bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. bit 9: pr1 bit 8: pr0 description 0 0 ch0 > ch1 > ch2 > ch3 (initial value) 1 ch0 > ch2 > ch3 > ch1 1 0 ch2 > ch0 > ch1 > ch3 1 round robin mode bits 7 to 3?reserved: these bits are always read as 0, and should only be written with 0. bit 2?address e rror flag (ae): indicates that an address er ror has occurred during dma transfer. if this bit is set duri ng data transfer, tran sfers on all channels are suspended, and an interrupt request (dmae) is generated. the cp u cannot write 1 to ae. this bit can only be cleared by writing 0 after reading 1. bit 2: ae description 0 no address error, dma transfer enabled (initial value) [clearing condition] when 0 is written to ae after reading ae = 1 1 address error, dma transfer disabled [setting condition] when an address error is caused by the dmac bit 1?nmi flag (nmif): indicates that nmi has been input. this bit is set regardless of whether or not the dmac is operating. if this b it is set during data tr ansfer, transfers on all channels are suspended. the cpu cannot write 1 to nmif. this bit can only be cleared by writing 0 after reading 1. bit 1: nmif description 0 no nmi input, dma transfer enabled (initial value) [clearing condition] when 0 is written to nmif after reading nmif = 1 1 nmi input, dma transfer disabled [setting condition] when an nmi interrupt is generated
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 517 of 1122 rej09b0370-0400 bit 0?dmac master enable (dme): enables activation of the entire dmac. when the dme bit and the de bit of the chcr register for the co rresponding channe l are set to 1, that channel is enabled for transfer. if this bi t is cleared during data transfer , transfers on all channels are suspended. even if the dme bit has been set, transfer is no t enabled when te is 1 or de is 0 in chcr, or when the nmi or ae bit in dmaor is 1. bit 0: dme description 0 operation disabled on all channels (initial value) 1 operation enabled on all channels 14.3 operation when a dma transfer request is issued, the dmac starts the transfer according to the predetermined channel priority order. it ends th e transfer when the tran sfer end conditions are satisfied. transfers can be requested in three mode s: auto-request, external request, and on-chip peripheral module request. there are two modes fo r dma transfer: single address mode and dual address mode. either burst mode or cycle st eal mode can be selected as the bus mode. 14.3.1 dma transfer procedure after the desired transfer conditions have been set in the dma source address register (sar), dma destination address register (dar), dm a transfer count register (dmatcr), dma channel control register (chcr), and dma operation register (dmaor), the dmac transfers data according to the following procedure: 1. the dmac checks to see if transfer is enable d (de = 1, dme = 1, te = 0, nmif = 0, ae = 0). 2. when a transfer request is issued and tran sfer has been enabled, the dmac transfers one transfer unit of data (determined by the setting of ts2?ts0). in auto-request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value is decremented by 1 for each transf er. the actual transfer flow de pends on the address mode and bus mode. 3. when the specified number of transfers have been completed (when the dmatcr value reaches 0), the tr ansfer ends normally. if the ie bit in chcr is set to 1 at this time, a dmte interrupt request is sent to the cpu. 4. if a dmac address error or nmi interrupt occurs , the transfer is suspe nded. transfer is also suspended when the de bit in chcr or the dme bit in dmaor is cleared to 0. in the event of an address error, a dmae interrupt request is forcibly sent to the cpu.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 518 of 1122 rej09b0370-0400 figure 14.2 shows a flowchart of this procedure. note: if a transfer request is issu ed while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. transfer is started when subsequently enabled (by setting de = 1, dme = 1, te = 0, nmif = 0, ae = 0).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 519 of 1122 rej09b0370-0400 start initial settin g s (sar, dar, dmatcr, chcr, dmaor) ille g al address check (reflected in ae bit) de, dme = 1? nmif, ae, te = 0? transfer request issued? * 1 transfer (1 transfer unit) dmatcr ? 1 dmatcr update sar, dar dmte interrupt request (when ie = 1) dmatcr = 0? nmif or ae = 1 or de = 0 or dme = 0? end of transfer normal end nmif or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection method transfer suspended * 4 * 2 * 3 no no yes yes yes no no no yes yes no yes notes: 1. in auto-request mode, transfer be g ins when the nmif, ae, and te bits are all 0, and the de and dme bits are set to 1. 2. dreq level detection (external request) in burst mode, or cycle steal mode 3. dreq ed g e detection (external request) in burst mode, or auto-request mode in burst mode 4. an ille g al address is detected by comparin g bits ts2?ts0 in chcrn with sarn and darn figure 14.2 dmac transfer flowchart
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 520 of 1122 rej09b0370-0400 14.3.2 dma transfer requests dma transfer requests are basically generated at e ither the data tr ansfer source or destination, but they can also be issued by external devices or on-chip peripheral modu les that are neither the source nor the destination. transfers can be requested in three modes: auto-re quest, external request, and on-chip peripheral module request. the transfer request mode is selected by means of bits rs3?rs0 in dma channel control registers 0?3 (chcr0?chcr3). auto request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bit in chcr0?chcr3 and the dme bit in the dma operation register (dmaor) are set to 1, the transfer begins (so long as the te bit in chcr0?chcr3 and the nmif and ae bits in dmaor are all 0). external request mode: in this mode a transfer is performed in response to a transfer request signal ( dreq ) from an external de vice. one of the modes shown in table 14.4 should be chosen according to the application system . if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), transfer starts when dreq is input. the ds bit in chcr0/chcr1 is used to select either falling edge detection or low level detection for the dreq signal (level detection when ds = 0, edge detection when ds = 1). the source of the transfer reques t does not have to be the data transfer source or destination. dreq is accepted after a power-on reset if te = 0, nmif = 0, and ae = 0, but transfer is not executed if dma transfer is not enabled (de = 0 or dme = 0). in this case, dma transfer is started when enabled (by setting de = 1 and dme = 1).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 521 of 1122 rej09b0370-0400 table 14.4 selecting external request mode with rs bits rs3 rs2 rs1 rs0 address mode transfer source transfer destination 0 0 0 0 dual address mode external memory, memory-mapped external device, or external device with dack external memory, memory-mapped external device, or external device with dack 1 0 single address mode external memory or memory-mapped external device external device with dack 1 single address mode external device with dack external memory or memory-mapped external device ? external request acceptance conditions 1. when at least one of dmaor.dme and chcr.de is 0, and dmaor.nmif, dmaor.ae, and chcr.te are all 0, if an external request ( dreq : edge-detected) is input it will be held inside the dmac until dm a transfer is either executed or canceled. since dma transfer is not enabled in this cas e (dme = 0 or de = 0), dma transfer is not initiated. dma transfer is started after it is enabled (dme = 1, de = 1, dmaor.nmif = 0, dmaor.ae = 0, chcr.te = 0). 2. when dma transfer is enabled (dme = 1, de = 1, dmaor.nmif = 0, dmaor.ae = 0, chcr.te = 0), if an external request ( dreq ) is input, dma tran sfer is started. 3. an external request ( dreq ) will be ignored if input when chcr.te = 1, dmaor.nmif = 1, dmaor.ae = 1, during a power-on reset or manual reset, in deep sleep mode, standby mode, or while the dmac is in the module standby state. 4. a previously input external request will be canceled by the occurrence of an nmi interrupt (dmaor.nmif = 1) or address error (dmaor.ae = 1), or by a power-on reset or manual reset. ? usage notes 1. an external request ( dreq ) is detected by a low level or falling edge. ensure that the external request ( dreq ) signal is held high when there is no dma transfer request from an external device after a powe r-on reset or manual reset. when dma transfer is restarted, check wh ether a dma transfer request is being held. 2. with dreq edge detection, an accepted external re quest can be canceled by first negating dreq , enabling a change of setting from chcr.ds = 1 to chcr.ds = 0, and then asserting dreq after setting chcr.ds to 1 again.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 522 of 1122 rej09b0370-0400 on-chip peripheral module request mode: in this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. as shown in table 14.5, there are seven transfer request signa ls: input capture interrupts from the timer unit (tmu), and receive-data-full interrupts (rxi) and transmit-data-empty interrupts (txi) from the two serial communication interfaces (sci, scif). if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), transfer starts when a transfer request signal is input. the source of the transfer reques t does not have to be the data transfer source or destination. however, when the transfer request is set to rx i (transfer request by sc i/scif receive-data-full interrupt), the transfer source must be the sci/ scif's receive data regi ster (scrdr1/scfrdr2). when the transfer request is set to txi (tra nsfer request by sci/sc if transmit-data-empty interrupt), the transfer destination must be the sci/scif's transmit data register (sctdr1/scftdr2). table 14.5 selecting on-chip peripheral module request mode with rs bits rs3 rs2 rs1 rs0 dmac transfer request source dmac transfer request signal transfer source transfer destination bus mode 1 0 0 0 sci transmitter sctdr1 (sci transmit-data- empty transfer request) external * sctdr1 cycle steal mode 1 sci receiver scrdr1 (sci receive-data-full transfer request) scrdr1 external * cycle steal mode 1 0 scif transmitter scftdr2 (scif transmit-data- empty transfer request) external * scftdr2 cycle steal mode 1 scif receiver scfrdr2 (scif receive-data-full transfer request) scfrdr2 external * cycle steal mode 1 0 0 tmu channel 2 input capture occurrence external * external * burst/cycle steal mode 1 tmu channel 2 input capture occurrence external * on-chip peripheral burst/cycle steal mode 1 0 tmu channel 2 input capture occurrence on-chip peripheral external * burst/cycle steal mode legend: tmu: timer unit sci: serial communication interface scif: serial communication interface with fifo
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 523 of 1122 rej09b0370-0400 notes: sci/scif burst transfer setting is prohibited. if input capture interrupt acceptance is set for multiple channels and de =1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. a dma transfer request by means of an input capture interrupt can be canceled by setting tcr2.icpe1 = 0 and tcr2.icpe0 = 0 in the tmu. * external memory or memory-mapped external device to output a transfer request from an on-chip peripheral module, set the dma transfer request enable bit for that module and output a transfer request signal. for details, see sections 12, timer unit (tmu), 15, serial communicati on interface (sci), and 16, serial communication in terface with fifo (scif). when a dma transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the si gnal is discontinued automatically. this occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 channel priorities if the dmac receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined prior ity system, either in a fixed mode or round robin mode. the mode is selected with priority bits pr1 and pr0 in the dma operation register (dmaor). fixed mode: in this mode, the relative channel prior ities remain fixed. the following priority orders are available in fixed mode: ? ch0 > ch1 > ch2 > ch3 ? ch0 > ch2 > ch3 > ch1 ? ch2 > ch0 > ch1 > ch3 the priority order is selected with bits pr1 and pr0 in dmaor. round robin mode: in round robin mode, each time the transfer of one transfer un it (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. this is illustrated in figure 14 .3. the order of priority in round robin mode immediately after a reset is ch0 > ch1 > ch2 > ch3. note: in round robin mode, if no transfer request is accepted for any channel during dma transfer, the priority order becomes ch0 > ch1 > ch2 > ch3.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 524 of 1122 rej09b0370-0400 ch0 > ch1 > ch2 > ch3 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 transfer on c hannel 0 priority order after transfer initial priority order channel 0 is g iven the lowest priority. transfer on c hannel 1 priority order after transfer initial priority order transfer on c hannel 2 priority order after transfer initial priority order priority after transfer due to issuance of a transfer request for channel 1 only. when channel 2 is g iven the lowest priority, the priorities of channels 0 and 1, which were hi g her than channel 2, are also shifted simultaneously. if there is a transfer request for channel 1 only immediately afterward, channel 1 is g iven the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. transfer on c hannel 3 initial priority order priority order after transfer no chan g e in priority order ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 when channel 1 is g iven the lowest priority, the priority of channel 0, which was hi g her than channel 1, is also shifted simultaneously. figure 14.3 round robin mode figure 14.4 shows the changes in priority levels when transfer requests ar e issued simultaneously for channels 0 and 3, and channel 1 receives a transf er request during a tran sfer on channel 0. the operation of the dmac in this case is as follows.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 525 of 1122 rej09b0370-0400 1. transfer requests are issued si multaneously for channels 0 and 3. 2. since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. a transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. at the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. at this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. at the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. the channel 3 transfer is started. 8. at the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. 3 1, 3 3 transfer request channel waiting dmac operation channel priority order 1. issued for channels 0 and 3 3. issued for channel 1 2. start of channel 0 transfer 0 > 1 > 2 > 3 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 4. end of channel 0 transfer 5. start of channel 1 transfer 6. end of channel 1 transfer 7. start of channel 3 transfer 8. end of channel 3 transfer chan g e of priority order chan g e of priority order chan g e of priority order none figure 14.4 example of changes in priority order in round robin mode
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 526 of 1122 rej09b0370-0400 14.3.4 types of dma transfer the dmac supports the transfers shown in table 14.6. it can operate in single address mode, in which either the transf er source or the transf er destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source an d transfer destination addresses are output. the actual tr ansfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. table 14.6 supported dma transfers transfer destination transfer source external device with dack external memory memory-mapped external device on-chip peripheral module external device with dack not available single address mode single address mode not available external memory single address mode dual address mode dual address mode dual address mode memory-mapped external device single address mode dual address mode dual address mode dual address mode on-chip peripheral module not available dual address mode dual address mode not available
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 527 of 1122 rej09b0370-0400 address modes single address mode: in single address mode, both the transfer source and the transfer destination are external; one is acce ssed by the dack signal and the other by an address. in this mode, the dmac performs a dma transfer in one bus cycle by simultaneously outputting the external device strobe si gnal (dack) to either the transfer so urce or transfer de stination external device to access it, while outputting an address to th e other side of the transfer. figure 14.5 shows an example of a transfer between external memory and an extern al device with dack in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. dmac dack dreq external memory external device with dack sh7751/sh7751r external address bus : data flow external data bus le g end: figure 14.5 data flow in single address mode two types of transfer are possible in single addr ess mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. only the external request signal ( dreq ) is used in both these cases. figure 14.6 shows the transfer timing for single address mode. the access timing depends on the type of external me mory. for details, see the descriptions of the memory interfaces in section 13 , bus state controller (bsc).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 528 of 1122 rej09b0370-0400 address output to external memory space data output from external device with dack dack si g nal to external device with dack we si g nal to external memory space address output to external memory space data output from external memory space rd si g nal to external memory space dack si g nal to external device with dack (a) from external device with dack to external memory space (b) from external memory space to external device with dack ckio a28?a0 csn d63?d0 dack we ckio a28?a0 csn d63?d0 rd dack figure 14.6 dma transfer ti ming in single address mode
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 529 of 1122 rej09b0370-0400 dual address mode: dual address mode is used to acces s both the transf er source and the transfer destination by address. the transfer source and destinatio n can be accessed by either on- chip peripheral module or external address. in dual address mode, data is read from the transf er source in the data read cycle, and written to the transfer destination in the data write cycle, so that the transfer is execut ed in two bus cycles. the transfer data is temporarily stored in th e data buffer in the bus state controller (bsc). in a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the bsc's data buffer in the read cycle, then written to the other external memory in the write cycle. figure 14.8 shows the timing for this operation. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar takin g the sar value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (bsc). 1st bus c y c le 2nd bus c y c le takin g the dar value as the address, the data stored in the bsc's data buffer is written to the transfer destination module. dmac bsc bsc dmac figure 14.7 operation in dual address mode
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 530 of 1122 rej09b0370-0400 ckio a28?a0 csn d63?d0 rd we dack transfer from external memory space to external memory space transfer source address transfer destination address data read cycle (1st cycle) data write cycle (2nd cycle) figure 14.8 example of transfer timing in dual address mode bus modes there are two bus modes, cycle steal mode and bur st mode, selected with the tm bit in chcr0? chcr3. cycle steal mode: in cycle steal mode, the dmac releases the bus to the cpu at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. when the next transfer request is issued, the dmac reacquires the bus from the cpu and carries out another transfer-unit transfer. at the end of this transfer, the bus is again given to the cpu. this is repeat ed until the transfer end condition is satisfied. cycle steal mode can be used with all categories of transfer request sour ce, transfer source, and transfer destination. figure 14.9 shows an example of dma transf er timing in cycle steal mode. the transfer conditions in this example are dual address mode and dreq level detection.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 531 of 1122 rej09b0370-0400 cpu cpu dmac dmac cpu dmac dmac cpu cpu cpu dreq bus cycle bus returned to cpu read write read write figure 14.9 example of dma transfer in cycle steal mode burst mode: in burst mode, once the dmac has acquired the bus it holds th e bus and transfers data continuously until the transfer end cond ition is satisfied. bus release by means of breq and refresh requests conform to the dmac burst mode transfer priority speci fication in bus control register 1 (bcrl.dmabst). with dreq low level detection in external request mode, however, when dreq is driven high the bus passes to anothe r bus master after the end of the dmac transfer request that has already been accepted, ev en if the transfer end condition has not been satisfied. figure 14.10 shows an example of dma transfer timing in burst mode. the transfer conditions in this example are single address mode and dreq level detection (chcrn.ds = 0, chcrn.tm = 1). cpu dmac dmac dmac dmac dmac dmac cpu cpu cpu dreq bus cycle figure 14.10 example of dm a transfer in burst mode note: burst mode can be set regardless of the transfer size. a 32-byte block transfer burst mode setting can also be made.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 532 of 1122 rej09b0370-0400 relationship between dma transfer type, request mode, and bus mode table 14.7 shows the relationship between the ty pe of dma transfer, th e request mode, and the bus mode. table 14.7 relationship between dma tr ansfer type, request mode, and bus mode address mode type of transfer request mode bus mode transfer size (bits) usable channels single external device with dack and external memory external b/c 8/16/32/64/32b 0, 1 (2, 3) * 6 external device with dack and memory-mapped external device external b/c 8/16/32/64/32b 0, 1 (2, 3) * 6 dual external memory and external memory internal * 1 , external * 7 b/c 8/16/32/64/32b 0, 1, 2, 3 * 5, * 6 external memory and memory- mapped external device internal * 1 , external * 7 b/c 8/16/32/64/32b 0, 1, 2, 3 * 5, * 6 memory-mapped external device and memory-mapped external device internal * 1 , external * 7 b/c 8/16/32/64/32b 0, 1, 2, 3 * 5, * 6 external memory and on-chip peripheral module internal * 2 b/c * 3 8/16/32/64 * 4 0, 1, 2, 3 * 5, * 6 memory-mapped external device and on-chip peripheral module internal * 2 b/c * 3 8/16/32/64 * 4 0, 1, 2, 3 * 5, * 6 legend: 32b: 32-byte burst transfer b: burst c: cycle steal external: external request internal: auto request, on-chip peripheral module request notes: 1. external request, auto-request, or on- chip peripheral module request (tmu input capture interrupt request) possible. in the case of an on-chip peripheral module request, it is not possible to specify external memo ry data transfer with the sci (scif) as the transfer request source. 2. auto-request, or on-chip peripheral module request possible. if the transfer request source is the sci (scif), either the tr ansfer source must be scrdr1 (scfrdr2) or the transfer destination mu st be sctdr1 (scftdr2). 3. when the transfer request source is the sci (scif), only cycle steal mode can be used. 4. access size permitted for the on-chip perip heral module register that is the transfer source or transfer destination.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 533 of 1122 rej09b0370-0400 5. when the transfer request is an external request, only channels 0 and 1 can be used. 6. in ddt mode, transfer requests can be accepted for all channels from external devices capable of dtr format output. 7. see tables 14.8 and 14.9 for the transfer sources and transfer destinations in dma transfer by means of an external request. (a) normal dma mode table 14.8 shows the memory interfaces that can be specified for the transf er source and transfer destination in dma transfer initiated by an extern al request supported by this lsi in normal dma mode. table 14.8 external request transfer sources and destinat ions in normal dma mode transfer direction (settable memory interface) transfer source transfer destination address mode usable dmac channels 1 synchronous dram external device with dack single 0, 1 2 external device with dack synchronous dram single 0, 1 3 sram-type, dram external device with dack single 0, 1 4 external device with dack sram-type, dram single 0, 1 5 synchronous dram sram-type, mpx, pcmcia * dual 0, 1 6 sram-type, mpx, pcmcia * synchronous dram dual 0, 1 7 sram-type, dram, pcmcia, mpx sram-type, mpx, pcmcia * dual 0, 1 8 sram-type, mpx, pcmcia * sram-type, dram, pcmcia, mpx dual 0, 1 notes: "sram-type" in the table indicates an sr am, byte control sram, or burst rom setting. memory interfaces on which transfer is possible in single address mode are sram, byte control sram, burst rom, dram, and synchronous dram. when performing dual address mode transfer, make the dack output setting for the sram, byte control sram, burst rom, pcmcia, or mpx interface. * dack output setting in dual address mode transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 534 of 1122 rej09b0370-0400 (b) ddt mode table 14.9 shows the memory interfaces that can be specified for the transf er source and transfer destination in dma transfer initiated by an extern al request supported by this lsi in ddt mode. table 14.9 external request transfer so urces and destinations in ddt mode transfer direction (settable memory interface) transfer source transfer destination address mode usable dmac channels 1 synchronous dram external device with dack single 0, 1, 2, 3 2 external device with dack sync hronous dram single 0, 1, 2, 3 3 synchronous dram sram-type, mpx, pcmcia * dual 1, 2, 3 4 sram-type, mpx, pcmcia * synchronous dram dual 1, 2, 3 5 sram-type, dram, pcmcia, mpx sram-type, mpx, pcmcia * dual 1, 2, 3 6 sram-type, mpx, pcmcia * sram-type, dram, pcmcia, mpx dual 1, 2, 3 notes: "sram-type" in the table indicates an sr am, byte control sram, or burst rom setting. the only memory interface on which single address mode transfer is possible in ddt mode is synchronous dram. when performing dual address mode transfer, make the dack output setting for the sram, byte control sram, burst rom, pcmcia, or mpx interface. * dack output setting in dual address mode transfer bus mode and channel priority order when, for example, channel 1 is tran sferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. if fixed mode has been set for the priority levels (ch0 > ch1), transfer on channel 1 is continued after transfer on channel 0 is co mpletely finished, whether cycle st eal mode or burst mode is set for channel 0. if round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. channel execution alternates in the order: channel 1 channel 0 channel 1 channel 0. an example of round robin mode operation is shown in figure 14.11.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 535 of 1122 rej09b0370-0400 since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the cpu until channel 1 transfer ends. cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu notes: priority system: round robin mode channel 0: cycle steal mode channel 1: burst mode (ed g e-sensin g ) ch0 ch1 ch0 cpu cpu dmac channel 1 burst mode dmac channel 0 and channel 1 round robin mode dmac channel 1 burst mode figure 14.11 bus handling with two dmac channels operating note: when channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the cpu during a break in requests. 14.3.5 number of bus cycle states and dreq pin sampling timing number of states in bus cycle: the number of states in the bus cycle when the dmac is the bus master is controlled by the bus state controlle r (bsc) just as it is when the cpu is the bus master. see section 13, bus state controller (bsc), for details. dreq pin sampling timing: in external request mode, the dreq pin is sampled at the rising edge of ckio clock pulses. when dreq input is detected, a dmac bus cycle is generated and dma transfer executed after four ckio cycles at the earliest. with dreq falling edge detection, as the signal passes via an asynchronous circuit the dmac recognizes dreq two cycles (ckio) later (one cycle (ckio) later in the case of low level detection). the second and subsequent dreq sampling operations are performe d one cycle after the start of the first dmac transfer bus cycle (i n the case of single address mode). drak is output for one cycle only, once each time dreq is detected, regardless of the transfer mode or dreq detection method. in the case of burst mode edge detection, dreq is sampled in the first cycle only, and so drak is output in the first cycle only .
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 536 of 1122 rej09b0370-0400 operation: figures 14.12 to 14.22 show the timing in each mode. 1. cycle steal mode in cycle steal mode, the dreq sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of dreq . for example, in figure 14.12 (cycle steal mo de, dual address mode, level detection), dmac transfer begins, at the earliest, four ckio cycles after the first sampling operatio n. the second sampling operation is performed one cycle after the start of the first dmac transfer write cycle. if dreq is not detected at this time, sampling is executed in every subsequent cycle. in figure 14.13 (cycle steal mode, dual address mode, edge detection), dmac transfer begins, at the earliest, five ckio cycles after the first sampling operation. the second sampling operation begins from the cycle in which the first dmac transfer read cycle ends. if dreq is not detected at this time, sampling is executed in every subsequent cycle. for details of the timing for various memory accesses, see section 13 , bus state controller (bsc). figure 14.18 shows the cas e of cycle steal mode, single addr ess mode, and level detection. in this case, too, transfer is started, at th e earliest, four ckio cycles after the first dreq sampling operation. the second sampling operatio n is performed one cycle after the start of the first dmac tran sfer bus cycle. figure 14.19 shows the cas e of cycle steal mode, single addr ess mode, and edge detection. in this case, transfer is star ted, at the earliest, five ckio cycles after the first dreq sampling operation. the second sampling begins one cycle after the first assertion of drak. in single address mode, the dack signal is output every dmac transfer cycle. 2. burst mode, dual address mode, level detection dreq sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. for example, in figure 14.14, dmac transfer be gins, at the earliest, four ckio cycles after the first sampling operation. the second sampling oper ation is performed one cycle after the start of the first dmac transfer write cycle. in the case of dual address mode transfer initiated by an external request, the dack signal can be output in either the read cycle or the write cycle of the dmac transfer according to the specification of the am bit in chcr. 3. burst mode, single address mode, level detection dreq sampling timing in burst mode using single address mode and level detection is shown in figure 14.20.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 537 of 1122 rej09b0370-0400 in the example shown in figure 14.20, dmac tran sfer begins, at the earliest, four ckio cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first dmac transfer bus cycle. in single address mode, the dack signal is output every dmac transfer cycle. in figure 14.22, with a 32-byte data size, 32-bit bus width, and sdram: row hit write, dmac transfer begins, at the earliest, six ckio cycles after the first sampling operation. the second sampling operation begins one cycle after dack is asserted for the first dmac transfer. 4. burst mode, dual address mode, edge detection in burst mode using dual address mode and edge detection, dreq sampling is performed in the first cycle only. for example, in the case shown in figure 14.15, dmac transfer begins, at the earliest, five ckio cycles after the first sampling operation. dm ac transfer then continues until the end of the number of data transfers set in dmatcr. dreq is not sampled during this time, and therefore drak is output in the first cycle only. in the case of dual address mode transfer initiated by an external request, the dack signal can be output in either the read cycle or the write cycle of the dmac transfer according to the specification of the am bit in chcr. 5. burst mode, single address mode, edge detection in burst mode using single address mode and edge detection, dreq sampling is performed only in the first cycle. for example, in the case shown in figure 14.21, dmac transfer begins, at the earliest, five cycles after the first sampling operation. dmac transfer then continues until the end of the number of data transfers set in dmatcr. dreq is not sampled during this time, and therefore drak is output in the first cycle only. in single address mode, the dack signal is output every dmac transfer cycle. suspension of dma transfer in case of dreq level detection with dreq level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which dma transfer is bein g executed can judge from the rising edge of ckio that drak has been asse rted, and can suspend dma transfer by negating dreq . in this case, the next drak signal is not output.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 538 of 1122 rej09b0370-0400 source address read write read 1st acceptance 2nd acceptance write bus locked source address destination address bus locked destination address cpu cpu dmac cpu dmac drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.12 dual addres s mode/cycle steal mode external bus external bus/ dreq (level detection), dack (read cycle)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 539 of 1122 rej09b0370-0400 source address read write read read 3rd acceptance 4th accep- tance 1st acceptance 2nd acceptance write bus locked source address source address destination address bus locked destination address cpu dmac cpu dmac cpu dmac drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.13 dual addres s mode/cycle steal mode external bus external bus/ dreq (edge detection), dack (read cycle)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 540 of 1122 rej09b0370-0400 source address read write read 1st acceptance 2nd acceptance write bus locked source address destination address bus locked destination address cpu dmac-2 cpu dmac-1 drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.14 dual a ddress mode/burst mode external bus external bus/ dreq (level detection), dack (read cycle)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 541 of 1122 rej09b0370-0400 source address read write read 1st acceptance write bus locked source address destination address bus locked destination address cpu dmac-2 cpu dmac-1 te bit: transfer end drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.15 dual a ddress mode/burst mode external bus external bus/ dreq (edge detection), dack (read cycle)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 542 of 1122 rej09b0370-0400 bus cycle on-chip peripheral address bus ckio source address on-chip peripheral data bus read read read d[31:0] write write write source address source address a[25:0] destination address destination address destination address cpu cpu dmac cpu dmac cpu dmac note: when bcyc : pcyc = 1 : 1 figure 14.16 dual addres s mode/cycle steal mode on-chip sci (level detection) external bus
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 543 of 1122 rej09b0370-0400 bus cycle ckio source address read read read d[31:0] write write write source address source address a[25:0] destination address destination address destination address cpu dmac cpu dmac cpu dmac t1 t2 t1 t2 t1 t2 on-chip peripheral address bus on-chip peripheral data bus note: when bcyc : pcyc = 1 : 1 figure 14.17 dual addres s mode/cycle steal mode external bus on-chip sci (level detection)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 544 of 1122 rej09b0370-0400 read read read read 1st acceptance cpu cpu cpu dmac cpu dmac dmac cpu dmac source address 2nd acceptance source address 3rd acceptance source address 4th acceptance source address drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.18 single address mode/cycle steal mode external bus external bus/ dreq (level detection)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 545 of 1122 rej09b0370-0400 source address read read read 3rd acceptance 1st acceptance 2nd acceptance source address source address cpu cpu dmac cpu dmac cpu dmac drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.19 single address mode/cycle steal mode external bus external bus/ dreq (edge detection)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 546 of 1122 rej09b0370-0400 source address read read read read 4th acceptance 3rd acceptance 1st acceptance 2nd acceptance source address source address source address cpu dmac-4 dmac-2 dmac-3 cpu dmac-1 : dreq samplin g and determination of channel priority drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[31:0] le g end: figure 14.20 single address mode/burst mode external bus external bus/ dreq (level detection)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 547 of 1122 rej09b0370-0400 source address read read te bit: transfer end read read 1st acceptance source address source address source address cpu dmac-2 dmac-4 dmac-3 cpu dmac-1 drak0 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[31:0] : dreq samplin g and determination of channel priority le g end: figure 14.21 single address mode/burst mode external bus external bus/ dreq (edge detection)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 548 of 1122 rej09b0370-0400 drak0 : dreq samplin g and determination of channel priority dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[31:0] 1st acceptance cpu cpu d1 d6 d8 asserted 2 cycles before start of bus cycle asserted 2 cycles before start of bus cycle asserted 2 cycles before start of bus cycle 2nd acceptance 3rd acceptance dmac-1 dmac-2 dmac-3 destination address destination address destination address d1 d6 d8 d1 d6 d7 d8 d7 d7 le g end: figure 14.22 single address mode/burst mode external bus external bus/ dreq (level detection)/32-byte block transfer (bus width: 32 bits, sdram: row hit write)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 549 of 1122 rej09b0370-0400 14.3.6 ending dma transfer the conditions for ending dma transfer are differ ent for ending on individual channels and for ending on all channels together. except for the case where transfer ends when the value in the dma transfer count register (dmatcr) reaches 0, the following conditions apply to ending transfer. 1. cycle steal mode (external request, on-chip peripheral module request, auto-request) when a transfer end condition is satisfied, acceptance of dmac transfer requests is suspended. the dmac completes transfer for th e transfer requests accepted up to the point at which the transfer end conditio n was satisfied, then stops. in cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. burst mode, edge detection (external request, on-chip peripheral module request, auto- request) the delay between the point at which a transfer end condition is satisfied and the point at which the dmac actually stops is the same as in cycle steal mode. in burst mode with edge detection, only the first transfer request activ ates the dmac, but the timing of stop request (de = 0 in chcr, dme = 0 in dmaor) sampli ng is the same as the transfer request sampling timing shown in 4 and 5 under operation in section 14.3.5, number of bus cycle states and dreq pin sampling timing. therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the dmac stops. 3. burst mode, level detection (external request) the delay between the point at which a transfer end condition is satisfied and the point at which the dmac actually stops is the same as in cycle steal mode. as in the case of burst mode with edge detection, the timing of stop request (de = 0 in chcr, dme = 0 in dmaor) sampling is the same as the transfer request sa mpling timing shown in 2 and 3 under operation in section 14.3.5, number of bus cycle states and dreq pin sampling timing. therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the dmac stops. 4. transfer suspension bus timing transfer suspension is executed on completion of processing for one transfer unit. in dual address mode transfer, write cycl e processing is executed even if a transfer en d condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 550 of 1122 rej09b0370-0400 conditions for ending transf er on individual channels: transfer ends on the corresponding channel when either of the following conditions is satisfied: ? the value in the dma transfer coun t register (dmatcr) reaches 0. ? the de bit in the dma channel control register (chcr) is cleared to 0. 1. end of transfer when dmatcr = 0 when the dmatcr value reaches 0, dma transf er ends on the corresponding channel and the transfer end flag (te) in chcr is set. if the interrupt enable b it (ie) is set at this time, an interrupt (dmte) request is sent to the cpu. transfer ending when dmatcr = 0 does not follow the procedures described in 1, 2, 3, and 4 in section 14.3.6. 2. end of transfer when de = 0 in chcr when the dma enable bit (de) in chcr is cleared, dma transfer is suspended on the corresponding channel. the te bit is not set in this case. transfer ending in this case follows the procedures described in 1, 2, 3, and 4 in section 14.3.6. conditions for ending transfer si multaneously on all channels: transfer ends on all channels simultaneously when either of the following conditions is satisfied: ? the address error bit (ae) or nmi flag (nmif) in the dma operation register (dmaor) is set. ? the dma master enable bit (dme ) in dmaor is cleared to 0. 1. end of transfer when ae = 1 in dmaor if the ae bit in dmaor is set to 1 due to an ad dress error, dma transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the cpu. therefore, when ae is set to 1, the values in the dma source address register (sar), dma destination address register (dar), and dma transfer count register (dmatcr) indicate the addresses for the dma transfer to be performed next and the remaining number of transfers. the te bit is not set in this case. before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the ae bit after first reading 1 from it. acceptan ce of external requests is suspended while ae is set to 1, so a dma transfer request must be reissued when resuming transfer. acceptance of internal requests is al so suspended, so when resuming transfer, the dma transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 551 of 1122 rej09b0370-0400 2. end of transfer when nmif = 1 in dmaor if the nmif bit in dmaor is set to 1 due to an nmi interrupt, dma tran sfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the cpu. therefore, wh en nmif is set to 1, the va lues in the dma source address register (sar), dma destination address register (dar), and dma transfer count register (dmatcr) indicate the addresses for the dma transfer to be performed next and the remaining number of transfers. th e te bit is not set in this case. before resuming transfer after nmi interrupt handling is completed, 0 must be written to the nmif bit after first reading 1 from it. as in the case of ae being set to 1, acceptance of external reque sts is suspended while nmif is set to 1, so a dma transfer reques t must be reissued wh en resuming transfer. acceptance of internal requests is also suspended, so when resuming transfer, the dma transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. end of transfer when dme = 0 in dmaor if the dme bit in dmaor is clear ed to 0, dma transfer is suspended on all channels in accordance with the c onditions in 1, 2, 3, and 4 in sectio n 14.3.6, and the bus is passed to the cpu. the te bit is not set in this case. when dme is cleared to 0, the values in the dma source address register (sar), dma destinati on address register (dar), and dma transfer count register (dmatcr) indicate the addresses for the dma transfer to be performed next and the remaining number of tr ansfers. when resumi ng transfer, dme must be set to 1. operation will then be resumed from the next transfer.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 552 of 1122 rej09b0370-0400 14.4 examples of use 14.4.1 examples of transfer between external memory and an external device with dack examples of transfer of data in external memory to an external device with dack using dmac channel 1 are considered here. table 14.10 shows the transfer conditions and the corresponding register settings. table 14.10 conditions for transfer between external memory and an external device with dack, and corresponding register settings transfer conditions register set value transfer source: external memory sar1 h'0c000000 transfer source: external device with dack dar1 (accessed by dack) number of transfers: 32 dmatcr1 h'00000020 transfer source address: decremented chcr1 h'000022a5 transfer destination address: (setting invalid) transfer request source: external pin ( dreq1 ) edge detection bus mode: burst transfer unit: word no interrupt request at end of transfer channel priority order: 2 > 0 > 1 > 3 dmaor h'00000201
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 553 of 1122 rej09b0370-0400 14.5 on-demand data transfer mode (ddt mode) 14.5.1 operation setting the ddt bit to 1 in dmaor causes a transi tion to on-demand data transfer mode (ddt mode). in ddt mode, it is possible to transfer to channel 0 to 3 via the data bus and ddt module, and simultaneously issue a transfer request, using the dbreq , bavl , tr , tdack , id [1:0], dtr.id, and dtr.md signals between an external device and the dmac. figure 14.23 shows a block diagram of the dmac, ddt, bsc, and an external device (with dbreq , bavl , tr , tdack , id [1:0], dtr.id, and dtr.md pins). dmac ddt memory external device (with dbreq , bavl , tr , tdack , and id [1:0]) dtr bsc sar0 dar0 dmatcr0 chcr0 dreq0?3 data buffer bavl bavl dbreq tdack id[1:0] ddtmode data buffer address bus ddtmode tdack id[1:0] data bus request controller tr fifo or memory figure 14.23 on-demand tr ansfer mode block diagram after first making the normal dma transfer settings for dmac channels 0 to 3 using the cpu, a transfer request is output from an external device using the dbreq , bavl , tr , tdack , dtr.id [1:0], and dtr.md [1:0] signals (handshake protocol using the data bus). a transfer request can also be issu ed simply by asserting tr , without using the external bus (handshake protocol without use of the data bus). for channel 2, after making the dma transfer settings in the normal way, a transfer request can be issued directly from an external device (with dbreq , bavl , tr , tdack , dtr.id [1:0], and dtr.md [1:0] pins) by asserting dbreq and tr simultaneously . in ddt mode, there is a choice of five modes for performing dma transfer.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 554 of 1122 rej09b0370-0400 1. normal data transfer mode (channel 0) bavl (the data bus available signal) is asserted in response to dbreq (the data bus request signal) from an external device. two ckio-synchronous cycles after bavl is asserted, the external data bus drives the data transfer setting command (dtr command) in synchronization with tr (the transfer request signal). the initial settings are then made in the dmac channel 0 control register, and the dma transfer is processed. 2. normal data transfer mode (except channel 1 to channel 3) in this mode, the data transfer settings are made in the dmac from the cpu, and dma transfer requests only are performed from the external device. as in 1 above, dbreq is asserted from the external devi ce and the external bus is secured, then the dtr command is driven. the transfer request channel can be specified by means of the two id bits in the dtr command. 3. handshake protocol using the data bus (valid for channel 0 only) this mode is only valid for channel 0. after the initial settings have been made in the dmac channel 0 control register, the ddt module asserts a data transfer request for the dmac by setting the dtr command id = 00, md = 00, and sz 101, 110 and driving the dtr command. 4. handshake protocol without use of the data bus the ddt module includes a function for recording the previously asserted request channel. by using this function, it is possible to assert a transfer request for the channel for which a request was asserted immediatel y before, by asserting tr only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the dmac control register (dtr command and data transfer setting by the cpu in the dmac). 5. direct data transfer mode (valid for channel 2 only) a data transfer request can be asserted for channel 2 by asserting dbreq and tr simultaneously from an external device after the initial settings have been made in the dmac channel 2 control register.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 555 of 1122 rej09b0370-0400 14.5.2 pins in ddt mode figure 14.24 shows the system configuration in ddt mode. synchronous dram dbreq / dreq0 bavl /drak0 tr / dreq1 tdack /dack0 id1, id0/drak1, dack1 ckio d31?d0 = dtr external device sh7751/sh7751r a25?a0, ras, cas, we, dqmn, cke figure 14.24 system configuratio n in on-demand data transfer mode ? dbreq : data bus release request signal for transmittin g the data transfer request format (dtr format) or a dma request from an external device to the dmac if there is a wait for release of the data bus, an external device can have the data bus released by asserting dbreq . when dbreq is accepted, the bsc asserts bavl . ? bavl : data bus d31?d0 release signal assertion of bavl means that the data bus will be released two cycles later. ? tr : transfer request signal assertion of tr has the following different meanings. ? in normal data transfer mode (channel 0, except channel 0), tr is asserted, and at the same time the dtr format is output, two cycles after bavl is asserted. ? in the case of the handshake protocol without use of the data bus, asserting tr enables a transfer request to be issued for the channel for which a transfer request was made immediately before. this function can be used only when bavl is not asserted two cycles earlier. ? in the case of direct data tran sfer mode (valid only for channe l 2), a direct transfer request can be made to channel 2 by asserting dbreq and tr simultaneously.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 556 of 1122 rej09b0370-0400 ? tdack : reply strobe signal for external device from dmac the assertion timing is the same as the dackn assertion timing for each memory interface. however, note that tdack is an active-low signal. ? id1, id0: channel number notification signals ? 00: channel 0 ? 01: channel 1 ? 10: channel 2 ? 11: channel 3 data transfer request format (dtr) sz id md (reserved) 31 28 29 27 25 23 26 24 0 (reserved) figure 14.25 data tr ansfer request format the data transfer request format (dtr format) cons ists of 32 bits. in the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, channel number and transfer request mode are specified. connection is made to d31 through d0. bits 31 to 29: transmit size (sz2?sz0) ? 000: dtr format selected ? 001: setting prohibited ? 010: setting prohibited ? 011: setting prohibited ? 100: setting prohibited ? 101: setting prohibited ? 110: request queue clear specification ? 111: transfer end specification bit 28: reserved bits 27 and 26: channel number (id1, id0) ? 00: channel 0 ? 01: channel 1 ? 10: channel 2
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 557 of 1122 rej09b0370-0400 ? 11: channel 3 bits 25 and 24: transfer request mode (md1, md0) ? 00: handshake protocol (data bus used) ? 01: setting prohibited ? 10: request queue clear specification ? 11: setting prohibited bits 23 to 0: reserved notes: 1. in channels 1 to 3, only the id field is valid. 2. in channel 0, the md field is valid. set md = 00. if 01, 10, or 11 is set, the dmac will halt with an address error. 3. in edge-sense burst mode, dma transfer is executed continuously. in level-sense burst mode and cycle steal mode, a ha ndshake protocol is used to transfer each unit of data. 4. when specifying data transfer requests using a handshake protocol for channel 0, set dtr.id = 00, dtr.md = 00, and dtr.sz 101, 110 for the dtr format. use the mov instruction to make settings in the dmac's sar0, dar0, chcr0, and dmatcr0 registers. either single address mode or dual address mode can be used as the transfer mode. select one of the following settings: chcr0.rs3?rs0 = 0000, 0010, 0011. operation is not guaranteed if the dtr format data settings are dtr.id = 00, dtr.md = 00, and dtr.sz 101, 110. usable sz, id, and md combination in ddt mode table 14.11 shows the usable combination of sz, id, and md in ddt mode of this lsi. table 14.11 usable sz, id, and md combination in ddt mode sz [2:0] id [1:0 ] md [1:0] function 000 00 00 request for transfer to channel 0 110 00 10 request queue clear 111 00 00 transfer end x 01 x request for transfer to channel 1 x 10 x request for transfer to channel 2 x 11 x request for transfer to channel 3 legend: x: don't care note: don't set values other than those shown in the above table.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 558 of 1122 rej09b0370-0400 14.5.3 transfer request a cceptance on each channel on channel 0, a dma data transfer request can be made by means of the dtr format. no further transfer requests are accepted between dtr format acceptance and the end of the data transfer. on channels 1 to 3, output a transfer request from an external device by means of the dtr format (id = 01, 10, or 11) after making dmac control register settings in the same way as in normal dma mode. each of channels 1 to 3 has a reque st queue that can accept up to four transfer requests. when a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. when chcr.te = 1 when a transfer request remains in the request queue and a transfer is completed, the request queue retains it. when another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 559 of 1122 rej09b0370-0400 tb tc td te tf th ta t g tk tj ti tm tn to tp tq ts tl tr tv tu tt tw trwd tdbqs ckio bank prechar g e-sel addr dqmn id1-id0 d31-d0 (read) csn casn ras dbreq bavl tr tdack bs rd/ wr tad tcsd tad tcsd row row row tad c1 h/l trasd tdqmd tcasd2 tcasd2 trds tbsd tbsd c1 c2 c4 c3 tdqmd trdh dmac channel tidd ttdad ttdad tidd ttrs ttrh tbavd [2ckio cycles - tdtrs] (= 18ns: 100mhz) dtr= 1ckio cycle (= 10ns: 100mhz) tdtrs tdtrh tdbqh tbavd trasd figure 14.26 single address mode/synchronous dram external device longword transfer sdram auto-precharge read bus cycle, burst (rcd = 1, cas latency = 3, tpc = 3)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 560 of 1122 rej09b0370-0400 tb tc td te tf th ta t g tk tj ti tm tn to tp tq ts tl tr tv tu tt tw ckio bank prechar g e-sel addr dqmn id1-id0 d31-d0 (read) csn casn ras dbreq bavl tr tdack bs rd/ wr tad tcsd tdqmd c1 tbsd twdd [2ckio cycles - tdtrs] (= 18ns: 100mhz) dtr= 1ckio cycle (= 10ns: 100mhz) tbsd twdd trwd tcsd row row trasd row tad h/l c1 tad trasd tcasd2 tcasd2 trwd tdqmd c4 c3 c2 tdtrs tdtrh tdbqs tdbqh tbavd tbavd ttrs ttrh ttdad dmac channel tidd tidd ttdad figure 14.27 single address mode/external device synchronous dram longword transfer sdram auto-precharge write bus cycle, burst (rcd = 1, trwl = 2, tpc = 1)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 561 of 1122 rej09b0370-0400 tb tc td te tf th ta t g tk tj ti tm tn to tp tq ts tl tr tt trwd tdbqs ckio bank prechar g e-sel addr dqmn id1-id0 d31-d0 (read) csn casn ras dbreq bavl tr tdack bs rd/ wr tad tcsd tad tcsd row row row tad c1 h/l trasd tdqmd tcasd2 tcasd2 trds tbsd tbsd c1 c2 c4 c3 tdqmd trdh dmac channel ttdad ttrs ttrh tbavd [2ckio cycles - tdtrs] (= 18ns: 100mhz) dtr= 1ckio cycle (= 10ns: 100mhz) tdtrs tdtrh tdbqh tbavd trasd ttdad dmac channel figure 14.28 dual add ress mode/synchronous dram sram longword transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 562 of 1122 rej09b0370-0400 ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq ra ca d0 d1 d2 d3 rd ba dtr 00 figure 14.29 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer ra ca wt ba d0 d1 d2 d3 d4 d5 dtr ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq figure 14.30 single address mode/burst mode/external device external bus 32-byte block transfer/channel 0 on-demand data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 563 of 1122 rej09b0370-0400 ra ca ca ca d1 d0 dtr ba rd rd rd 00 00 ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq dqmn figure 14.31 single address mode/burst mode/external bus external device 32-bit transfer/channel 0 on-demand data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 564 of 1122 rej09b0370-0400 ra ca ca d1 d0 dtr ba wt wt ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq dqmn figure 14.32 single address mode/burst mode/external device external bus 32-bit transfer/channel 0 on-demand data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 565 of 1122 rej09b0370-0400 ca ca d0 d1 dtr md = 00 d0 d1 d2 d3 wt wt dtr md = 00 start of data transfer next transfer request ckio id1, id0 tdack d31?d0 a25?a0 tr bavl dbreq cmd figure 14.33 handshake protocol using data bus (channel 0 on-demand data transfer)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 566 of 1122 rej09b0370-0400 ca ca d0 d1 d2 d3 d0 d1 d2 d3 wt wt md = 00 start of data transfer next transfer request ckio id1, id0 tdack dtr d31?d0 a25?a0 tr bavl dbreq cmd figure 14.34 handshake protocol without use of data bus (channel 0 on-demand data transfer)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 567 of 1122 rej09b0370-0400 ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we d0 ra ca d1 d2 d3 ba rd figure 14.35 read from synchronous dram precharge bank ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we ra ca d0 d1 d2 d3 pch ba rd transfer requests can be accepted figure 14.36 read from synchronous dram non-precharge bank (row miss)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 568 of 1122 rej09b0370-0400 ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we ca rd d0 d1 d2 d3 figure 14.37 read from synchronous dram (row hit) ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we ra ca ba wt d0 d1 d2 d3 figure 14.38 write to synchronous dram precharge bank
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 569 of 1122 rej09b0370-0400 ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we ra ca d0 d1 d2 d3 pch ba wt transfer requests can be accepted figure 14.39 write to synchronous dram non-precharge bank (row miss) ckio dbreq bavl tr a25?a0 d31?d0 ras, cas, we d0 ca d1 d2 d3 wt figure 14.40 write to synchronous dram (row hit)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 570 of 1122 rej09b0370-0400 00 d0 d1 d2 ra ca rd ba dtr ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq figure 14.41 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 571 of 1122 rej09b0370-0400 dma operation register (dmaor) 31 15 9 8 2 1 0 ddt pr[1:0] ae nmif dme note: ddt: 0: normal dma mode 1: on-demand data transfer mode figure 14.42 ddt mode setting dtr ca ca d0 d1 d2 d3 d0 d1 d2 d3 d1 d2 d3 wt wt ckio id1, id0 tdack cmd d31?d0 a25?a0 tr bavl dbreq start of data transfer no dma request samplin g figure 14.43 single address mo de/burst mode/edge detection/ external device external bus data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 572 of 1122 rej09b0370-0400 ca ca d0 d1 d2 d3 d0 d1 d2 d3 dtr rd rd start of data transfer wait for next dma request ckio id1, id0 tdack cmd d31?d0 a25?a0 tr bavl dbreq figure 14.44 single address mo de/burst mode/level detection/ external bus external device data transfer ca ca ca rd rd rd dtr d0 d3 d2 ckio id1, id0 tdack dqmn d31?d0 a25?a0 tr bavl dbreq cmd idle cycle idle cycle idle cycle figure 14.45 single address mode/burst mode/edge detection/by te, word, longword, quadword/external bus external device data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 573 of 1122 rej09b0370-0400 ca ca ca wt dtr d0 d3 d1 ckio id1, id0 tdack dqmn d31?d0 a25?a0 tr bavl dbreq cmd idle cycle idle cycle idle cycle wt wt figure 14.46 single address mode/burst mode/edge detection/by te, word, longword, quadword/external device external bus data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 574 of 1122 rej09b0370-0400 dtr id = 1, 2, or 3 ra ca ba rd d0 d1 d2 d3 ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq 01 or 10 or 11 figure 14.47 single address mode/burst mode/32-byte block transfer/dma transfer request to channels 1?3 using data bus
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 575 of 1122 rej09b0370-0400 ra ca ba rd 10 d0 d1 d2 d3 d4 d5 d6 d7 ckio id1, id0 tdack ras, cas, we d31?d0 a25?a0 tr bavl dbreq no dtr cycle, so requests can be made at any time figure 14.48 single address mode/b urst mode/32-byte block transfer/ external bus external device data transfer/ direct data transfer request to ch annel 2 without using data bus
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 576 of 1122 rej09b0370-0400 ckio ca ca ra ba rd rd rd rd id1, id0 tdack d31?d0 a25?a0 tr bavl dbreq ca ca d0 d1 d2 d3 ras, cas, we d0 d1 d2 d3 d0 d1 d2 3rd 4th 1st 2nd 5th four requests can be queued handshakin g is necessary to send additional requests no more requests must be i g nored (no request transmitted) figure 14.49 single address mode/burst mode/external bus external device data transfer/direct data tran sfer request to channel 2
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 577 of 1122 rej09b0370-0400 ckio ca ca ra ba wt wt wt id1, id0 tdack d31?d0 a25?a0 tr bavl dbreq ca ca d0 d1 d2 d3 ras, cas, we d0 d1 d2 d3 3rd 4th 5th handshakin g is necessary to send additional requests must be i g nored (no request transmitted) d0 d1 d2 d3 wt four requests can be queued 1st 2nd figure 14.50 single address mode/burst mode/external device external bus data transfer/direct data tran sfer request to channel 2
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 578 of 1122 rej09b0370-0400 ckio ca ca ca ca rd rd rd rd id1, id0 tdack d31?d0 a25?a0 tr bavl dbreq ras, cas, we d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 3rd 4th 5th handshakin g is necessary to send additional requests must be i g nored (no request transmitted) four requests can be queued 1st 2nd figure 14.51 single address mode/burst mode/external bus external device data transfer (active bank address)/direct data transfer request to channel 2
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 579 of 1122 rej09b0370-0400 ckio ca ca wt wt wt id1, id0 tdack d31?d0 a25?a0 tr bavl dbreq ca ca d0 d1 d2 d3 ras, cas, we d0 d1 d2 d3 3rd 4th 5th handshakin g is necessary to send additional requests must be i g nored (no request transmitted) d0 d1 d2 d3 wt four requests can be queued 1st 2nd figure 14.52 single address mode/burst mode/external device external bus data transfer (active bank address)/direct data transfer request to channel 2
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 580 of 1122 rej09b0370-0400 14.5.4 notes on use of ddt module 1. normal data transfer mode (channel 0) set dtr.id = 00 and dtr.md = 00. if a setti ng of md = 01, 10, or 11 is made, the dmac will halt with an address error. in this case, the error can be cleared by reading dmaor.ae = 1, then writing ae = 0. 2. normal data transfer mode (channel 1 to channel 3) if a setting of dtr.id = 01, 10, or 11 is made, dtr.md will be ignored. 3. handshake protocol using the data bus (valid on channel 0 only) a. the handshake protocol using the data bus can be executed only on channel 0. (the dtr format must be set to dtr.id = 00, dtr.md = 00, and dtr.sz 101, 110. operation is not guaranteed if the dtr format data se ttings are dtr.id = 00, dtr. md = 00, and dtr.sz 101, 110.) b. if, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that dma transfer is executed settings of dtr.id = 00, dtr.md = 00, and dtr.sz 101, 110 are input in the handshake protocol using the data bus, a transfer requ est will be asserted for channel 0. c. if tr only is asserted by means of the handshake protocol without use of the data bus and a dma transfer request is input when channel 0 dma transfer has ended and chcr0.te = 1, the dmac will freeze. before issuing a dm a transfer request, the te flag must be cleared by writing chcr0.te = 0 after reading chcr0.te = 1. 4. handshake protocol without use of the data bus a. with the handshake protocol without use of the data bus, a dma transfer request can be input to the dmac again for the channel fo r which transfer was requested immediately before by asserting tr only. b. when using the handshake protocol without use of the data bus, first make the necessary settings in the dmac control registers. c. when not using the handshake protocol without use of the data bus, if tr only is asserted without outputting dtr, a request will be issu ed for the channel for which dma transfer was requested immediately before. also, if th e first dma transfer request after a power-on reset is input by asserting tr only, it will be ignored and the dmac will not operate. 5. direct data transfer mode (valid on channel 2 only) a. if a dma transfer request for channel 2 is input by simultaneous assertion of dbreq and tr during dma transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is sp ace in the ddt channel 2 request queue. b. in direct data transfer mode (with dbreq and tr asserted simultaneously), dbreq is not interpreted as a bus arbitra tion signal, and therefore the bavl signal is never asserted.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 581 of 1122 rej09b0370-0400 6. request queue tran sfer request acceptance a. the ddt has four request queues for each of channels 1 to 3. when these request queues are full, a dma transfer request from an external device will be ignored. b. if a dma transfer request for channel 0 is input during execution of a channel 0 dma bus cycle, the ddt will ignore that request. conf irm that channel 0 dma transfer has finished (burst mode) or that a dma bus cycle is not in progress (cycle steal mode). 7. dtr format a. the ddt module processes dtr.id , dtr.md, and dtr.sz as follows. when dtr.id= 00 ? md = 00, sz 101, 110: handshake protocol using the data bus ? md 00, sz = 111: chcr0.de = 0 setting (dma transfer end request) ? md = 10, sz = 110: ddt request queue clear when dtr.id 00 ? transfer request to channels 1?3 (items other than id ignored) note: do not use setting values other than the above. 8. data transfer end request a. a data transfer end request (dtr.id = 00, md 00, sz = 111) cannot be accepted during channel 0 dma transfer. therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. when a transfer end request (dtr.id = 00, md 00, sz = 111) is accepted, the values set in chcr0, sar0, dar0, and dmatcr0 are reta ined. in this case, execution cannot be restarted from an external device. to re start execution, set chcr0 .de = 1 with an mov instruction. 9. request queue clearance a. when settings of dtr.id = 00, dtr.md = 10, and sz = 110 are accepted by the ddt in normal data transfer mode, ddt channel 0 requests and channel 1 to 3 request queues are all cleared. all external requests held on the dmac side are also cleared. b. in case 3-c, the dmac freeze state can be cleared. c. when settings of dmaor.ddt = 1, dtr.id = 00, dtr.md = 10, and sz = 110 are accepted by the ddt in case 11, the dmac freeze state can be cleared. 10. dbreq assertion a. after dbreq is asserted, do not assert dbreq again until bavl is asserted, as this will result in a discrepancy between the number of dbreq and bavl assertions. b. the bavl assertion period due to dbreq assertion is one cycle. if a row address miss occurs in a read or write in the non-precharged bank during synchronous dram access, bavl is asserted for a number of cycles in accordance with the ras precharge interval set in bsc.mcr.tcp.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 582 of 1122 rej09b0370-0400 c. it takes one cycle for dbreq to be accepted by the dmac after being asserted by an external device. if a row address miss occurs at this time in a read or write in the non- precharged bank during sy nchronous dram access, and bavl is asserted, the dbreq signal asserted by the external device is ignored. therefore, bavl is not asserted again due to this signal. 11. clearing ddt mode check that dma transfer is not in progress on any channel before setting the dmaor.ddt bit. if the dmaor.ddt setting is changed from 1 to 0 during dma transfer in ddt mode, the dmac will freeze. this also applies when switching from normal dma mode (dmaor.ddt = 0) to ddt mode. 12. confirming dma transfer requests and number of transfers executed the channel associated with a dma bus cycle being executed in response to a dma transfer request can be confirmed by determining the level of external pins id1 and id0 at the rising edge of the ckio clock while tdack is asserted. (id = 00: channel 0; id = 01: channel 1; id = 10: channel 2; id = 11: channel 3)
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 583 of 1122 rej09b0370-0400 14.6 configuration of the dmac (sh7751r) 14.6.1 block diagram of the dmac figure 14.53 is a block diagram of the dmac in the sh7751r. dreq0?7 request 8 dmaqueclr0-7 queclr0?7 sar0, dar0, dmatcr0, chcr0 only ddtmode bavl 48 bits ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 request controller dtr command buffer ddt module ddtd external bus tr dbreq tdack id[2:0] tdack id[1:0] d[31:0] dbreq bavl / id2 sar0?7 dar0?7 dmatcr0?7 chcr0?7 dmaor bus interface peripheral bus internal bus dmac module count control re g istr control activation control request priority control 32b data buffer bus state controller on-chip peripheral module external address/on-chip peripheral module address tmu sci, scif dack0, dack1 drak0, drak1 dreq0 , dreq1 le g end: dmaor: sar: dar: dmatcr: chcr: dmac operation re g ister dmac source address re g ister dmac destination address re g ister dmac transfer count re g ister dmac channel control re g ister figure 14.53 block diagram of the dmac
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 584 of 1122 rej09b0370-0400 14.6.2 pin configuration (sh7751r) tables 14.12 and 14.13 show the pin configuration of the dmac. table 14.12 dmac pins channel pin name a bbreviation i/o function 0 dma transfer request dreq0 input dma transfer request input from external device to channel 0 dreq acceptance confirmation drak0 output acceptance of request for dma transfer from channel 0 to external device notification to exte rnal device of start of execution dma transfer end notification dack0 output strobe output to external device of dma transfer request from channel 0 to external device 1 dma transfer request dreq1 input dma transfer request input from external device to channel 1 dreq acceptance confirmation drak1 output acceptance of request for dma transfer from channel 1 to external device notification to exte rnal device of start of execution dma transfer end notification dack1 output strobe output to external device of dma transfer request from channel 1 to external device
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 585 of 1122 rej09b0370-0400 table 14.13 dmac pins in ddt mode pin name abbreviation i/o function data bus request dbreq ( dreq0 ) input data bus release request from external device for dtr format input data bus available bavl / id2 (drak0) output data bus release notification data bus can be used 2 cycles after bavl is asserted notification of channel number to external device at same time as tdack output transfer request signal tr ( dreq1 ) input if asserted 2 cycles after bavl assertion, dtr format is sent only tr asserted: dma request dbreq and tr asserted simultaneously: direct request to channel 2 dmac strobe tdack (dack0) output reply strobe signal for external device from dmac channel number notification id[1:0] (drak1, dack1) output notification of channel number to external device at same time as tdack output (id [1] = drak1, id [0] = dack1) requests for dma transfer from external de vices are normally accepte d only on channel 0 ( dreq0 ) and channel 1 ( dreq1 ). in ddt mode, the bavl pin functions as both the data-bus- available pin and channel-number-notification ( id2 ) pin. 14.6.3 register configuration (sh7751r) table 14.14 shows the configuration of the dmac's registers. the dmac of the sh7751r has a total of 33 registers: four regist ers are assigned to each channel, an d there is a control register for the overall control of the dmac.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 586 of 1122 rej09b0370-0400 table 14.14 register configuration chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size dma source address register 0 sar0 r/w undefined h'ffa00000 h'1fa00000 32 dma destination address register 0 dar0 r/w undefined h'ffa00004 h'1fa00004 32 dma transfer count register 0 dmatcr0 r/w undefined h'ffa00008 h'1fa00008 32 0 dma channel control register 0 chcr0 r/w * h'00000000 h'ffa0000c h'1fa0000c 32 dma source address register 1 sar1 r/w undefined h'ffa00010 h'1fa00010 32 dma destination address register 1 dar1 r/w undefined h'ffa00014 h'1fa00014 32 dma transfer count register 1 dmatcr1 r/w undefined h'ffa00018 h'1fa00018 32 1 dma channel control register 1 chcr1 r/w * h'00000000 h'ffa0001c h'1fa0001c 32 dma source address register 2 sar2 r/w undefined h'ffa00020 h'1fa00020 32 dma destination address register 2 dar2 r/w undefined h'ffa00024 h'1fa00024 32 dma transfer count register 2 dmatcr2 r/w undefined h'ffa00028 h'1fa00028 32 2 dma channel control register 2 chcr2 r/w * h'00000000 h'ffa0002c h'1fa0002c 32 dma source address register 3 sar3 r/w undefined h'ffa00030 h'1fa00030 32 dma destination address register 3 dar3 r/w undefined h'ffa00034 h'1fa00034 32 dma transfer count register 3 dmatcr3 r/w undefined h'ffa00038 h'1fa00038 32 3 dma channel control register 3 chcr3 r/w * h'00000000 h'ffa0003c h'1fa0003c 32 com- mon dma operation register dmaor r/w * h'00000000 h'ffa 00040 h'1fa00040 32
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 587 of 1122 rej09b0370-0400 chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size dma source address register 4 sar4 r/w undefined h'ffa00050 h'1fa00050 32 dma destination address register 4 dar4 r/w undefined h'ffa00054 h'1fa00054 32 dma transfer count register 4 dmatcr4 r/w undefined h'ffa00058 h'1fa00058 32 4 dma channel control register 4 chcr4 r/w * h'00000000 h'ffa0005c h'1fa0005c 32 dma source address register 5 sar5 r/w undefined h'ffa00060 h'1fa00060 32 dma destination address register 5 dar5 r/w undefined h'ffa00064 h'1fa00064 32 dma transfer count register 5 dmatcr5 r/w undefined h'ffa00068 h'1fa00068 32 5 dma channel control register 5 chcr5 r/w * h'00000000 h'ffa0006c h'1fa0006c 32 dma source address register 6 sar6 r/w undefined h'ffa00070 h'1fa00070 32 dma destination address register 6 dar6 r/w undefined h'ffa00074 h'1fa00074 32 dma transfer count register 6 dmatcr6 r/w undefined h'ffa00078 h'1fa00078 32 6 dma channel control register 6 chcr6 r/w * h'00000000 h'ffa0007c h'1fa0007c 32 dma source address register 7 sar7 r/w undefined h'ffa00080 h'1fa00080 32 dma destination address register 7 dar7 r/w undefined h'ffa00084 h'1fa00084 32 7 dma transfer count register 7 dmatcr7 r/w undefined h'ffa00088 h'1fa00088 32 dma channel control register 7 chcr7 r/w * h'00000000 h'ffa0008c h'1fa0008c 32 notes: longword access should be used for all cont rol registers. if a different access width is used, reads will return all 0s and writes will not be possible. * bit 1 of chcr0?chcr7 and bits 2 and 1 of dmaor can only be written with 0 after being read as 1, to clear the flags.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 588 of 1122 rej09b0370-0400 14.7 register descriptions (sh7751r) 14.7.1 dma source address registers 0 ? 7 (sar0 ? sar7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma source address registers 0 ? 7 (sar0 ? sar7) are 32-bit readable/w ritable registers that specify the source address for a dm a transfer. the functions of thes e registers are the same as on the sh7751. for more informat ion, see section 14.2.1, dma source address registers 0 ? 3 (sar0 ? sar3). 14.7.2 dma destination address registers 0 ? 7 (dar0 ? dar7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma destination address registers 0 ? 7 (dar0 ? dar7) are 32-bit readable/writable registers that specify the destination address fo r a dma transfer. the functions of these registers are the same as on the sh7751. for more information, see s ection 14.2.2, dma destin ation address registers 0 ? 3 (dar0 ? dar3).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 589 of 1122 rej09b0370-0400 14.7.3 dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) are 32-bit read able/writable registers that specify the number of transfers in tran sfer operations for the corresponding channel (bytecount, word count, longword count, quadword count, or 32-byte count). functions of these registers are the same as the tr ansfer-count registers of the sh7751. for more information, see section 14.2.3, dma transfer count registers 0 ? 3 (dmatcr0 ? dmatcr3). 14.7.4 dma channel control registers 0 ? 7 (chcr0 ? chcr7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ssa2 ssa1 ssa0 stc dsa2 dsa1 dsa0 dtc ? ? ? ? ds rl am al initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r r r r r/w (r/w) r/w (r/w) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 tm ts2 ts1 ts0 qcl ie te de initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w (r/w) r/w (r/w) r/w dma channel control registers 0 ? 7 (chcr0 ? chcr7) are 32-bit readable/w ritable registers that specify the operating mode, transfer me thod, etc., for each channel. bits 31 ? 28 and 27 ? 24 correspond to the so urce address and destination address, respectively; these settings are only valid when the transfer involves the cs5 or cs6 space and the relevant space has been specified as a pcmcia-interface space. in other cas es, these bits should be cleared to 0. for more information about the pcmcia interface, see s ection 13.3.7, pc mcia interface.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 590 of 1122 rej09b0370-0400 no function is assigned to bits 18 and 16 of the chcr2?chcr7 registers. writing to these bits of the chcr2?chcr7 registers is invalid. if, however, a value is written to these bits, it should always be 0. these bits are always read as 0. these registers are initialized to h'00000000 by a power-on or manual reset. their values are retained in standby, sleep, and deep-sleep modes. bits 31 to 29?source address space attribute specification (ssa2?ssa0): these bits specify the space attribute for pcmc ia access. these bits are only valid in the case of page mapping to pcmcia connected to areas 5 and 6. for details of the settings, see the description of the ssa2 ? ssa0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 28?source address wait control select (stc): specifies cs5 or cs6 space wait control for pcmcia access. this bit selects the wait contro l register in the bsc that performs area 5 and 6 wait cycle control. for details of the settings, see the description of the stc bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 27 to 25?destination address space attribute specification (dsa2?dsa0): these bits specify the space attribute for pcmcia access. th ese bits are only valid in the case of page mapping to pcmcia connected to areas 5 and 6. fo r details of the settings, see the description of the dsa2 ? dsa0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 24?destination address wait control select (dtc): specifies cs5 or cs6 space wait cycle control for pcmcia access. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. for details of the settings, see the description of the dtc bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 23 to 20?reserved: these bits are always read as 0, and should only be written with 0. bit 19? dreq select (ds): specifies either low level detection or falling edge detection as the sampling method for the dreq pin used in external request mode. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr7. for details of the settings, see the description of the ds bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 18?request check level (rl): selects whether the drak signal (that notifies an external device of the acceptance of dreq ) is an active-high or active-low output. this bit is valid only in chcr0 and chcr1 in normal mode, and is invalid in ddt mode. for details of the settings, see the description of the rl bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 591 of 1122 rej09b0370-0400 bit 17?acknowledge mode (am): in dual address mode, selects whether dack is output in the data read cycle or write cycle. in single addre ss mode, dack is always output regardless of the setting of this bit. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr7. (ddt mode: tdack ) for details of the settings, see the description of the am bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 16?acknowledge level (al): specifies the dack (acknowledge) signal as active-high or active-low. this bit is valid only in chcr0 and chcr1 in normal mode, and is invalid in ddt mode. for details of the settings, see the description of the al bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 15 and 14?destination address mode 1 and 0 (dm1, dm0): these bits specify incrementing/decrementing of th e dma transfer destination addr ess. the specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. for details of the settings, see the description of the dm1 and dm0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 13 and 12?source addre ss mode 1 and 0 (sm1, sm0): these bits specify incrementing/decrementing of the dma transfer source address. the specification of these bits is ignored when data is transferre d from an external device to ex ternal memory in single address mode. for details of the settings, see the description of the sm1 and sm0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 11 to 8?resource select 3 to 0 (rs3?rs0): these bits specify the tr ansfer request source. for details of the settings, see the description of the rs3 ? rs0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 7?transmit mode (tm): specifies the bus mode for transfer. for details of the settings, see the description of the tm bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 6 to 4?transmit size 2 to 0 (ts2?ts0): these bits specify the tr ansfer data size. for details of the settings, see the description of the ts2 ? ts0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 592 of 1122 rej09b0370-0400 bit 3 ? request queue clear (qcl): writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. this bit is only functional when dmaor.ddt = 1 and dmaor.dbl = 1. chcr bit 3 qcl description 0 this bit is always read as 0. (initial value) writing a 0 to this bit is invalid. 1 when dmaor.dbl = 1, writing a 1 to th is bit clears the request queues on the ddt side and any external requests stor ed in the dmac. the written value is not retained. bit 2?interrupt enable (ie): when this bit is set to 1, an interrupt request (dmte) is generated after the number of data tran sfers specified in dmatcr (when te = 1). for details of the settings, see the description of the ie bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 1?transfer end (te): this bit is set to 1 after the number of transfers specified in dmatcr. if the ie bit is set to 1 at this ti me, an interrupt request (dmte) is generated. if data transfer ends before te is set to 1 (for ex ample, due to an nmi inte rrupt, address error, or clearing of the de bit or the dme bit in dmaor), th e te bit is not set to 1. when this bit is 1, the transfer enabled state is not ente red even if the de bit is set to 1. for details of the settings, see the description of the te bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 0?dmac enable (de): enables operation of the corresponding channel. for details of the settings, see the description of the de bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 593 of 1122 rej09b0370-0400 14.7.5 dma operation register (dmaor) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddt dbl ? ? ? ? pr1 pr0 ? ? ? ? ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r r/w r/w r r r r r r/(w) r/(w) r/w dmaor is a 32-bit readable/writable register that specifies the dmac transfer mode. dmaor is initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode and deep sleep mode. bits 31 to 16?reserved: these bits are always read as 0, and should only be written with 0. bit 15?on-demand data transfer (ddt): specifies on-demand data tr ansfer mode. for details of the settings, see the description of the ddt bit in section 14.2.5, dma operation register (dmaor). bit 14 ? number of ddt-mode channels (dbl): selects the number of channels that are able to accept external requests in ddt mode. bit 14: dbl description 0 four ddt-mode channels (initial value) 1 eight ddt-mode channels note: when dmaor.dbl = 0, channels 4 to 7 do not accept external requests. when dmaor.dbl = 1, one channel can be selected from among channels 0 ? 7 by the combination of dtr.sz and dtr.id in the dtr fo rmat (see figure 14.54) . table 14.15 shows the channel selection by dtr format in the ddt mode.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 594 of 1122 rej09b0370-0400 table 14.15 channel selection by dtr format (dmaor.dbl = 1) dtr.id[1:0] dtr.sz[2:0] 101 dtr.sz[2:0] = 101 00 ch0 ch4 01 ch1 ch5 10 ch2 ch6 11 ch3 ch7 sz id md count * reserved (reserved) 31 29 28 27 26 25 24 23 16 0 note: * these bits are valid when request queue clear is specified (with no transfer count function). figure 14.54 dtr format (tra nsfer request format) (sh7751r) bits 13 to 10?reserved: these bits are always read as 0, and should only be written with 0. bits 9 and 8?priority mode 1 and 0 (pr1, pr0): these bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. dmaor bit 9 dmaor bit 8 pr1 pr0 description 0 0 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 (initial value) 0 1 ch0 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 > ch1 1 0 ch2 > ch0 > ch1 > ch3 > ch4 > ch5 > ch6 > ch7 1 1 round robin mode bits 7 to 3?reserved: these bits are always read as 0, and should only be written with 0. bit 2?address e rror flag (ae): indicates that an address er ror has occurred during dma transfer. if this bit is set duri ng data transfer, tran sfers on all channels are suspended, and an interrupt request (dmae) is generated. the cpu cannot write 1 to ae. this bit can only be cleared by writing 0 after reading 1. for details of the settings, see the description of the ae bit in section 14.2.5, dma opera tion register (dmaor).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 595 of 1122 rej09b0370-0400 bit 1?nmi flag (nmif): indicates that nmi has been input. this bit is set regardless of whether or not the dmac is operating. if this b it is set during data tr ansfer, transfers on all channels are suspended. the cpu cannot write 1 to nmif. this bit can only be cleared by writing 0 after reading 1. for details of the settings, see th e description of the nmif bit in section 14.2.5, dma operation register (dmaor). bit 0?dmac master enable (dme): enables activation of the entire dmac. when the dme bit and the de bit of the chcr register for the co rresponding channe l are set to 1, that channel is enabled for transfer. if this bi t is cleared during data transfer , transfers on all channels are suspended. even if the dme bit has been set, transfer is no t enabled when te is 1 or de is 0 in chcr, or when the nmi or ae bit in dmaor is 1. for details of the settings, see the description of the dme bit in section 14.2.5, dma operation register (dmaor). 14.8 operation (sh7751r) operation specific to the sh7751r is described here. for details of operation, see section 14.3, operation. 14.8.1 channel specification for a normal dma transfer in normal dma transfer mode, the dmac always operates with eight channels, and external requests are only accepted on channel 0 ( dreq0 ) and channel 1 ( dreq1 ). after setting the registers of the channels in use, including chcr, sar, dar, and dmatcr, dma transfer is started on receiving a dma transfer request in the transfer-enabled state (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), in the order of predetermined priority. the transfer ends when the transfer-end condition is satisfied. ther e are three modes for transfer requests: auto- request, external request, and on-chip peripheral module request. the addressing modes for dma transfer are the single-address mode and the dual- address mode. bus mode is selectable between burst mode and cycle steal mode. 14.8.2 channel specification for ddt-mode dma transfer for dma transfer in ddt mode, the dmaor.dbl setting selects either four or eight channels. external requests are accepted on channels 0 ? 3 when dmaor.dbl = 0, and on channels 0 ? 7 when dmaor.dbl = 1. for further information on these settings, see the entry on the dbl bit in section 14.7.5, dma operat ion register (dmaor).
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 596 of 1122 rej09b0370-0400 14.8.3 transfer channel notification in ddt mode when the dmac is set up for four-channel external request acceptance in ddt mode (dmaor.dbl = 0), the id [1:0] bits are used to notify the external device of the dmac channel that is to be used. for more details, see section 14.5, on-demand data transfer mode (ddt mode). when the dmac is set up for eight-channe l external request acceptance in ddt mode (dmaor.dbl = 1), the id [1:0] bits and the simultaneous (on the timing of tdack assertion) assertion of id2 from the bavl (data bus available) pin are used to notify the external device of the dmac channel that is to be used (see table 14.16, notification of transfer channel in eight- channel ddt mode). when the dmac is set up for eight-channe l external request acceptance in ddt mode (dmaor.dbl = 1), it is important to note that the bavl pin has the two functions as shown in table 14.17. table 14.16 notification of transf er channel in eight-channel ddt mode bavl / id2 id[1:0] transfer channel 00 ch0 01 ch1 10 ch2 1 11 ch3 00 ch4 01 ch5 0 10 ch6 11 ch7 table 14.17 function of bavl function of bavl tdack = high bus available tdack = low notification of channel number ( id2 )
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 597 of 1122 rej09b0370-0400 14.8.4 clearing request queues by dtr format in ddt mode, the request queues of any channel can be cleared by using dtr.id, dtr.md, dtr.sz, and dtr.count [7:4] in a dtr format. this function is only available when dmaor.dbl = 1. table 14.18 shows the dtr fo rmat settings for clearing request queues. table 14.18 dtr format for clearing request queues dmaor.dbl dtr.id dtr.md dtr.sz dtr.count[7:4] description 10 clear the request queues of all channels (1 ? 7). clear the ch0 request-accepted flag 0 00 11 110 * setting prohibited 10 * clear the request queues of all channels (1 ? 7). clear the ch0 request-accepted flag. 0001 clear the ch0 request-accepted flag 0010 clear the ch1 request queues. 0011 clear the ch2 request queues. 0100 clear the ch3 request queues. 0101 clear the ch4 request queues. 0110 clear the ch5 request queues. 0111 clear the ch6 request queues. 1 00 11 110 1000 clear the ch7 request queues. note: (sh7751r) dtr.sz = dtr[31:29], dt r.id = dtr[27:26], dtr.md = dtr[25:24], dtr.count[7:4] = dtr[23:20] 14.8.5 interrupt-request codes when the number of transfers sp ecified in dmatcr has been finished and the interrupt request is enabled (chcr.ie = 1), a transfer-end interrup t request can be sent to the cpu from each channel. table 14.19 lists the interrupt-request c odes that are associated with these transfer-end interrupts.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 598 of 1122 rej09b0370-0400 table 14.19 dmac interrupt-request codes source of the interrupt descri ption intevt code priority dmte0 ch0 transfer-end interrupt h'640 high dmte1 ch1 transfer-end interrupt h'660 dmte2 ch2 transfer-end interrupt h'680 dmte3 ch3 transfer-end interrupt h'6a0 dmte4 ch4 transfer-end interrupt h'780 dmte5 ch5 transfer-end interrupt h'7a0 dmte6 ch6 transfer-end interrupt h'7c0 dmte7 ch7 transfer-end interrupt h'7e0 dmae address error interrupt h'6c0 low dmte4?dmte7: these codes ar e not used in the sh7751. ckio ra dtr ca d1 d2 rd ba 00 id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl / id2 dbreq d0 figure 14.55 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 599 of 1122 rej09b0370-0400 ckio ra dtr ca d1 d2 rd ba 00 id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl / id2 dbreq d0 figure 14.56 single address mo de/cycle steal mode/external bus external device/32-byte block transfer/ on-demand data transfer on channel 4
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 600 of 1122 rej09b0370-0400 14.9 usage notes 1. when modifying sar0?sar3, dar0?dar3, dmatcr0?dmatcr3, and chcr0? chcr3 in the sh7751 or when modifying sar0?sar7, dar0?dar7, dmatcr0? dmatcr7, and chcr0?chcr7 in the sh7751r, first clear the de bit for the relevant channel to 0. 2. the nmif bit in dmaor is set when an nmi interrupt is input even if the dmac is not operating. confirmation method when dma tran sfer is not executed correctly: with the sh7751, read the nmif, ae, and dme bits in dmaor, the de and te bits in chcr0?chcr3, and dmatcr0?dmatcr3. with the sh7751r, read the nmif, ae, and dme bits in dmaor, the de and te bits in chcr0?chcr7, and dmatcr0?dmatcr7. if nmif was set before the transfer, the dmatcr transfer count will remain at the set va lue. if nmif was set during the transfer, when the de bit is 1 and the te bit is 0 in chcr0?chcr3 in the sh7751 or chcr0? chcr7 in the sh7751r, the dmatcr value will i ndicate the remaining number of transfers. also, the next addresses to be accessed can be found by reading sar0?sar3 and dar0? dar3 in the sh7751 or sar0?sar7 and dar0?dar7 in the sh7751r. if the ae bit has been set, an address error has occurred. ch eck the set values in chcr, sar, and dar. 3. check that dma transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. either check that te = 1 in the sh7751's chcr0?chcr3 or in the sh7751r's chcr0? chcr7, or clear dme to 0 in dmaor to termin ate dma transfer. when dme is cleared to 0 in dmaor, transfer halts at the end of th e currently executing dma bus cycle. note, therefore, that transfer may no t end immediately, depending on the transfer data size. dma operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that dma transfer has ended. 4. do not specify a dmac, ccn, bsc, ubc, or pcic control register as the dmac transfer source or destination. 5. when activating the dmac, make the sar, dar, and dmatcr register settings for the relevant channel before setting de to 1 in ch cr, or make the register settings with de cleared to 0 in chcr, then set de to 1. it does not matter whether setting of the dme bit to 1 in dmaor is carried out first or last. to operate the relevant channel, dme and de must both be set to 1. the dmac may not operate norm ally if the sar, dar, and dmatcr settings are not made (with the exception of the unused register in single address mode). 6. after the dmatcr count reaches 0 and dma tr ansfer ends normally, always write 0 to dmatcr even when executing the maximum number of transfers on the same channel.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 601 of 1122 rej09b0370-0400 7. when falling edge detection is used for external requests, keep the external request pin high when making dmac settings. 8. when using the dmac in single address mode , set an external addre ss as the address. all channels will halt due to an address error if an on-chip peripheral module address is set.
14. direct memory access controller (dmac) rev.4.00 oct. 10, 2008 page 602 of 1122 rej09b0370-0400
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 603 of 1122 rej09b0370-0400 section 15 serial co mmunication interface (sci) 15.1 overview this lsi is equipped with a single-channel serial communication interface (sci) and a single- channel serial communication in terface with built-in fifo regist ers (sci with fifo: scif). the sci can handle both asynchronous and synchronous serial communication. the sci supports a smart card interface. this is a serial communication function supporting a subset of the iso/iec 7816-3 (identification card s) standard. for details, see section 17, smart card interface. the scif is a dedicated asynchronous communication serial in terface with built-in 16-stage fifo registers for both transmission an d reception. for details, see sec tion 16, serial communication interface with fifo (scif). 15.1.1 features sci features are listed below. ? choice of synchronous or asynchronous serial communication mode ? asynchronous mode serial data communication is executed us ing an asynchronous system in which synchronization is achieved character by ch aracter. serial data communication can be carried out with standard asynchronous co mmunication chips such as a universal asynchronous receiver/transm itter (uart) or asynchrono us communication interface adapter (acia). a multiprocessor communication function is also provided that enables serial data communication w ith a number of processors. there is a choice of 12 serial data transfer formats. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even/odd/none multiprocessor bit: 1 or 0 receive error detection: parity , overrun, and framing errors break detection: a break can be detected by reading the rxd pin level directly from the serial port register (scsptr1) when a framing error occurs.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 604 of 1122 rej09b0370-0400 ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data transfer format. data length: 8 bits receive error detecti on: overrun errors ? full-duplex communication capability the transmitter and receiver are mutually indepe ndent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources there are four interrupt sour ces?transmit-data-empty, transm it-end, receive-data-full, and receive-error?that can issue re quests independently. the transm it-data-empty interrupt and receive-data-full interrupt can ac tivate the dma controller (dmac) to execute a data transfer. ? when not in use, the sci can be stopped by halting its clock supply to reduce power consumption.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 605 of 1122 rej09b0370-0400 15.1.2 block diagram figure 15.1 shows a block diagram of the sci. module data bus scrdr1 scrsr1 rxd txd sck sctdr1 sctsr1 scssr1 scscr1 scsmr1 scbrr1 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 tei txi rxi eri sci bus interface internal data bus scsptr1 legend: scrsr1: receive shift register scrdr1: receive data register sctsr1: transmit shift register sctdr1: transmit data register scsmr1: serial mode register scscr1: serial control register scssr1: serial status register scbrr1: bit rate register scsptr1: serial port register figure 15.1 block diagram of sci
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 606 of 1122 rej09b0370-0400 15.1.3 pin configuration table 15.1 shows the sci pin configuration. table 15.1 sci pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin txd out put transmit data output note: they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr1 and the c/ a bit in scsmr1. break state transmission and detection, can be set in the sci's scsptr1 register. 15.1.4 register configuration the sci has the internal registers shown in ta ble 15.2. these registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. with the exception of the serial port register, the sci registers ar e initialized in standby mode and in the module standby st ate as well as after a power-on reset or manual reset. when recovering from standby mode or the module standby state, the registers must be set again. table 15.2 sci registers name abbreviation r/w initial value p4 address area 7 address access size serial mode register scsmr1 r/w h'00 h'ffe00000 h'1fe00000 8 bit rate register scbrr1 r/w h'ff h'ffe00004 h'1fe00004 8 serial control register scs cr1 r/w h'00 h'ffe00008 h'1fe00008 8 transmit data register sctdr1 r/w h'ff h'ffe0000c h'1fe0000c 8 serial status register scssr1 r/(w) * 1 h'84 h'ffe00010 h'1fe00010 8 receive data register scrdr 1 r h'00 h'ffe00014 h'1fe00014 8 serial port register scsptr1 r/w h'00 * 2 h'ffe0001c h'1fe0001c 8 notes: 1. only 0 can be written, to clear flags. 2. the value of bits 2 and 0 is undefined
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 607 of 1122 rej09b0370-0400 15.2 register descriptions 15.2.1 receive shift register (scrsr1) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? scrsr1 is the register used to receive serial data. the sci sets serial data input fr om the rxd pin in scrsr1 in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to scrdr1 automatically. scrsr1 cannot be directly read or written to by the cpu. 15.2.2 receive data register (scrdr1) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r scrdr1 is the register that stores received serial data. when the sci has received one byte of serial data , it transfers the received data from scrsr1 to scrdr1 where it is stored, and completes the r eceive operation. scrsr1 is then enabled for reception. since scrsr1 and scrdr1 function as a double buffer in this way, it is possible to receive data continuously. scrdr1 is a read-only register, and cannot be written to by the cpu. scrdr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 608 of 1122 rej09b0370-0400 15.2.3 transmit shift register (sctsr1) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? sctsr1 is the register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from sctdr1 to sctsr1, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from sctdr1 to sctsr1, and transmission started, automati cally. however, data transfer from sctdr1 to sctsr1 is not performed if the tdre flag in the serial status register (scssr1) is set to 1. sctsr1 cannot be directly read or written to by the cpu. 15.2.4 transmit data register (sctdr1) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w sctdr1 is an 8-bit register that st ores data for serial transmission. when the sci detects that sctsr1 is empty, it transfers the transmit data written in sctdr1 to sctsr1 and starts serial transmission. continuo us serial transmission can be carried out by writing the next transmit data to sctdr1 during serial transmission of the data in sctsr1. sctdr1 can be read or written to by the cpu at all times. sctdr1 is initialized to h'ff by a power-on reset or manual reset, in standby mode, and in the module standby state.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 609 of 1122 rej09b0370-0400 15.2.5 serial mode register (scsmr1) bit: 7 6 5 4 3 2 1 0 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scsmr1 is an 8-bit register used to set the sci's serial transfer format and select the baud rate generator clock source. scsmr1 can be read or writte n to by the cpu at all times. scsmr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit 7?communication mode (c/ a ): selects asynchronous mode or synchronous mode as the sci operating mode. bit 7: c/ a description 0 asynchronous mode (initial value) 1 synchronous mode bit 6?character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting, bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (b it 7) of sctdr1 is not transmitted.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 610 of 1122 rej09b0370-0400 bit 5?parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in recepti on, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asyn chronous mode. the o/ e bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit additi on is performed in transmission so that the total number of 1-bits in the transmit character pl us the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bi ts in the receive character plus the parity bit is odd. bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set, the stop bit setting is invalid since stop bits are not added. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bi t) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 611 of 1122 rej09b0370-0400 in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2?multiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. for details of the multiprocessor communication function, see section 15.3.3, multiprocessor communication function. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from pck, pck/4, pck/16, and pck/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, bit rate register (scbrr1). bit 1: cks1 bit 0: cks0 description 0 0 pck clock (initial value) 1 pck/4 clock 1 0 pck/16 clock 1 pck/64 clock note: pck: peripheral clock 15.2.6 serial control register (scscr1) bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scscr1 register performs enabling or disab ling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 612 of 1122 rej09b0370-0400 scscr1 can be read or written to by the cpu at all times. scscr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit 7?transmit interrupt enable (tie): enables or disables transmit-data-empty interrupt (txi) request generation when serial transmit data is transferred from sctdr1 to sctsr1 and the tdre flag in scssr1 is set to 1. bit 7: tie description 0 transmit-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-data-empty interrupt (txi) request enabled note: * txi interrupt requests can be cleared by read ing 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0. bit 6?receive interrupt enable (rie): enables or disables receive -data-full interrupt (rxi) request and receive-error interrupt (eri) request ge neration when serial recei ve data is transferred from scrsr1 to scrdr1 and the rdrf flag in scssr1 is set to 1. bit 6: rie description 0 receive-data-full interrupt (rxi) r equest and receive-error interrupt (eri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) r equest and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt requests can be cleare d by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the fl ag to 0, or by clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5: te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in scssr1 is fixed at 1. 2. in this state, serial transmission is st arted when transmit data is written to sctdr1 and the tdre flag in scssr1 is cleared to 0. scsmr1 setting must be performed to decide the transmit format before setting the te bit to 1.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 613 of 1122 rej09b0370-0400 bit 4?receive enable (re): enables or disables the start of serial reception by the sci. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not a ffect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this stat e when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. scsmr1 setting must be performed to decide the receive format before setting the re bit to 1. bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in scsmr1 is set to 1. the mpie bit setting is invalid in synchronous mode or when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when data with mpb = 1 is received 1 multiprocessor interrupts enabled * note: * when receive data including mpb = 1 is received, the mpie bit is cleared to 0 automatically, and generation of rxi and eri in terrupts (when the tie and rie bits in scscr1 are set to 1) and fer and orer flag setting is enabled. bit 2?transmit-end inte rrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation when there is no valid tr ansmit data in sctdr1 at the time for msb data transmission. bit 2: teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei interrupt requests can be cleared by reading 1 from the tdre flag in scssr1, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 614 of 1122 rej09b0370-0400 bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as the serial clock output pin or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode and in the case of external clock operation (cke1 = 1). the cke1 and cke0 bits must be set before determining the sci's operating mode with scsmr1. for details of clock source selection, see table 15.9 in section 15.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock/sck pin functions as input pin (input signal ignored) * 1 synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 615 of 1122 rej09b0370-0400 15.2.7 serial status register (scssr1) bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 ? 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear the flag. scssr1 is an 8-bit register containing status flag s that indicate the opera ting status of the sci, and multiprocessor bits. scssr1 can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. scssr1 is initialized to h'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit 7?transmit data register empty (tdre): indicates that data has been transferred from sctdr1 to sctsr1 and the next serial transmit data can be written to sctdr1. bit 7: tdre description 0 valid transmit data has been written to sctdr1 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when data is written to sctdr1 by the dmac 1 there is no valid transmit data in sctdr1 (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 ? when data is transferred from sctdr1 to sctsr1 and data can be written to sctdr1
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 616 of 1122 rej09b0370-0400 bit 6?receive data register full (rdrf): indicates that the received data has been stored in scrdr1. bit 6: rdrf description 0 there is no valid receive data in scrdr1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to rdrf after reading rdrf = 1 ? when data in scrdr1 is read by the dmac 1 there is valid receive data in scrdr1 [setting condition] when serial reception ends normally and receive data is transferred from scrsr1 to scrdr1 note: scrdr1 and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scscr1 is cleared to 0. if reception of the next data is completed whil e the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5?overrun error (orer): indicates that an overrun erro r occurred during reception, causing abnormal termination. bit 5: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when the next serial reception is completed while rdrf = 1 notes: 1. the orer flag is not affected and re tains its previous state when the re bit in scscr1 is cleared to 0. 2. the receive data prior to the overrun error is retained in scrdr1, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued either.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 617 of 1122 rej09b0370-0400 bit 4?framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4: fer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to fer after reading fer = 1 1 a framing error occurred during reception [setting condition] when the sci checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scscr1 is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to scrdr1 but the rdrf flag is not set. serial reception cannot be continued while the fer flag is set to 1. bit 3?parity error (per): indicates that a parity error occu rred during reception with parity addition in asynchronous mode, ca using abnormal termination. bit 3: per description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to per after reading per = 1 1 a parity error occurred during reception * 2 [setting condition] when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in scsmr1 notes: 1. the per flag is not affected and retains its previous state when the re bit in scscr1 is cleared to 0. 2. if a parity error occurs, the receive data is transferred to scrdr1 but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 618 of 1122 rej09b0370-0400 bit 2?transmit end (tend): indicates that there is no valid data in sctdr1 when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2: tend description 0 transmission is in progress [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when data is written to sctdr1 by the dmac 1 transmission has been ended (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 ? when tdre = 1 on transmission of the la st bit of a 1-byte serial transmit character bit 1?multiprocessor bit (mpb): this bit is read-only and cannot be written to. the read value is undefined. note: this bit is prepar ed for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode, however, this does not function correctly in this lsi. do not use the read value from this bit. bit 0?multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. unlike transmit data, the mpbt bit is not double -buffered, so it is necessary to check whether transmission has been completed before changing its value. bit 0: mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 619 of 1122 rej09b0370-0400 15.2.8 serial port register (scsptr1) bit: 7 6 5 4 3 2 1 0 eio ? ? ? spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 ? 0 ? r/w: r/w ? ? ? r/w r/w r/w r/w scsptr1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (sci) pins. input data can be read from the rxd pin, output data written to the txd pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. sck pin data reading and output data writing can be performed by means of bits 3 and 2. bit 7 controls enabling and disabling of the rxi interrupt. scsptr1 can be read or written to by the cpu at all times. all scsptr1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. scsptr1 is not initialized in the module standby state or standby mode. bit 7?error interrupt only (eio): when the eio bit is 1, an rxi interrupt request is not sent to the cpu even if the rie bit is set to 1. when the dmac is used, this setting means that only eri interrupts are handled by the cpu. the dmac transfers read data to memory or another peripheral module. this bit specifies enabling or disabling of the rxi interrupt. bit 7: eio description 0 when the rie bit is 1, rxi and eri interrupts are sent to intc (initial value) 1 when the rie bit is 1, only eri interrupts are sent to intc bits 6 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?serial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr1 and the cke1 and cke0 b its in scscr1 should be cleared to 0. bit 3: spb1io description 0 spb1dt bit value is not output to the sck pin (initial value) 1 spb1dt bit value is output to the sck pin
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 620 of 1122 rej09b0370-0400 bit 2?serial port cloc k port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of bit 3, spb1io, for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on or manual reset is undefined. bit 2: spb1dt description 0 input/output data is low-level 1 input/output data is high-level bit 1?serial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr1 should be cleared to 0. bit 1: spb0io description 0 spb0dt bit value is not output to the txd pin (initial value) 1 spb0dt bit value is output to the txd pin bit 0?serial port break data (spb0dt): specifies the serial port rxd pin input data and txd pin output data. the txd pin output condition is specified by the spb0io bit (see the description of bit 1, spb0io, for details). when the txd pin is designated as an output, the value of the spb0dt bit is output to the txd pin. the rxd pin value is read from the spb0dt bit regardless of the value of the spb0io bit. the initial value of this bit after a power-on or manual reset is undefined. bit 0: spb0dt description 0 input/output data is low-level 1 input/output data is high-level
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 621 of 1122 rej09b0370-0400 sci i/o port block diagrams are shown in figures 15.2 to 15.4. reset reset internal data bus sptrw sptrw sci r q d spb1io c r q d spb1dt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * sck le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr1 and the c/ a bit in scsmr1. figure 15.2 sck pin
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 622 of 1122 rej09b0370-0400 reset internal data bus sptrw sci r q d spb0io c reset sptrw r q d spb0dt c txd transmit enable si g nal serial transmit data le g end: sptrw: write to sptr figure 15.3 txd pin internal data bus sci rxd sptrr serial receive data le g end: sptrr: read sptr figure 15.4 rxd pin
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 623 of 1122 rej09b0370-0400 15.2.9 bit rate register (scbrr1) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scbrr1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr1. scbrr1 can be read or written to by the cpu at all times. scbrr1 is initialized to h'ff by a power-on reset or manual reset, in standby mode, and in the module standby state. the scbrr1 setting is found from the following equations. asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b pck synchronous mode: n = 10 6 ? 1 8 2 2n ? 1 b pck where b: bit rate (bits/s) n: scbrr1 setting for baud rate generator (0 n 255) pck: peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr1 setting n clock cks1 cks0 0 pck 0 0 1 pck/4 0 1 2 pck/16 1 0 3 pck/64 1 1
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 624 of 1122 rej09b0370-0400 the bit rate error in asynchronous mode is found from the following equation: error ( % ) = 100 pck 10 6 (n + 1) b 64 2 2n ? 1 ? 1 table 15.3 shows sample scbrr1 settings in asynchronous mode, and table 15.4 shows sample scbrr1 settings in synchronous mode.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 625 of 1122 rej09b0370-0400 table 15.3 examples of bi t rates and scbrr1 settings in asynchronous mode pck (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 pck (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 626 of 1122 rej09b0370-0400 pck (mhz) 6 6.144 7.37288 8 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 0 6 ?6.99 pck (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 627 of 1122 rej09b0370-0400 pck (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 pck (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73 legend: blank: no setting is available. ?: a setting is available but error occurs.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 628 of 1122 rej09b0370-0400 table 15.4 examples of bit rates and scbrr1 settings in synchronous mode pck (mhz) 4 8 16 28.7 30 bit rate (bits/s) n n n n n n n n n n 10 ? ? ? ? ? ? ? ? ? ? 250 2 249 3 124 3 249 ? ? ? ? 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 ? ? 0 29 500k 0 1 0 3 0 7 ? ? 0 14 1m 0 0 * 0 1 0 3 ? ? ? ? 2m 0 0 * 0 1 ? ? ? ? legend: blank: no setting is available. ?: a setting is available but error occurs. notes: as far as possible, the setting s hould be made so that the error is within 1 % . * continuous transmission/reception is not possible.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 629 of 1122 rej09b0370-0400 table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. tables 15.6 and 15.7 show the maximum bit rates with external clock input. table 15.5 maximum bit rate for various frequencies with baud rate generator (asynchronous mode) settings pck (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 630 of 1122 rej09b0370-0400 table 15.6 maximum bit rate with external clock input (asynchronous mode) pck (mhz) external input clock (mh z) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 15.7 maximum bit rate with ext ernal clock input (synchronous mode) pck (mhz) external input clock (mh z) maximum bit rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 631 of 1122 rej09b0370-0400 15.3 operation 15.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or synchronous mode and the transmission format is made using scsmr1 as shown in table 15.8. the sci clock so urce is determined by a combination of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1, as shown in table 15.9. ? asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addi tion, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overru n errors, and breaks, during reception ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. when external clock is selected : a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). ? synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip. when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 632 of 1122 rej09b0370-0400 table 15.8 scsmr1 settings for serial transfer format selection scsmr1 settings sci transfer format bit 7: c/ a bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length multi- processor bit parity bit stop bit length 0 1 bit 0 1 no 2 bits 0 1 bit 0 1 1 8-bit data yes 2 bits 0 1 bit 0 1 no 2 bits 0 1 bit 1 0 1 1 asynchronous mode 7-bit data no yes 2 bits 0 no 1 bit 0 1 8-bit data 2 bits 0 1 bit 0 1 1 * 1 asynchronous mode (multiprocessor format) 7-bit data yes 2 bits 1 * * * * synchronous mode 8-bit data no none note: an asterisk in the table means ?don't care.?
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 633 of 1122 rej09b0370-0400 table 15.9 scsmr1 and scscr1 settings for sci clock source selection scsmr1 scscr1 setting sci transmit/receive clock bit 7: c/ a bit 1: cke1 bit 0: cke0 mode clock source sck pin function 0 0 0 internal sci does not use sck pin 1 outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times the bit rate 1 asynchronous mode 1 0 0 internal outputs serial clock 1 1 0 synchronous mode external inputs serial clock 1 15.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or r eceived, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by- character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receive r also have a double-buffered structure, so that data can be read or written during transm ission or reception, enabling continuous data transfer. figure 15.5 shows the general format for asynchronous serial communication. in asynchronous serial co mmunication, the transmission line is us ually held in the mark state (high level). the sci monitors the transmission line, an d when it goes to the space state (low level), recognizes a start bit and st arts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 634 of 1122 rej09b0370-0400 serial data (lsb) 7 or 8 bits one unit of transfer data (character or frame) parity bit 1 bit, or none 1 or 2 bits stop bit(s) 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 idle state (mark state) start bit 1 bit (msb) transmit/receive data figure 15.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) data transfer format table 15.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the scsmr1 setting.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 635 of 1122 rej09b0370-0400 table 15.10 serial transfer formats (asynchronous mode) scsmr1 settings serial transfer format and frame length chr pe mp stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 s 8-bit data stop 0 0 0 1 s 8-bit data stop stop 0 1 0 0 s 8-bit data p stop 0 1 0 1 s 8-bit data p stop stop 1 0 0 0 s 7-bit data stop 1 0 0 1 s 7-bit data stop stop 1 1 0 0 s 7-bit data p stop 1 1 0 1 s 7-bit data p stop stop 0 * 1 0 s 8-bit data mpb stop 0 * 1 1 s 8-bit data mpb stop stop 1 * 1 0 s 7-bit data mpb stop 1 * 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 636 of 1122 rej09b0370-0400 mpb: multiprocessor bit note: an asterisk in the table means ?don't care.? clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci's se rial clock, according to the setting of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1. for details of sci clock source selection, see table 15.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 one frame 0 figure 15.6 relation between outp ut clock and transfer data phase (asynchronous mode) data transfer operations sci initialization (asynchronous mode): before transmitting and receiving data, it is necessary to clear the te and re bits in scscr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and sctsr1 is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, pe r, fer, and orer flags, or the contents of scrdr1. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 15.7 shows a sample sci initialization flowchart.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 637 of 1122 rej09b0370-0400 initialization clear te and re bits in scscr1 to 0 set cke1 and cke0 bits in scscr1 (leavin g te and re bits cleared to 0) set data transfer format in scsmr1 set value in scbrr1 1-bit interval elapsed? set te and re bits in scscr1 to 1, and set rie, tie, teie, and mpie bits end yes wait no 1. set the clock selection in scscr1. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when clock output is selected in asynchronous mode, it is output immediately after scscr1 settin g s are made. 2. set the data transfer format in scsmr1. 3. write a value correspondin g to the bit rate into scbrr1. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr1 to 1. also set the rie, tie, teie, and mpie bits. settin g the te and re bits enables the txd and rxd pins to be used. when transmittin g , the sci will g o to the mark state; when receivin g , it will g o to the idle state, waitin g for a start bit. figure 15.7 sample sci initialization flowchart serial data transmission (asynchronous mode): figure 15.8 shows a sample flowchart for serial transmission. use the following procedure for serial data transm ission after enabling the sci for transmission.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 638 of 1122 rej09b0370-0400 start of transmission read tdre fla g in scssr1 tdre = 1? all data transmitted? tend = 1? break output? clear te bit in scscr1 to 0 end of transmission yes no yes no yes no yes no write transmit data to sctdr1 and clear tdre fla g in scssr1 to 0 read tend fla g in scssr1 clear spb0dt to 0 and set spb0io to 1 1. sci status check and transmit data write: read scssr1 and check that the tdre fla g is set to 1, then write transmit data to sctdr1 and clear the tdre fla g to 0. 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre fla g to confirm that writin g is possible, then write data to sctdr1, and then clear the tdre fla g to 0. (checkin g and clearin g of the tdre fla g is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) 3. break output at the end of serial transmission: to output a break in serial transmission, clear the spb0dt bit to 0 and set the spb0io bit to 1 in scsptr, then clear the te bit in scscr1 to 0. figure 15.8 sample serial transmission flowchart
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 639 of 1122 rej09b0370-0400 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre fl ag in scssr1. when tdre is cl eared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to scts r1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. (a format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from sctdr1 to sctsr1, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in scssr1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is outp ut continuously. if the teie bit in scscr1 is set to 1 at this time, a tei in terrupt request is generated. figure 15.9 shows an example of the operation for transmission in asynchronous mode.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 640 of 1122 rej09b0370-0400 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdre tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to sctdr1 and tdre fla g cleared to 0 by txi interrupt handler one frame tei interrupt request txi interrupt request figure 15.9 example of transmit operation in asynchronous mode (example with 8-bit data, parity, one stop bit) serial data reception (asynchronous mode): figure 15.10 shows a sample flowchart for serial reception. use the following procedure for serial data reception after enabling th e sci for reception.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 641 of 1122 rej09b0370-0400 start of reception read orer, per, and fer fla g s in scssr1 read rdrf fla g in scssr1 per or fer or orer = 1? rdrf = 1? all data received? clear re bit in scscr1 to 0 end of reception error handlin g yes no yes no yes no read receive data in scrdr1, and clear rdrf fla g in scssr1 to 0 1. receive error handlin g and break detection: if a receive error occurs, read the orer, per, and fer fla g s in scssr1 to identify the error. after performin g the appropriate error handlin g , ensure that the orer, per, and fer fla g s are all cleared to 0. reception cannot be resumed if any of these fla g s are set to 1. in the case of a framin g error, a break can be detected by readin g the value of the rxd pin. 2. sci status check and receive data read : read scssr1 and check that rdrf = 1, then read the receive data in scrdr1 and clear the rdrf fla g to 0. 3. serial reception continuation procedure: to continue serial reception, complete zero- clearin g of the rdrf fla g before the stop bit for the current frame is received. (the rdrf fla g is cleared automatically when the direct memory access controller (dmac) is activated by an rxi interrupt and the scrdr1 value is read.) figure 15.10 sample serial reception flowchart (1)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 642 of 1122 rej09b0370-0400 error handlin g orer = 1? fer = 1? break? per = 1? end yes yes no yes no no no yes clear orer, per, and fer fla g s in scssr1 to 0 parity error handlin g framin g error handlin g clear re bit in scscr1 to 0 overrun error handlin g figure 15.10 sample serial reception flowchart (2)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 643 of 1122 rej09b0370-0400 in serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 start bit is det ected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr1 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. a. parity check: the sci checks whether the numbe r of 1-bits in the recei ve data agrees with the parity (even or odd) set in the o/ e bit in scsmr1. b. stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. c. status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from scrsr1 to scrdr1. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in scrdr1. if a receive error is detected in the error chec k, the operation is as shown in table 15.11. note: no further receive operations can be pe rformed when a receive error has occurred. also note that the rdrf flag is not set to 1 in rece ption, and so the error flags must be cleared to 0. 4. if the eio bit in scsptr1 is cleared to 0 an d the rie bit in scscr1 is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. if the rie bit in scscr1 is set to 1 when the orer, per, or fer flag changes to 1, a receive-error interrupt (eri) request is generate d. a receive-data-full re quest is always output to the dmac when the rdrf flag changes to 1. table 15.11 receive error conditions receive error abbreviation condition data transfer overrun error orer reception of next data is completed while rdrf flag in scssr1 is set to 1 receive data is not transferred from scrsr1 to scrdr1 framing error fer stop bit is 0 receive data is transferred from scrsr1 to scrdr1 parity error per received data parity differs from that (even or odd) set in scsmr1 receive data is transferred from scrsr1 to scrdr1 figure 15.11 shows an example of the operation for reception in asynchronous mode.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 644 of 1122 rej09b0370-0400 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdrf fer serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame scrdr1 data read and rdrf fla g cleared to 0 by rxi interrupt handler eri interrupt request g enerated by framin g error figure 15.11 example of sci receive operation (example with 8-bit data, parity, one stop bit) 15.3.3 multiprocessor co mmunication function the multiprocessor communication function pe rforms serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing a serial tr ansmission line. when multiprocessor communication is carried ou t, each receiving stat ion is addressed by a unique id code. the serial communication cycle consists of two cy cles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. th e multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with wh ich it wants to perform serial communication as data with the multiprocessor bit set to 1. it then sends transmit data as data with the multiprocessor bit cleared to 0. the receiving station skips the data until data with the multip rocessor bit set to 1 is sent. when data with a 1 multiprocessor b it is received, the receiving statio n compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 645 of 1122 rej09b0370-0400 figure 15.12 shows an example of inter-proce ssor communication using a multiprocessor format. note: even when this lsi has received data with a 0 multiprocessor bit that was meant to be sent to another station, the rdrf flag in scssr1 is set to 1. when the rdrf flag in scssr1 is set to 1, the exception handling routine reads the mpie bit in scscr1, and skips the receive data if the mpie b it is 1. skipping of unnecessary data is achieved by collaborative operation with the exception handling routine. transmittin g station receivin g station a receivin g station b receivin g station c receivin g station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line (mpb = 1) (mpb = 0) h'01 h'aa le g end: mpb: multiprocessor bit serial data id transmission cycle: receivin g station specification data transmission cycle: data transmission to receivin g station specified by id figure 15.12 example of in ter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 646 of 1122 rej09b0370-0400 data transfer formats there are four data transfer form ats. when the multipro cessor format is specified, the parity bit specification is invalid. for details, see table 15.10. clock see the description under clock in section 15.3.2, operation in asynchronous mode. data transfer operations multiprocessor serial data transmission: figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. use the following procedure for multiprocessor seri al data transmission after enabling the sci for transmission.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 647 of 1122 rej09b0370-0400 start of transmission read tend fla g in scssr1 tend = 1? clear tdre fla g to 0 read tend fla g in scssr1 tend = 1? clear mpbt bit in scssr1 to 0 write data to sctdr1 clear tdre fla g to 0 read tdre fla g in scssr1 end of transmission no yes no yes all data transmitted? tdre = 1? yes yes no no set mpbt bit in scssr1 to 1 and write id data to sctdr1 1. sci status check and id data write: read scssr1 and check that the tend fla g is set to 1, then set the mpbt bit in scssr1 to 1 and write id data to sctdr1. finally, clear the tdre fla g to 0. 2. preparation for data transfer: read scssr1 and check that the tend fla g is set to 1, then set the mpbt bit in scssr1 to 1. 3. serial data transmission: write the first transmit data to sctdr1, then clear the tdre fla g to 0. to continue data transmission, be sure to read 1 from the tdre fla g to confirm that writin g is possible, then write data to sctdr1, and then clear the tdre fla g to 0. (checkin g and clearin g of the tdre fla g is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) figure 15.13 sample multiprocessor serial tr ansmission flowchart
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 648 of 1122 rej09b0370-0400 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in scssr1. wh en tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to scts r1, the sci sets the tdre flag to 1 and starts transmission. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is set to 1, the tend flag in scssr1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. if the teie bit in scscr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. the sci monitors the tdre fl ag. when tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transf ers the data from sctdr1 to sctsr1. 5. after transferring data from sctdr1 to scts r1, the sci sets the tdre flag to 1 and starts transmitting. if the transmit-data-emp ty interrupt enable bit (tie bit) in scscr1 is set to 1 at this time, a transmit-data-empty interrupt (txi) request is generated. the order of transmission is the same as in step 2. figure 15.14 shows an example of sci operation for transmission using a multiprocessor format.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 649 of 1122 rej09b0370-0400 serial data mpbt bit cleared to 0, data written to sctdr1, and tdre fla g cleared to 0 by tei interrupt handler data written to sctdr1 and tdre fla g cleared to 0 by txi interrupt handler txi interrupt request tei interrupt request 1 1 0d0d1 d7 0 0 0 d0 d1 d7 0 d0 d1 d7 11 1 multi- proces- sor bit multi- proces- sor bit multi- proces- sor bit stop bit start bit stop bit stop bit start bit data data data start bit tdre tend one frame idle state (mark state) figure 15.14 example of sci transmit operation (example with 8-bit data, multiprocessor bit, one stop bit) multiprocessor serial data reception 1. method for determining wh ether an interrupt generated during receive operation is a multiprocessor interrupt when an interrupt such as rxi occurs du ring receive operation using the on-chip sci multiprocessor communication function, check the state of the mpie bit in the scscr1 register as part of the interrupt handling routine. a. if the mpie bit in the scscr1 register is set to 1 ignore the received data. data with the multiprocessor bit (mpb) set to 0 and intended for another station was received, and the rdrf bit in the scscr1 re gister was set to 1. therefore, clear the rdrf bit in the scscr1 register to 0. b. if the mpie bit in the scsc r1 register is cleared to 0 a multiprocessor interrupt indicating that data (id) with the multiprocessor bit (mpb) set to 1 was received, or a receive data full in terrupt (rxi) occurred when data with the multiprocessor bit (mpb) se t to 0 and intended for this station was received. 2. method for determining whethe r received data is id or data do not use the mpb bit in the scssr1 register for software processing.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 650 of 1122 rej09b0370-0400 when using software processing to determine wh ether received data is id (mpb = 1) or data (mpb = 0), use a procedur e such as saving a user-defined fl ag in memory to indicate receive start. figure 15.15 shows a flowchart of a sample software workaround.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 651 of 1122 rej09b0370-0400 receive data full interrupt generated no no no no no no yes yes yes yes yes yes user-defined receive start flag = 1 ? read orer and fer flags in scssr1 read rdrf flag in scssr1 read receive data in scrdr1 set user-defined receive start flag to 1 end of id reception handling end of data reception rte error handling read orer and fer flags in scssr1 read receive data in scrdr1 clear user-defined receive start flag to 0 set rdrf = 0 and mpie = 1 fer or orer = 1 ? fer or orer = 1 ? mpie = 0 ? this station's id ? all data received ? figure 15.15 sample flowchart of multip rocessor serial reception with interrupt generation figure 15.16 shows a sample flowchart of multiprocessor serial r eception. to perform multiprocessor serial reception, first enable the sci for data reception and then follow the procedure shown below.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 652 of 1122 rej09b0370-0400 start of reception no no no no no no no yes yes yes yes yes yes yes set mpie bit to 1 user-defined receive start fla g = 1? read orer and fer fla g s in scssr1 read rdrf fla g in scssr1 read receive data in scrdr1 set user-defined receive start fla g to 1 read orer and fer fla g s in scssr1 read receive data in scrdr1 clear user-defined receive start fla g to 0 set rdrf = 0 and mpie = 1 fer or orer = 1 ? fer or orer = 1 ? mpie = 0 ? this station's id? all data received? end of data reception rte error handlin g rxi = 1 ? end of id reception handlin g figure 15.16 sample multiprocessor serial reception flowchart (1)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 653 of 1122 rej09b0370-0400 orer = 1? fer = 1? error handlin g overrun error handlin g break? framin g error handlin g clear re bit in scscr1 to 0 clear orer and fer fla g s in scssr1 to 0 end yes no no yes yes no figure 15.16 sample multiprocessor serial reception flowchart (2)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 654 of 1122 rej09b0370-0400 figure 15.17 shows an example of sci operation for multiprocesso r format reception. 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpie rdrf id1 id2 data2 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpb mpie rdrf scrdr1 value id1 serial data start bit data (id1) stop bit start bit idle state (mark state) data (data1) stop bit (b) data matches station's id rxi interrupt request (multiprocessor interrupt) mpie = 0 scrdr1 data read and rdrf fla g cleared to 0 by rxi interrupt handler as data is not this station's id, mpie bit is set to 1 a g ain rxi interrupt request mpb serial data start bit data (id2) stop bit start bit data (data2) stop bit idle state (mark state) (a) data does not match station's id scrdr1 value rxi interrupt request (multiprocessor interrupt) mpie = 0 scrdr1 data read and rdrf fla g cleared to 0 by rxi interrupt handler as data matches this station's id, reception continues and data is received by rxi interrupt handler mpie bit set to 1 a g ain the rdrf fla g is cleared to 0 by is the rxi interrupt handler figure 15.17 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 655 of 1122 rej09b0370-0400 in multiprocessor mode serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 start bit is det ected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr1 in lsb-to-msb order. 3. if the mpie bit is 1, mpie is cleared to 0 when a 1 is received in the multiprocessor bit position. if the multiprocessor bit is 0, the mpie bit is not changed. 4. if the mpie bit is 0, rdrf is checked at the stop bit position, and if rdrf is 1 the overrun error bit is set. if the stop bit is not 0, the framing error bit is set. if rdrf is 0, the value in scrsr1 is transferred to scrdr1, and if the stop bit is 0, rdrf is set to 1. 15.3.4 operation in synchronous mode in synchronous mode, data is transmitted or receive d in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receive r also have a double-buffered structure, so that data can be read or written during transm ission or reception, enabling continuous data transfer. figure 15.18 shows the general format for synchronous serial communication. one unit of transfer data (character or frame) note: * hi g h except in continuous transfer serial clock serial data lsb bit 0 msb * * bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 don't care don't care figure 15.18 data format in synchronous communication
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 656 of 1122 rej09b0370-0400 in synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in serial communication, one char acter consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in synchronous mode, the sci receives data in sync hronization with the falling edge of the serial clock. data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected , according to the setting of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1. for details of sci clock source selection, see table 15.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transf er of one character, and when no transfer is performed the clock is fi xed high. in reception only, if an on -chip clock source is selected, clock pulses are output while re = 1. wh en the last data is received, re should be cleared to 0 before the end of bit 7. data transfer operations sci initialization (synchronous mode): before transmitting and receiving data, it is necessary to clear the te and re bits in scscr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and sctsr1 is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, pe r, fer, and orer flags, or the contents of scrdr1. figure 15.19 shows a sample sci initialization flowchart.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 657 of 1122 rej09b0370-0400 set data transfer format in scsmr1 1-bit interval elapsed? end no wait yes set te and re bits in scscr1 to 1, and set rie, tie, teie, and mpie bits set value in scbrr1 set rie, tie, teie, mpie, cke1 and cke0 bits in scscr1 (leavin g te and re bits cleared to 0) clear te and re bits in scscr1 to 0 initialization 1. set the clock selection in scscr1. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. 2. set the data transfer format in scsmr1. 3. write a value correspondin g to the bit rate into scbrr1. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr1 to 1. also set the rie, tie, teie, and mpie bits. settin g the te and re bits enables the txd and rxd pins to be used. figure 15.19 sample sci initialization flowchart
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 658 of 1122 rej09b0370-0400 serial data transmission (synchronous mode): figure 15.20 shows a sample flowchart for serial transmission. use the following procedure for serial data transm ission after enabling the sci for transmission. start of transmission read tdre fla g in scssr1 tdre = 1? all data transmitted? read tend fla g in scssr1 clear te bit in scscr1 to 0 end tend = 1? no yes no yes yes no write transmit data to sctdr1 and clear tdre fla g in scssr1 to 0 1. sci status check and transmit data write: read scssr1 and check that the tdre fla g is set to 1, then write transmit data to sctdr1 and clear the tdre fla g to 0. 2. to continue serial transmission, be sure to read 1 from the tdre fla g to confirm that writin g is possible, then write data to sctdr1, and then clear the tdre fla g to 0. (checkin g and clearin g of the tdre fla g is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) figure 15.20 sample serial transmission flowchart
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 659 of 1122 rej09b0370-0400 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre fl ag in scssr1. when tdre is cl eared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to scts r1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a transmit-data-empty interrupt (txi) request is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). 3. the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is tr ansferred from sctdr1 to sctsr1, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in sc ssr1 is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scscr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. after completion of serial transmission, the sck pin is fixed high. figure 15.21 shows an example of sci operation in transmission.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 660 of 1122 rej09b0370-0400 lsb msb tdre tend bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 serial clock serial data transfer direction txi interrupt request data written to sctdr1 and tdre fla g cleared to 0 in txi interrupt handler tei interrupt request one frame txi interrupt request figure 15.21 example of sci transmit operation serial data reception (synchronous mode): figure 15.22 shows a sample flowchart for serial reception. use the following procedure for serial data reception after enabling th e sci for reception. when changing the operating mode from asynchronous to synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 661 of 1122 rej09b0370-0400 start of reception read orer fla g in scssr1 orer = 1? read rdrf fla g in scssr1 rdrf = 1? read receive data in scrdr1, and clear rdrf fla g in scssr1 to 0 all data received? clear re bit in scscr1 to 0 end of reception yes no yes yes no no error handlin g 1. receive error handlin g : if a receive error occurs, read the orer fla g in scssr1 , and after performin g the appropriate error handlin g , clear the orer fla g to 0. transfer cannot be resumed if the orer fla g is set to 1. 2. sci status check and receive data read: read scssr1 and check that the rdrf fla g is set to 1, then read the receive data in scrdr1 and clear the rdrf fla g to 0. transition of the rdrf fla g from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, finish readin g the rdrf fla g , readin g scrdr1, and clearin g the rdrf fla g to 0, before the msb (bit 7) of the current frame is received. (the rdrf fla g is cleared automatically when the direct memory access controller (dmac) is activated by a receive-data-full interrupt (rxi) request and the scrdr1 value is read.) figure 15.22 sample serial reception flowchart (1)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 662 of 1122 rej09b0370-0400 error handlin g overrun error handlin g clear orer fla g in scssr1 to 0 orer = 1? end yes no figure 15.22 sample serial reception flowchart (2) in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in scrsr1 in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from scrsr1 to scrdr1. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in scrdr1. if a receive error is detected in the error chec k, the operation is as shown in table 15.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. also, as the rdrf flag is not set to 1 when receiving, the flag mu st be cleared to 0. 3. if the rie bit in scrsr1 is set to 1 when the rdrf flag ch anges to 1, a receive-data-full interrupt (rxi) request is generated. if the rie bit in scrsr1 is set to 1 when the orer flag changes to 1, a receive-error interr upt (eri) request is generated. figure 15.23 shows an example of sci operation in reception.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 663 of 1122 rej09b0370-0400 rdrf orer transfer direction serial clock serial data bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request data read from scrdr1 and rdrf fla g cleared to 0 in rxi interrupt handler one frame rxi interrupt request eri interrupt request due to overrun error figure 15.23 example of sci receive operation simultaneous serial data transmission and reception (syn chronous mode): figure 15.24 shows a sample flowchart for simultaneous serial transmit and receive operations. use the following procedure for simultaneous serial data transmit and receive operations after enabling the sci for tran smission and reception.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 664 of 1122 rej09b0370-0400 read tdre fla g in scssr1 tdre = 1? write transmit data to sctdr1 and clear tdre fla g in scssr1 to 0 read orer fla g in scssr1 orer = 1? error handlin g read rdrf fla g in scssr1 rdrf = 1? read receive data in scrdr1, and clear rdrf fla g in scssr1 to 0 all data transferred? clear te and re bits in scrsr1 to 0 end of transmission/reception start of transmission/reception no yes yes no no yes yes no 1. sci status check and transmit data write: read scssr1 and check that the tdre fla g is set to 1, then write transmit data to sctdr1 and clear the tdre fla g to 0. transition of the tdre fla g from 0 to 1 can also be identified by a txi interrupt. 2. receive error handlin g : if a receive error occurs, read the orer fla g in scssr1 , and after performin g the appropriate error handlin g , clear the orer fla g to 0. transmission/reception cannot be resumed if the orer fla g is set to 1. 3. sci status check and receive data read: read scssr1 and check that the rdrf fla g is set to 1, then read the receive data in scrdr1 and clear the rdrf fla g to 0. transition of the rdrf fla g from 0 to 1 can also be identified by an rxi interrupt. 4. serial transmission/reception continuation procedure: to continue serial transmission/ reception, finish readin g the rdrf fla g , readin g scrdr1, and clearin g the rdrf fla g to 0, before the msb (bit 7) of the current frame is received. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre fla g to confirm that writin g is possible, then write data to sctdr1 and clear the tdre fla g to 0. (checkin g and clearin g of the tdre fla g is automatic when the dmac is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1. similarly, the rdrf fla g is cleared automatically when the dmac is activated by a receive-data-full interrupt (rxi) request and the scrdr1 value is read.) note: when switchin g from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1. figure 15.24 sample flowchart for serial data transmission and reception
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 665 of 1122 rej09b0370-0400 15.4 sci interrupt sources and dmac the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full in terrupt (rxi) request, and tran smit-data-empty interrupt (txi) request. table 15.12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scrsr1, and the eio bit in scsptr1. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in the serial status register (scssr1) is set to 1, a tdr-empty request is generated separately from the interrupt request . a tdr-empty request can activate the direct memory access controller (dmac) to perform data transfer. the tdre flag is cleared to 0 automatically when a write to the transmit data register (sctdr1) is performed by the dmac. when the rdrf flag in scssr1 is set to 1, an rdr-full request is generated separately from the interrupt request. an rdr-full request can ac tivate the dmac to perform data transfer. the rdrf flag is cleared to 0 automatically wh en a receive data register (scrdr1) read is performed by the dmac. when the orer, fer, or per flag in scssr1 is se t to 1, an eri interrupt request is generated. the dmac cannot be activated by an eri interrupt request. when receive data processing is to be carried out by the dmac and receive error handling is to be performed by means of an interrupt to the cpu, set the rie bit to 1 and also set the eio bit in scsptr1 to 1 so that an interrupt error occurs only for a receive error. if the eio bit is cleared to 0, interrupts to the cpu will be generated even during normal data reception. when the tend flag in scssr1 is set to 1, a tei interrupt request is generated. the dmac cannot be activated by a tei interrupt request. a txi interrupt indicates that transmit data can be written, and a tei interrupt indicates that the transmit operation has ended.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 666 of 1122 rej09b0370-0400 table 15.12 sci interrupt sources interrupt source description dmac activation priority on reset release eri receive error (orer, fer, or per) not possible high rxi receive data register full (rdrf) possible txi transmit data register empty (tdre) possible tei transmit end (tend) not possible low see section 5, exceptions, for the priority order and relation to non-sci interrupts. 15.5 usage notes the following points should be noted when using the sci. sctdr1 writing and the tdre flag: the tdre flag in scssr1 is a status flag that indicates that transmit data has been transferred from sc tdr1 to sctsr1. when the sci transfers data from sctdr1 to sctsr1, the tdre flag is set to 1. data can be written to sctdr1 regardless of the state of the tdre flag. however, if new data is written to sctdr1 when the tdre flag is cleared to 0, the data stored in sctdr1 will be lost since it has not yet been transferred to sctsr1. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to sctdr1. simultaneous multip le receive errors: if a number of receive errors occur at the same time, the state of the status flags in scssr1 is as shown in table 15.13. if there is an overrun error, data is not transferred from scrsr1 to scrd r1, and the receive data is lost.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 667 of 1122 rej09b0370-0400 table 15.13 scssr1 status flags and transfer of receive data scssr1 status flags receive errors rdrf orer fer per receive data transfer scrsr1 scrdr1 overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x legend: o: receive data is transferred from scrsr1 to scrdr1. x: receive data is not transferred from scrsr1 to scrdr1. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the br eak state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity erro r flag (per) may also be set. note that the sci receiver continues to operate in the break state, so if the fer flag is cleared to 0 it will be set to 1 again. sending a break signal: the input/output condition and level of the txd pin are determined by bits spb0io and spb0dt in the serial port register (scsptr1). this feature can be used to send a break signal. after the serial transmitter is initialized, the txd pin function is not selected and the value of the spb0dt bit substitutes for the mark state until the te bit is set to 1 (i.e. transmission is enabled). the spb0io and spb0dt bits should therefore be set to 1 (designating output and high level) beforehand. to send a break signal during serial transmissi on, clear the spb0dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of its current state, and the txd pin becomes an output port outputting the value 0.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 668 of 1122 rej09b0370-0400 handling of tend flag and te bit: the tend flag is set to 1 when the stop bit of the final data segment is transmitted. if the te bit is cl eared immediately after confirming that the tend flag was set, transmission may not complete proper ly because stop bit transmission processing is still underway. therefore, wait at leas t 0.5 serial clock cycles (1.5 cy cles if two stop bits are used) after confirming that the tend flag was set before clearing the te bit. receive error flags and transmit op erations (synchronous mode only): transmission cannot be started when a receive er ror flag (orer, per, or fer) is set to 1, even if the tdre flag is set to 1. be sure to clear the receive error flags to 0 before starting transmission. note also that the receive error flags are not cleared to 0 by clearing the re bit to 0. receive data sampling timi ng and receive margin in asynchronous mode: the sci operates on a base clock with a frequency of 16 times the bit rate. in reception, the sci synchronizes internally with the fall of the start bit, which it sa mples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 15.25. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (rxd) start bit ?7.5 clocks +7.5 clocks synchronization samplin g timin g data samplin g timin g figure 15.25 receive data sampling timing in asynchronous mode the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n ................ (1)
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 669 of 1122 rej09b0370-0400 m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % ............................................ (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % . when using the dmac: when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after sctdr1 is updated by the dmac. incorrect operation may result if the transmit clock is input within 4 cycles after sctdr1 is updated. (see figure 15.26) sck tdre txd d0 d1 d2 d3 d4 d5 d6 d7 t note: when operatin g on an external clock, set t > 4. figure 15.26 example of synchronous transmission by dmac when scrdr1 is read by the dmac, be sure to set the sci receive-data-full interrupt (rxi) as the activation source with bits rs3 to rs0 in chcr. when using synchronous external clock mode: ? do not set te or re to 1 until at least 4 peripheral operating clock cycles after external clock sck has changed from 0 to 1. ? only set both te and re to 1 when external clock sck is 1.
15. serial communication interface (sci) rev.4.00 oct. 10, 2008 page 670 of 1122 rej09b0370-0400 ? in reception, note that if re is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck input, rdrf will be set to 1 but copying to scrdr1 will not be possible. when using synchronous internal clock mode: in reception, note that if re is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck output, rdrf will be set to 1 but copying to scrdr1 will not be possible. when using dmac: when using the dmac for transmission/reception, make a setting to suppress output of rxi and txi interrupt requests to the interrupt controller. even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the dmac independently of the interrupt handling program.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 671 of 1122 rej09b0370-0400 section 16 serial communi cation interface with fifo (scif) 16.1 overview this lsi is equipped with a single-channel serial communication interface with built-in fifo buffers (serial communication in terface with fifo: scif ). the scif can perform asynchronous serial communication. sixteen-stage fifo registers ar e provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 features scif features are listed below. ? asynchronous serial communication serial data communication is executed us ing an asynchronous system in which synchronization is achieved character by charact er. serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchrono us communication interface adapter (acia). there is a choice of 8 serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? receive error detection: parity , framing, and overrun errors ? break detection: if the receive data following that in which a framing error occurred is also at the space ?0? level, and there is a frame erro r, a break is detected. when a framing error occurs, a break can also be det ected by reading the rxd2 pin le vel directly from the serial port register (scsptr2). ? full-duplex communication capability the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 16-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 672 of 1122 rej09b0370-0400 ? choice of serial clock source: internal clock from baud rate generator or external clock from sck2 pin ? four interrupt sources there are four interrupt sour ces?transmit-fifo-dat a-empty, break, receive-fifo-data-full, and receive-error?that can is sue requests independently. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data-empty or receive-fifo-data-full interrupt. ? when not in use, the scif can be stopped by halting its clock supply to reduce power consumption. ? modem control functions ( rts2 and cts2 ) are provided. ? the amount of data in the transm it/receive fifo registers, and th e number of receive errors in the receive data in the receive fi fo register, can be ascertained. ? a timeout error (dr) can be detected during reception.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 673 of 1122 rej09b0370-0400 16.1.2 block diagram figure 16.1 shows a block diagram of the scif. module data bus scfrdr2 (16-stage) scrsr2 rxd2 txd2 sck2 cts2 rts2 scftdr2 (16-stage) sctsr2 scsmr2 sclsr2 scfdr2 scfcr2 scfsr2 scbrr2 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 txi rxi eri bri scif bus interface internal data bus scscr2 scsptr2 legend: scrsr2: receive shift register scfrdr2: receive fifo data register sctsr2: transmit shift register scftdr2: transmit fifo data register scsmr2: serial mode register scscr2: serial control register scfsr2: serial status register scbrr2: bit rate register scsptr2: serial port register scfcr2: fifo control register scfdr2: fifo data count register sclsr2: line status register figure 16.1 block diagram of scif
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 674 of 1122 rej09b0370-0400 16.1.3 pin configuration table 16.1 shows the scif pin configuration. table 16.1 scif pins pin name abbreviation i/o function serial clock pin md0/sc k2 i/o clock input/output receive data pin md2/rxd2 input receive data input transmit data pin md1/txd2 output transmit data output modem control pin md7/ cts2 i/o transmission enabled modem control pin md8/ rts2 i/o transmission request note: these pins function as the md0, md1, md 2, md7, and md8 mode input pins after a power- on reset. these pins are made to function as serial pins by performing scif operation settings with the te, re, cke1, and cke0 bits in scscr2 and the mce bit in scfcr2. break state transmission and detection can be set in the scif's scsptr2 register. 16.1.4 register configuration the scif has the internal registers shown in tabl e 16.2. these registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. table 16.2 scif registers name abbrevia- tion r/w initial value p4 address area 7 address access size serial mode register scsmr2 r/w h'0000 h'ffe80000 h'ife80000 16 bit rate register scbrr2 r/w h'ff h'ffe80004 h'ife80004 8 serial control register scs cr2 r/w h'0000 h'ffe80008 h'ife80008 16 transmit fifo data register scftdr2 w undefined h'ffe8000c h'ife8000c 8 serial status register scfsr2 r/(w) * 1 h'0060 h'ffe80010 h'ife80010 16 receive fifo data register scf rdr2 r undefined h'ffe80014 h'ife80014 8 fifo control register scfcr2 r/w h'0000 h'ffe80018 h'ife80018 16 fifo data count register scfdr2 r h'0000 h'ffe8001c h'ife8001c 16 serial port register scsptr2 r/w h'0000 * 2 h'ffe80020 h'ife80020 16 line status register sclsr2 r/(w) * 3 h'0000 h'ffe80024 h'ife80024 16 notes: 1. only 0 can be written, to clear flags. bits 15 to 8, 3, and 2 are read-only, and cannot be modified. 2. the value of bits 6, 4, 2, and 0 is undefined. 3. only 0 can be written, to clear flags. bits 15 to 1 are read-only, and cannot be modified.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 675 of 1122 rej09b0370-0400 16.2 register descriptions 16.2.1 receive shift register (scrsr2) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? scrsr2 is the register used to receive serial data. the scif sets serial data input from the rxd2 pi n in scrsr2 in the orde r received, starting with the lsb (bit 0), and converts it to parallel data. wh en one byte of data has been received, it is transferred to the recei ve fifo register, scfrdr2, automatically. scrsr2 cannot be directly read or written to by the cpu. 16.2.2 receive fifo da ta register (scfrdr2) bit: 7 6 5 4 3 2 1 0 r/w: r r r r r r r r scfrdr2 is a 16-stage fifo register that stores received serial data. when the scif has received one byte of serial da ta, it transfers the receive d data from scrsr2 to scfrdr2 where it is stored, and completes the receive operation. scrsr2 is then enabled for reception, and consecutive receive operations can be performed until the receive fifo register is full (16 data bytes). scfrdr2 is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo register, an undefined value will be returned. when the r eceive fifo register is full of receive data, subsequent serial data is lost. the contents of scfrdr2 are undefined after a power-on reset or manual reset.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 676 of 1122 rej09b0370-0400 16.2.3 transmit shift register (sctsr2) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? sctsr2 is the register used to transmit serial data. to perform serial data transmission, the scif first transfers transmit data from scftdr2 to sctsr2, then sends the data to the txd2 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr2 to sctsr2, and transmission started, automatically. sctsr2 cannot be directly read or written to by the cpu. 16.2.4 transmit fifo data register (scftdr2) bit: 7 6 5 4 3 2 1 0 r/w: w w w w w w w w scftdr2 is a 16-stage fifo register that stores 8-bit data for serial transmission. if sctsr2 is empty when transmit data has been written to scftdr2, the scif transfers the transmit data written in scftdr2 to scts r2 and starts serial transmission. scftdr2 is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr2 is filled with 16 bytes of transmit data. data written in this case is ignored. the contents of scftdr2 are undefined after a power-on reset or manual reset.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 677 of 1122 rej09b0370-0400 16.2.5 serial mode register (scsmr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? chr pe o/ e stop ? cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r r/w r/w scsmr2 is a 16-bit register used to set the scif's serial transfer format and select the baud rate generator clock source. scsmr2 can be read or writte n to by the cpu at all times. scsmr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 7?reserved: these bits are always read as 0, and should only be written with 0. bit 6?character length (chr): selects 7 or 8 bits as the asynchronous mode data length. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (b it 7) of scftdr2 is not transmitted. bit 5?parity enable (pe): selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in recepti on, the parity bit is checked for the parity (even or odd) specified by the o/ e bit.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 678 of 1122 rej09b0370-0400 bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking. the o/ e bit setting is invalid when parity addition and checking is disabled. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit additi on is performed in transmission so that the total number of 1-bits in the transmit character pl us the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bi ts in the receive character plus the parity bit is odd. bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bi t) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the star t bit of the next transmit character. bit 2?reserved: this bit is always read as 0, and should only be written with 0.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 679 of 1122 rej09b0370-0400 bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from pck, pck/4, pck/16, and pck/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, bit rate register (scbrr2). bit 1: cks1 bit 0: cks0 description 0 0 pck clock (initial value) 1 pck/4 clock 1 0 pck/16 clock 1 pck/64 clock note: pck: peripheral clock 16.2.6 serial control register (scscr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 tie rie te re reie ? cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r r/w r/w the scscr2 register performs enabling or disabling of scif transfer operations, serial clock output, and interrupt requests, and selection of the serial clock source. scscr2 can be read or written to by the cpu at all times. scscr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 8, and 2?reserved: these bits are always read as 0, and should only be written with 0.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 680 of 1122 rej09b0370-0400 bit 7?transmit interrupt enable (tie): enables or disables transmit-fifo-data-empty interrupt (txi) request generation when serial transmit data is transf erred from scftdr2 to sctsr2, the number of data bytes in the transmit fifo register falls to or below the transmit trigger set number, and the tdfe flag in the se rial status register (scfsr2) is set to 1. bit 7: tie description 0 transmit-fifo-data-empty in terrupt (txi) request disabled * (initial value) 1 transmit-fifo-data-empty in terrupt (txi) request enabled note: * txi interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to scftdr2 after reading 1 from the tdfe flag, then clearing it to 0, or by clearing the tie bit to 0. bit 6?receive interrupt enable (rie): enables or disables genera tion of a receive-data-full interrupt (rxi) request when the rdf flag or dr flag in scfsr2 is set to 1, a receive-error interrupt (eri) request when the er flag in sc fsr2 is set to 1, and a break interrupt (bri) request when the brk flag in scfsr2 or the orer flag in sclsr2 is set to 1. bit 6: rie description 0 receive-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request enabled note: * an rxi interrupt request can be cleared by reading 1 from the rdf or dr flag, then clearing the flag to 0, or by clearing the ri e bit to 0. eri and bri interrupt requests can be cleared by reading 1 from the er, brk, or orer flag, then clearing the flag to 0, or by clearing the rie and reie bits to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the scif. bit 5: te description 0 transmission disabled (initial value) 1 transmission enabled * note: * serial transmission is started when transmit data is written to scftdr2 in this state. serial mode register (scsmr2) and fifo control register (scfcr2) settings must be made, the transmission format decided, and t he transmit fifo reset, before the te bit is set to 1.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 681 of 1122 rej09b0370-0400 bit 4?receive enable (re): enables or disables the start of serial reception by the scif. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not a ffect the dr, er, brk, rdf, fer, per, and orer flags, which retain their states. 2. serial transmission is started when a start bit is detected in this state. serial mode register (scsmr2) and fifo c ontrol register (scfcr2) settings must be made, the reception format decided, and the re ceive fifo reset, before the re bit is set to 1. bit 3?receive error interrupt enable (reie): enables or disables gene ration of receive-error interrupt (eri) and break interrupt (bri) requests. the reie bit setting is valid only when the rie bit is 0. bit 3: reie description 0 receive-error interrupt (eri) and break interrupt (bri) requests disabled * (initial value) 1 receive-error interrupt (eri) and br eak interrupt (bri) requests enabled note: * receive-error interrupt (eri) and break in terrupt (bri) requests can be cleared by reading 1 from the er, brk, or orer flag, t hen clearing the flag to 0, or by clearing the rie and reie bits to 0. when reie is set to 1, eri and bri interrupt requests will be generated even if rie is cleared to 0. in dmac transfer, this setting is made if the interrupt controller is to be notified of eri and bri interrupt requests. bits 1 and 0?clock enable 1 and 0 (cke1 and cke0): these bits select the scif clock source and enable/disable clock output from the sck2 pin. the combination of cke1 and cke0 determine whether the sck2 pin functions as serial clock output pin or the serial clock input pin. note, however, that the setting of the cke0 bit is valid only when cke1 = 0 (internal clock operation). when cke1 = 1 (external clock), cke0 is ignored. also, be sure to set cke1 and cke0 prior to determining the scif operating mode with scsmr2. bit 1: cke1 bit 0: cke0 description 0 0 internal clock/sck pin functions as port (initial value) 1 internal clock/sck2 pin functions as clock output * 1 1 0 external clock/sck2 pin functions as clock input * 2 1 external clock/sck2 pin functions as clock input * 2 notes: 1. outputs a clock with a frequency 16 times the bit rate. 2. inputs a clock with a frequency 16 times the bit rate.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 682 of 1122 rej09b0370-0400 16.2.7 serial status register (scfsr2) bit: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 er tend tdfe brk fer per rdf dr initial value: 0 1 1 0 0 0 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 can be written, to clear the flag. scfsr2 is a 16-bit register. the lower 8 bits cons ist of status flags that indicate the operating status of the scif, and the upper 8 bits indicate th e number of receive erro rs in the data in the receive fifo register. scfsr2 can be read or written to by the cpu at al l times. however, 1 cannot be written to flags er, tend, tdfe, brk, rdf, and dr. also note that in order to cl ear these flags they must be read as 1 beforehand. the fer flag and per fl ag are read-only flags and cannot be modified. scfsr2 is initialized to h'0060 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 12?number of parity errors (per3?per0): these bits indicate the number of data bytes in which a parity erro r occurred in the receive data stored in scfrdr2. after the er bit in scfsr2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. if all 16 bytes of receive data in scfrdr2 have pa rity errors, the value indicated by bits per3 to per0 will be 0. bits 11 to 8?number of framing errors (fer3?fer0): these bits indicate the number of data bytes in which a framing error occurred in the receive data stored in scfrdr2. after the er bit in scfsr2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. if all 16 bytes of receive data in scfrdr2 have framing errors, the value indicated by bits fer3 to fer0 will be 0.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 683 of 1122 rej09b0370-0400 bit 7?receive error (er): indicates that a framing error or parity error occurred during reception.* note: * the er flag is not affected and retains its previous state when the re bit in scscr2 is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr2, and reception continues. the fer and per bits in scfsr2 can be used to determine whether there is a receive error in the data read from scfrdr2. bit 7: er description 0 no framing error or parity error occurred during reception (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1 a framing error or parity error occurred during reception [setting conditions] ? when the scif checks whether the st op bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * ? when, in reception, the number of 1- bits in the receive data plus the parity bit does not match the parity se tting (even or odd) specified by the o/ e bit in scsmr2 note: * in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 684 of 1122 rej09b0370-0400 bit 6?transmit end (tend): indicates that there is no valid data in scftdr2 when the last bit of the transmit character is sent , and transmission has been ended. bit 6: tend description 0 transmission is in progress [clearing conditions] ? when transmit data is written to scftdr2, and 0 is written to tend after reading tend = 1 ? when data is written to scftdr2 by the dmac 1 transmission has been ended (initial value) [setting conditions] ? power-on reset or manual reset ? when the te bit in scscr2 is 0 ? when there is no transmit data in sc ftdr2 on transmission of the last bit of a 1-byte serial transmit character
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 685 of 1122 rej09b0370-0400 bit 5?transmit fifo data empty (tdfe): indicates that data ha s been transferred from scftdr2 to sctsr2, the number of data bytes in scftdr2 has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2), and new transmit data can be written to scftdr2. bit 5: tdfe description 0 a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr2 [clearing conditions] ? when transmit data exceeding the transmit trigger set number is written to scftdr2 after reading tdfe = 1, and 0 is written to tdfe ? when transmit data exceeding the transmit trigger set number is written to scftdr2 by the dmac 1 the number of transmit data bytes in scftdr2 does not exceed the transmit trigger set number (initial value) [setting conditions] ? power-on reset or manual reset ? when the number of scftdr2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * note: * as scftdr2 is a 16-byte fifo register , the maximum number of bytes that can be written when tdfe = 1 is 16 - (transmit trigger set number). data written in excess of this will be ignored. the number of data bytes in scftdr2 is indicated by the upper bits of scfdr2. bit 4?break detect (brk): indicates that a receive data break signal has been detected. bit 4: brk description 0 a break signal has not been received (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1 a break signal has been received * [setting condition] when data with a framing error is received, followed by the space ?0? level (low level ) for at least one frame length note: * when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr2. when the break ends and the rece ive signal returns to mark ?1?, receive data transfer is resumed.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 686 of 1122 rej09b0370-0400 bit 3?framing error (fer): indicates whether or not a framing error has been found in the data that is to be read from the r eceive fifo data re gister (scfrdr2). bit 3: fer description 0 there is no framing error in the re ceive data that is to be read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in the data that is to be read next from scfrdr2 1 there is a framing error in the re ceive data that is to be read from scfrdr2 [setting condition] when there is a framing error in t he data that is to be read next from scfrdr2 bit 2?parity error (per): indicates whether or not a parity error has been found in the data that is to be read from the receive fifo data register (scfrdr2). bit 2: per description 0 there is no parity error in the receiv e data that is to be read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in the data that is to be read next from scfrdr2 1 there is a parity error in the receive data that is to be read from scfrdr2 [setting condition] when there is a parity error in the data that is to be read next from scfrdr2
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 687 of 1122 rej09b0370-0400 bit 1?receive fifo data full (rdf): indicates that the received data has been transferred from scrsr2 to scfrdr2, and th e number of receive data byte s in scfrdr2 is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr2). bit 1: rdf description 0 the number of receive data bytes in scfrdr2 is less than the receive trigger set number (initial value) [clearing conditions] ? power-on reset or manual reset ? when scfrdr2 is read until the number of receive data bytes in scfrdr2 falls below the receive trigger set number after reading rdf = 1, and 0 is written to rdf ? when scfrdr2 is read by the dmac until the number of receive data bytes in scfrdr2 falls below the receive trigger set number 1 the number of receive data bytes in scfrdr2 is equal to or greater than the receive trigger set number [setting condition] when scfrdr2 contains at least the re ceive trigger set number of receive data bytes * note: * scfrdr2 is a 16-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if all the data in scfrdr2 is read and another read is performed, the data value will be undefin ed. the number of receive data bytes in scfrdr2 is indicated by the lower bits of scfdr2.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 688 of 1122 rej09b0370-0400 bit 0?receive data ready (dr): indicates that there are fewer than the receive trigger set number of data bytes in scfrdr2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. bit 0: dr description 0 reception is in progress or has ended normally and there is no receive data left in scfrdr2 (i nitial value) [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr2 has been read after reading dr = 1, and 0 is written to dr ? when all the receive data in scfrdr2 has been read by the dmac 1 no further receive data has arrived [setting condition] when scfrdr2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * note: * equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: elementary time unit (time for transfer of 1 bit) 16.2.8 bit rate register (scbrr2) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scbrr2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr2. scbrr2 can be read or written to by the cpu at all times. scbrr2 is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 689 of 1122 rej09b0370-0400 the scbrr2 setting is found from the following equation. asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b pck where b: bit rate (bits/s) n: scbrr2 setting for baud rate generator (0 n 255) pck: peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr2 setting n clock cks1 cks0 0 pck 0 0 1 pck/4 0 1 2 pck/16 1 0 3 pck/64 1 1 the bit rate error in asynchronous mode is found from the following equation: error ( % ) = ? 1 100 pck 10 6 (n + 1) b 64 2 2n ? 1 16.2.9 fifo control register (scfcr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? rstrg2 rstrg1 rstrg0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 690 of 1122 rej09b0370-0400 scfcr2 performs data count resetting and trigger data number setting for the transmit and receive fifo registers, and also contai ns a loopback test enable bit. scfcr2 can be read or written to by the cpu at all times. scfcr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 11?reserved: these bits are always read as 0, and should only be written with 0. bits 10, 9 and 8? rts2 output active trigger (rstrg2, rstg1, and rstg0): these bits output the high level to the rts2 signal when the numb er of received data stored in the receive fifo data register (scfrdr2) exceeds the trigger number, as shown in the table below. bit 10: rstrg2 bit 9: rstrg1 bit 8: rstrg0 rts2 output active trigger 0 0 0 15 (initial value) 1 1 1 0 4 1 6 1 0 0 8 1 10 1 0 12 1 14 bits 7 and 6?receive fifo data number trigger (rtrg1, rtrg0): these bits are used to set the number of receive data bytes that sets the receive data full (rdf) flag in the serial status register (scfsr2). the rdf flag is set when the number of receive data bytes in scfrdr2 is equal to or greater than the trigger set number shown in the following table. bit 7: rtrg1 bit 6: rtrg 0 receive trigger number 0 0 1 (initial value) 1 4 1 0 8 1 14
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 691 of 1122 rej09b0370-0400 bits 5 and 4?transmit fifo data number trigger (ttrg1, ttrg0): these bits are used to set the number of remaining transmit data bytes that sets the transmit fifo data register empty (tdfe) flag in the serial status register (scf sr2). the tdfe flag is set when the number of transmit data bytes in scftdr2 is equal to or less than the trigger set number shown in the following table. bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 0 0 8 (8) (initial value) 1 4 (12) 1 0 2 (14) 1 1 (15) note: figures in parentheses are the number of empty bytes in scftdr2 when the flag is set. bit 3?modem control enable (mce): enables the cts2 and rts2 modem control signals. bit 3: mce description 0 modem signals disabled * (initial value) 1 modem signals enabled note: * cts2 is fixed at active-0 regardless of the input value, and rts2 output is also fixed at 0. bit 2?transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 1?receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and resets it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 692 of 1122 rej09b0370-0400 bit 0?loopback test (loop): internally connects th e transmit output pin (txd2) and receive input pin (rxd2), and the rts2 pin and cts2 pin, enabling loopback testing. bit 0: loop description 0 loopback test disabled (initial value) 1 loopback test enabled 16.2.10 fifo data count register (scfdr2) scfdr2 is a 16-bit register that indicates the number of data bytes stored in scftdr2 and scfrdr2. the upper 8 bits show the number of transmit data bytes in scftdr2, and the lower 8 bits show the number of receive da ta bytes in scfrdr2. scfdr2 can be read by the cpu at all times. bit: 15 14 13 12 11 10 9 8 ? ? ? t4 t3 t2 t1 t0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r these bits show the number of untransmitted data bytes in scftdr2. a value of h'00 indicates that there is no transmit data, and a value of h'10 indicates that scftdr2 is full of transmit data. bit: 7 6 5 4 3 2 1 0 ? ? ? r4 r3 r2 r1 r0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r these bits show the number of receive data bytes in scfr dr2. a value of h'00 indicates that there is no receive data, and a value of h'10 indicates that sc frdr2 is full of receive data.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 693 of 1122 rej09b0370-0400 16.2.11 serial port register (scsptr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 rtsio rtsdt ctsio ctsd t sckio sckdt spb2io spb2dt initial value: 0 ? 0 ? 0 ? 0 ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w scsptr2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface with fifo (scif) pins. input data can be read from the rxd2 pin, output data written to the txd2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. data can be read from, and output data written to, the sck2 pin by means of bits 3 and 2. data can be read from, and output data written to, the cts2 pin by means of bits 5 and 4. data can be read from, and output data written to, the rts2 pin by means of bits 6 and 7. scsptr2 can be read or written to by the cpu at all times. all scsptr2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manu al reset; the value of bits 6, 4, 2, and 0 is undefined. scsptr2 is not initialized in standby mode or in the module standby state. bits 15 to 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?serial port rts port i/o (rtsio): specifies the serial port rts2 pin input/output condition. when the rts2 pin is actually set as a port output pin and outputs the value set by the rtsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 7: rtsio description 0 rtsdt bit value is not output to rts2 pin (initial value) 1 rtsdt bit value is output to rts2 pin
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 694 of 1122 rej09b0370-0400 bit 6?serial port rts port data (rtsdt): specifies the serial port rts2 pin input/output data. input or output is specified by the rtsio bit (see the description of bit 7, rtsio, for details). in output mode, the rtsdt bit value is output to the rts2 pin. the rts2 pin value is read from the rtsdt bit regardless of the value of the rtsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 6: rtsdt description 0 input/output data is low-level 1 input/output data is high-level bit 5?serial port cts port i/o (ctsio): specifies the serial port cts2 pin input/output condition. when the cts2 pin is actually set as a port output pin and outputs the value set by the ctsdt bit, the mce bit in scf cr2 should be cleared to 0. bit 5: ctsio description 0 ctsdt bit value is not output to cts2 pin (initial value) 1 ctsdt bit value is output to cts2 pin bit 4?serial port cts port data (ctsdt): specifies the serial port cts2 pin input/output data. input or output is specified by the ctsio bit (see the description of bit 5, ctsio, for details). in output mode, the ctsdt bit value is output to the cts2 pin. the cts2 pin value is read from the ctsdt bit regardless of the value of the ctsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 4: ctsdt description 0 input/output data is low-level 1 input/output data is high-level bit 3?serial port cloc k port i/o (sckio): sets the i/o for the sck2 pin serial port. to actually set the sck2 pin as the port output pin and output the value set in the sckdt bit, set the cke1 and cke0 bits of th e scscr2 register to 0. bit 3: sckio description 0 shows that the value of the sckdt bit is not output to the sck2 pin (initial value) 1 shows that the value of the sckd t bit is output to the sck2 pin.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 695 of 1122 rej09b0370-0400 bit 2?serial port cloc k port data (sckdt): specifies the i/o data fo r the sck2 pin serial port. the sckio bit specified input or output. (see bit 3: sckio, for details.) when set for output, the value of the sckdt bit is output to the sck2 pin. regardless of the value of the sckio bit, the value of the sck2 pin is fetche d from the sckdt bit. the initial value after a power-on reset or manual reset is undefined. bit 2: sckdt description 0 shows i/o data level is low 1 shows i/o data level is high bit 1?serial port break i/o (spb2io): specifies the serial port txd2 pin output condition. when the txd2 pin is actually set as a port output pin and outputs the value set by the spb2dt bit, the te bit in scscr2 should be cleared to 0. bit 1: spb2io description 0 spb2dt bit value is not output to the txd2 pin (initial value) 1 spb2dt bit value is output to the txd2 pin bit 0?serial port break data (spb2dt): specifies the serial port rxd2 pin input data and txd2 pin output data. the txd2 pin output condition is specified by the spb2io bit (see the description of bit 1, spb2io, for details). when the txd2 pin is designated as an output, the value of the spb2dt bit is output to the txd2 pin. the rxd2 pin value is read from the spb2dt bit regardless of the value of the spb2io bit. the init ial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb2dt description 0 input/output data is low-level 1 input/output data is high-level
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 696 of 1122 rej09b0370-0400 scif i/o port block diagrams are shown in figures 16.2 to 16.6. reset internal data bus sptrw d7 d6 scif r q d rtsio c reset mode settin g re g ister sptrr sptrw r q d rtsdt c md8/ rts2 le g end: sptrw: write to sptr sptrr: read sptr note: * the rts2 pin function is desi g nated as modem control by the mce bit in scfcr2. modem control enable si g nal * rts2 si g nal figure 16.2 md8/ rts2 pin
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 697 of 1122 rej09b0370-0400 reset internal data bus sptrw d5 d4 scif r q d ctsio c reset sptrr mode settin g re g ister sptrw r q d ctsdt c md7/ cts2 le g end: sptrw: write to sptr sptrr: read sptr note: * the cts2 pin function is desi g nated as modem control by the mce bit in scfcr2. modem control enable si g nal * cts2 si g nal figure 16.3 md7/ cts2 pin
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 698 of 1122 rej09b0370-0400 reset internal data bus sptrw mode settin g re g ister scif r q d d1 d0 spb2io c reset sptrw r q d spb2dt c md1/txd2 le g end: sptrw: write to sptr transmit enable si g nal serial transmit data figure 16.4 md1/txd2 pin internal data bus mode settin g re g ister scif md2/rxd2 sptrr d0 serial receive data le g end: sptrr: read sptr figure 16.5 md2/rxd2 pin
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 699 of 1122 rej09b0370-0400 reset reset internal data bus sptrw sptrw scif r q d sckio c r q d sckdt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * md0/sck2 mode settin g re g ister le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck2 pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr2. figure 16.6 md0/sck2 pin
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 700 of 1122 rej09b0370-0400 16.2.12 line status register (sclsr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? orer initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r (r/w) * note: * only 0 can be written, to clear the flag. bits 15 to 1?reserved: these bits are always read as 0, and should only be written with 0. bit 0?overrun error (orer): indicates that an overrun er ror occurred during reception, causing abnormal termination. bit 0: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when the next serial reception is completed while the receive fifo is full notes: 1. the orer flag is not affected and re tains its previous state when the re bit in scscr2 is cleared to 0. 2. the receive data prior to the overr un error is retained in scfrdr2, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 701 of 1122 rej09b0370-0400 16.3 operation 16.3.1 overview the scif can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. see section 15.3 .2, operation in asynchronous mode, for details. sixteen-stage fifo buffers are provided for both transmission an d reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. rts2 and cts2 signals are also provided as modem control signals. the transmission format is selected using the se rial mode register (scsmr2), as shown in table 16.3. the scif clock source is determined by the cke1 bit in the serial control register (scscr2), as shown in table 16.4. ? data length: choice of 7 or 8 bits ? choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer fo rmat and character length) ? detection of framing errors, parity errors, rece ive-fifo-data- full state, overrun errors, receive- data-ready state, and breaks, during reception ? indication of the number of data bytes stored in the transmit and receive fifo registers ? choice of internal or external clock as scif clock source when internal clock is selected: the scif oper ates on the baud rate generator clock, and a clock with a frequency of 16 times the bit rate must be output when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 702 of 1122 rej09b0370-0400 table 16.3 scsmr2 settings for serial transfer format selection scsmr2 settings scif transfer format bit 6: chr bit 5: pe bit 3: stop mode data length multiprocessor bit parity bit stop bit length 0 1 bit 0 1 no 2 bits 0 1 bit 0 1 1 8-bit data yes 2 bits 0 1 bit 0 1 no 2 bits 0 1 bit 1 1 1 asynchronous mode 7-bit data no yes 2 bits table 16.4 scscr2 settings fo r scif clock source selection scscr2 setting scif transmit/receive clock bit 1: cke1 bit 0: cke0 mode clock source sck2 pin function 0 scif does not use sck2 pin 0 1 internal output clock with frequency of 16 times the bit rate 0 1 1 asynchronous mode external inputs clock with frequency of 16 times the bit rate
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 703 of 1122 rej09b0370-0400 16.3.2 serial operation data transfer format table 16.5 shows the data transfer formats that can be used. any of 8 tr ansfer formats can be selected according to the scsmr2 settings. table 16.5 serial transfer formats scsmr2 settings serial transfer format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 s 8-bit data stop 0 0 1 s 8-bit data stop stop 0 1 0 s 8-bit data p stop 0 1 1 s 8-bit data p stop stop 1 0 0 s 7-bit data stop 1 0 1 s 7-bit data stop stop 1 1 0 s 7-bit data p stop 1 1 1 s 7-bit data p stop stop legend: s: start bit stop: stop bit p: parity bit
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 704 of 1122 rej09b0370-0400 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck2 pin can be selected as th e scif's serial clock, according to the setting of the cke1 bit in scscr2. for details of scif clock source selection, see table 16.4. when an external clock is input at the sck2 pin, the clock frequency should be 16 times the bit rate used. when operating using the internal clock, the clock can be output via the sck2 pin. the frequency of this clock is 16 times the bit rate. data transfer operations scif initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr2 to 0, then initialize the scif as described below. when the transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, sctsr2 is initialized. note that clearing the te and re bits to 0 does not change the contents of scfsr2, scftdr2, or scfrdr2. the te bit should be cleared to 0 after all transmit data has been sent and the tend flag in scfsr2 has been set. tend can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state afte r the clearance. before setting te again to start transmission, the tfrst bit in scfcr2 should first be set to 1 to reset scftdr2. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 16.7 shows a sample scif initialization flowchart.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 705 of 1122 rej09b0370-0400 initialization clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) set data transfer format in scsmr2 set value in scbrr2 1-bit interval elapsed? set rtrg1?0, ttrg1?0, and mce bits in scfcr2 clear tfrst and rfrst bits to 0 set te and re bits in scscr2 to 1, and set rie, tie, and reie bits end wait no yes 1. set the clock selection in scscr2. be sure to clear bits rie and tie, and bits te and re, to 0. 2. set the data transfer format in scsmr2. 3. write a value corresponding to the bit rate into scbrr2. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr2 to 1. also set the rie, reie, and tie bits. setting the te and re bits enables the txd2 and rxd2 pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. figure 16.7 sample scif initialization flowchart
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 706 of 1122 rej09b0370-0400 serial data transmission: figure 16.8 shows a sample flow chart for serial transmission. use the following procedure for serial data transm ission after enabling the scif for transmission. start of transmission read tdfe fla g in scfsr2 tdfe = 1 ? write transmit data (16 ? transmit tri gg er set number) to scftdr2, read 1 from tdfe fla g and tend fla g in scfsr2, then clear to 0 all data transmitted ? read tend fla g in scfsr2 tend = 1 ? break output ? clear spb2dt to 0 and set spb2io to 1 clear te bit in scscr2 to 0 end of transmission no yes no yes no yes no yes 1. scif status check and transmit data write: read scfsr2 and check that the tdfe fla g is set to 1, then write transmit data to scftdr2, read 1 from the tdfe and tend fla g s, then clear these fla g s to 0. the number of transmit data bytes that can be written is 16 ? (transmit tri gg er set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe fla g to confirm that writin g is possible, then write data to scftdr2, and then clear the tdfe fla g to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, clear the spb2dt bit to 0 and set the spb2io bit to 1 in scsptr2, then clear the te bit in scscr2 to 0. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr2 indicated by the upper 8 bits of scfdr2. figure 16.8 sample serial transmission flowchart
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 707 of 1122 rej09b0370-0400 in serial transmission, the scif operates as described below. 1. when data is written into scftdr2, the sc if transfers the data fr om scftdr2 to sctsr2 and starts transmitting. confirm that the tdfe flag in the serial status register (scfsr2) is set to 1 before writing transmit data to scftdr2. the number of data bytes that can be written is at least 16 ? (transmit trigger set number). 2. when data is transferred from scftdr2 to sctsr2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr2. when the number of transmit data bytes in scftdr2 falls to or below the transmit trigger number set in the fifo control register (scfcr2), the tdfe flag is set. if the tie bit in scscr2 is set to 1 at this time, a transmit-fi fo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd2 pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr2 transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr2 to sctsr2, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scfsr2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. figure 16.9 shows an example of the operation for transmission in asynchronous mode.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 708 of 1122 rej09b0370-0400 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to scftdr2 and tdfe fla g read as 1 then cleared to 0 by txi interrupt handler one frame txi interrupt request figure 16.9 example of transmit operation (example with 8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and rest arted in accordance with the cts2 input value. when cts2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. when cts2 is set to 0, the next transmit data is output starting from the start bit. figure 16.10 shows an example of the operation when modem control is used. serial data txd2 0 d0 d1 d7 0/1 0 1 d0 d1 d7 0/1 cts2 drive hi g h before stop bit start bit parity bit stop bit start bit figure 16.10 example of op eration using modem control ( cts2 )
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 709 of 1122 rej09b0370-0400 serial data reception: figure 16.11 shows a sample fl owchart for serial reception. use the following procedure for serial data r eception after enabling th e scif for reception. start of reception read er, dr, brk fla g s in scfsr2 and orer fla g in sclsr2 er or dr or brk or orer = 1 ? read rdf fla g in scfsr2 rdf = 1 ? read receive data in scfrdr2, and clear rdf fla g in scfsr2 to 0 all data received ? clear re bit in scscr2 to 0 end of reception yes no yes yes no no error handlin g 1. receive error handlin g and break detection: read the dr, er, and brk fla g s in scfsr2, and the orer fla g in sclsr2, to identify any error, perform the appropriate error handlin g , then clear the dr, er, brk, and orer fla g s to 0. in the case of a framin g error, a break can also be detected by readin g the value of the rxd2 pin. 2. scif status check and receive data read : read scfsr2 and check that rdf = 1, then read the receive data in scfrdr2, read 1 from the rdf fla g , and then clear the rdf fla g to 0. the transition of the rdf fla g from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive tri gg er set number of receive data bytes from scfrdr2, read 1 from the rdf fla g , then clear the rdf fla g to 0. the number of receive data bytes in scfrdr2 can be ascertained by readin g the lower bits of scfdr2. figure 16.11 sample serial reception flowchart (1)
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 710 of 1122 rej09b0370-0400 error handlin g receive error handlin g er = 1 ? brk = 1 ? break handlin g dr = 1 ? read receive data in scfrdr2 clear dr, er, brk fla g s in scfsr2, and orer fla g in sclsr2, to 0 end yes yes yes no overrun error handlin g orer = 1 ? yes no no no 1. whether a framin g error or parity error has occurred in the receive data read from scfrdr2 can be ascertained from the fer and per bits in scfsr2. 2. when a break si g nal is received, receive data is not transferred to scfrdr2 while the brk fla g is set. however, note that the last data in scfrdr2 is h'00 (the break data in which a framin g error occurred is stored). figure 16.11 sample serial reception flowchart (2)
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 711 of 1122 rej09b0370-0400 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr2 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the st op bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr2) to scfrdr2. c. overrun error check: the scif checks that th e orer flag is 0, indi cating that no overrun error has occurred. d. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. if all the b, c, and d checks are passed, the receive data is stored in scfrdr2. note: reception continues when par ity error, framing error occurs. 4. if the rie bit in scscr2 is set to 1 when the rdf or dr fl ag changes to 1, a receive-fifo- data-full interrupt (rxi) request is generated. if the rie bit or reie bit in scscr2 is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit or reie bit in scscr2 is set to 1 when the brk or orer flag changes to 1, a break reception interrupt (br i) request is generated.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 712 of 1122 rej09b0370-0400 figure 16.12 shows an example of the operation for reception. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdf fer serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame data read and rdf fla g read as 1 then cleared to 0 by rxi interrupt handler eri interrupt request g enerated by receive error figure 16.12 example of scif receive operation (example with 8-bit data, parity, one stop bit) 5. when modem control is enabled, the rts2 signal is output when scfrdr2 is empty. when rts2 is 0, reception is possible. when rts2 is 1, this indicates that scfrdr2 contains a number of data bytes equal to or greater than the rts2 output active trigger set number. the rts2 output active trigger value is specified by bits 10 to 8 in the fifo control register (scfcr2), described in section 16.2.9, fifo control register (scfcr2). rts2 also goes to 1 when bit 4 (re) in scscr2 is 0. figure 16.13 shows an example of the operation when modem control is used. d0 d1 d2 d7 0/1 1 0 0 rts2 serial data rxd2 start bit parity bit stop bit start bit figure 16.13 example of operati on using modem control (rts2)
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 713 of 1122 rej09b0370-0400 16.4 scif interrupt sources and the dmac the scif has four interrupt sour ces: transmit-fifo-data-empty in terrupt (txi) request, receive- error interrupt (eri) requ est, receive-fifo-data-full interrupt (rxi) request, and break interrupt (bri) request. table 16.6 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie, rie, and reie bits in scscr2. a separate interrupt request is sent to the interrupt contro ller for each of these interrupt sources. when transmission/reception is carried out using the dmac, output of interrupt requests to the interrupt controller can be inhibited by clearing the rie bit in scscr2 to 0. by setting the reie bit to 1 while the rie bit is cleared to 0, it is possible to output eri and bri interrupt requests, but not rxi interrupt requests. when the tdfe flag in the serial status register (scfsr2) is set to 1, a transmit-fifo-data-empty request is generated separately from the interrupt request. a transmit-fifo-data-empty request can activate the dmac to perform data transfer. when the rdf flag or dr flag in scfsr2 is set to 1, a receive-fifo -data-full request is generated separately from the interrupt request. a receive-fifo-data-full request can activate the dmac to perform data transfer. when using the dmac for transmission/reception, set and enable the dmac before making the scif settings. see section 14, direct memory access controller (dmac), for details of the dmac setting procedure. when the brk flag in scfsr2 or the orer flag in the line status register (sclsr2) is set to 1, a bri interrupt request is generated. the txi interrupt indicates that transmit data can be written, and the rxi interrupt indicates that there is receive data in scfrdr2.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 714 of 1122 rej09b0370-0400 table 16.6 scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) not possible high rxi interrupt initiated by receive fifo data full flag (rdf) or receive data ready flag (dr) possible bri interrupt initiated by break flag (brk) or overrun error flag (orer) not possible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low see section 5, exceptions, for priorities and the relationship with non-scif interrupts. 16.5 usage notes note the following when using the scif. scftdr2 writing and the tdfe flag: the tdfe flag in the serial status register (scfsr2) is set when the number of transmit data bytes writte n in the transmit fifo data register (scftdr2) has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2). after tdfe is set, transmit data up to the number of empty bytes in scftdr2 can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr2 is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 agai n after being read as 1 and cleared to 0. tdfe clearing should therefore be carri ed out when scftdr2 contains mo re than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr2 can be found from the upper 8 bits of the fifo data count register (scfdr2). scfrdr2 reading and the rdf flag: the rdf flag in the serial status register (scfsr2) is set when the number of receive data bytes in the receive fifo data register (scfrdr2) has become equal to or greater than the receive tri gger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr2). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr2, allowi ng efficient continuous reception. however, if the number of data bytes in scfrdr2 is equal to or greater than the trigger number, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefor e be cleared to 0 after being read as 1 after all the receive data has been read.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 715 of 1122 rej09b0370-0400 the number of receive data bytes in scfrdr2 ca n be found from the lower 8 bits of the fifo data count register (scfdr2). break detection and processing: break signals can be detected by reading the rxd2 pin directly when a framing error (fer) is detected. in the brea k state the input from the rxd2 pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. although the scif stops tr ansferring receive data to scfrdr2 after receiving a break, the receive operation continues. sending a break signal: the input/output condition and level of the txd2 pin are determined by bits spb2io and spb2dt in the serial port register (scsptr2). this feature can be used to send a break signal. after the serial transmitter is initialized, the txd2 pin function is not selected and the value of the spb2dt bit substitutes for the mark state until the te bit is set to 1 (i.e. transmission is enabled). the spb2io and spb2dt bits should therefore be set to 1 (designating output and high level) beforehand. to send a break signal during serial transmissi on, clear the spb2dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized, regardless of its curren t state, and 0 is output from the txd2 pin. receive data sampling timi ng and receive margin: the scif operates on a base clock with a frequency of 16 times the bit rate. in reception, th e scif synchronizes internally with the fall of the start bit, which it samp les on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 16.14.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 716 of 1122 rej09b0370-0400 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (rxd2) start bit ?7.5 clocks +7.5 clocks synchronization samplin g timin g data samplin g timin g figure 16.14 receive data sampling timing in asynchronous mode the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n ...................... (1) legend: m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1 / (2 16) ) 100 % = 46.875 % ............................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % .
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 717 of 1122 rej09b0370-0400 when using the dmac: when using the dmac for transmission/reception, inhibit output of rxi and txi interrupt requests to the interrupt cont roller. if interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the dmac without regard to the interrupt handler. serial ports: note that, when the scif pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier.
16. serial communication interface with fifo (scif) rev.4.00 oct. 10, 2008 page 718 of 1122 rej09b0370-0400
17. smart card interface rev.4.00 oct. 10, 2008 page 719 of 1122 rej09b0370-0400 section 17 smart card interface 17.1 overview the serial communication interface (sci) supports a subset of the iso/iec 7816-3 (identification cards) standard as an extended function. switching between the normal serial communication interface an d the smart card interface is carried out by means of a register setting. 17.1.1 features features of the smart card interface are listed below. ? asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (p arity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? on-chip baud rate generator allows any bit rate to be selected ? three interrupt sources there are three interrupt source s?transmit-data-empty, receive-da ta-full, and transmit/receive error?that can issue requests independently. the transmit-data-empty inte rrupt and receive-dat a-full interrupt can activate the dma controller (dmac) to execute data transfer.
17. smart card interface rev.4.00 oct. 10, 2008 page 720 of 1122 rej09b0370-0400 17.1.2 block diagram figure 17.1 shows a block diag ram of the smart card interface. module data bus scrdr1 scrsr1 rxd txd sck sctdr1 sctsr1 scscmr1 scssr1 scscr1 scbrr1 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 txi rxi eri sci bus interface internal data bus scsmr1 legend: scscmr1: smart card mode register scrsr1: receive shift register scrdr1: receive data register sctsr1: transmit shift register sctdr1: transmit data register scsmr1: serial mode register scscr1: serial control register scssr1: serial status register scbrr1: bit rate register scsptr1: serial port register scsptr1 figure 17.1 block diagram of smart card interface
17. smart card interface rev.4.00 oct. 10, 2008 page 721 of 1122 rej09b0370-0400 17.1.3 pin configuration table 17.1 shows the smart card interface pin configuration. table 17.1 smart card interface pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin txd out put transmit data output 17.1.4 register configuration the smart card interface has the internal regist ers shown in table 17.2. details of the scbrr1, sctdr1, scrdr1, and scsptr1 registers are the sa me as for the normal sci function: see the register descriptions in section 15, serial communication interface (sci). with the exception of the serial port register, the smart card inte rface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. when recovering from standby mode or the module standby state, the registers must be set again. table 17.2 smart card interface registers name abbreviation r/w initial value p4 address area 7 address access size serial mode register scsmr1 r/w h'00 h'ffe00000 h'1fe00000 8 bit rate register scbrr1 r/w h'ff h'ffe00004 h'1fe00004 8 serial control register scs cr1 r/w h'00 h'ffe00008 h'1fe00008 8 transmit data register sctdr1 r/w h'ff h'ffe0000c h'1fe0000c 8 serial status register scssr1 r/(w) * 1 h'84 h'ffe00010 h'1fe00010 8 receive data register scrdr 1 r h'00 h'ffe00014 h'1fe00014 8 smart card mode register scscmr1 r/w h'00 h'ffe00018 h'1fe00018 8 serial port register scsptr1 r/w h'00 * 2 h'ffe0001c h'1fe0001c 8 notes: 1. only 0 can be written, to clear flags. 2. the value of bits 2 and 0 is undefined.
17. smart card interface rev.4.00 oct. 10, 2008 page 722 of 1122 rej09b0370-0400 17.2 register descriptions only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 smart card mode register (scscmr1) scscmr1 is an 8-bit readable/writable register that selects the smart card interface function. scscmr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit: 7 6 5 4 3 2 1 0 ? ? ? ? sdir sinv ? smif initial value: ? ? ? ? 0 0 ? 0 r/w: ? ? ? ? r/w r/w ? r/w bits 7 to 4 and 1?reserved: these bits are always read as 0, and should only be written with 0. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3: sdir description 0 sctdr1 contents are transmitted lsb-first (initial value) receive data is stored in scrdr1 lsb-first 1 sctdr1 contents are transmitted msb-first receive data is stored in scrdr1 msb-first bit 2?smart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the bit 3 function for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 17.3.4, register settings. bit 2: sinv description 0 sctdr1 contents are transmitted as they are (initial value) receive data is stored in scrdr1 as it is 1 sctdr1 contents are inve rted before being transmitted receive data is stored in scrdr1 in inverted form
17. smart card interface rev.4.00 oct. 10, 2008 page 723 of 1122 rej09b0370-0400 bit 0?smart card interface mode select (smif): enables or disables the smart card interface function. bit 0: smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled 17.2.2 serial mode register (scsmr1) bit 7 of scsmr1 has a different func tion in smart card interface mode. bit: 7 6 5 4 3 2 1 0 gm(c/ a ) chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?gsm mode (gm): sets the smart card interface function to gsm mode. with the normal smart card interf ace, this bit is cleared to 0. setting this bit to 1 selects gsm mode, an additional mode for controlling the timing for setting the tend flag that indicates completion of transmission, and the type of clock output used. the details of the additional clock output control mode are specified by the cke1 and cke0 bits in the serial control register (scscr1). in gsm mode, the pulse width is guar anteed when sck start/stop specifications are made by cke1 and cke0. bit 7: gm description 0 normal smart card interface mode operation (initial value) ? the tend flag is set 12.5 etu afte r the beginning of the start bit ? clock output on/off control only 1 gsm mode smart card interface mode operation ? the tend flag is set 11.0 etu afte r the beginning of the start bit ? clock output on/off and fixed-high/fixed-low control (set in scscr1) note: etu: elementary time unit (time for transfer of 1 bit) bits 6 to 0: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. with the smart card interface, the fo llowing settings should be used: chr = 0, pe = 1, stop = 1, mp = 0.
17. smart card interface rev.4.00 oct. 10, 2008 page 724 of 1122 rej09b0370-0400 17.2.3 serial control register (scscr1) bits 1 and 0 of scscr1 have a differ ent function in smart card interface mode. bit: 7 6 5 4 3 2 1 0 tie rie te re ? ? cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7 to 4: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. bits 3 and 2?reserved: not used with the smart card interface. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits specify th e function of the sck pin. in smart card interface mode, an internal cloc k is always used as th e clock source. in smart card interface mode, it is possible to specify a fixed high le vel or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. gm cke1 cke0 sck pin function 0 0 0 port i/o pin 1 clock output as sck output pin 1 0 invalid setting: must not be used 1 invalid setting: must not be used 1 0 0 output pin with output fixed low 1 clock output as output pin 1 0 output pin with output fixed high 1 clock output as output pin
17. smart card interface rev.4.00 oct. 10, 2008 page 725 of 1122 rej09b0370-0400 17.2.4 serial status register (scssr1) bit 4 of scssr1 has a differen t function in smart card interf ace mode. coupled with this, the setting conditions for bit 2 (tend) are also different. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer/ ers per tend ? ? initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear the flag. bits 7 to 5: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. bit 4?error signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission . framing errors are not detected in smart card interface mode. bit 4: ers description 0 normal reception, no error signal (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to ers after reading ers = 1 1 an error signal has been sent from the receiving side indicating detection of a parity error [setting condition] when the low level of the error signal is detected note: clearing the te bit in scscr1 to 0 does not affect the ers flag, which retains its previous state. bit 3?parity error (per): operates in the same way as fo r the normal sci. see section 15, serial communication interface (sci), for details.
17. smart card interface rev.4.00 oct. 10, 2008 page 726 of 1122 rej09b0370-0400 bit 2?transmit end (tend): the setting conditions for the tend flag are as follows. bit 2: tend description 0 transmission in progress [clearing condition] when 0 is written to tdre after reading tdre = 1 1 transmission has been ended (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 and the fer/ers bit is also 0 ? when the gm bit in scsmr1 is 0, and tdre = 1 and fer/ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character ? when the gm bit in scsmr1 is 1, and tdre = 1 and fer/ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character note: etu: elementary time unit (time for transfer of 1 bit) bits 1 and 0?reserved: not used with the sm art card interface. 17.3 operation 17.3.1 overview the main functions of the smar t card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (e lementary time unit: the time for transfer of one bit) is left between the end of the pari ty bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. ? if an error signal is detected during transmissi on, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no synchronous communication function.
17. smart card interface rev.4.00 oct. 10, 2008 page 727 of 1122 rej09b0370-0400 17.3.2 pin connections figure 17.2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected outside the chip. the data transmission line should be pulled up on the v cc power supply side with a resistor. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card us es an internal clock. chip port output is used as the reset signal. other pins must normally be connected to the power supply or ground. note: if an ic card is not connected, and both te and re are set to 1, closed transmission/reception is possi ble, enabling self-diagnosis to be carried out. sh7751/ sh7751r txd rxd sck px (port) data line clock line reset line io clk rst ic card v cc figure 17.2 schematic diagram of smart card interface pin connections
17. smart card interface rev.4.00 oct. 10, 2008 page 728 of 1122 rej09b0370-0400 17.3.3 data format figure 17.3 shows the smart card in terface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. if an error signal is detected during transmission, the same data is retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp de le g end: ds: start bit d0?d7: data bits dp: parity bit de: error si g nal when there is no parity error when a parity error occurs transmittin g station output transmittin g station output receivin g station output figure 17.3 smart card interface data format the operation sequence is as follows. 1. when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. 2. the transmitting station starts transmission of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). 3. with the smart card interface, the data line then returns to th e high-impedance state. the data line is pulled high with a pull-up resistor. 4. the receiving station car ries out a parity check. if there is no parity error and the data is r eceived normally, the receiving station waits for reception of the next data.
17. smart card interface rev.4.00 oct. 10, 2008 page 729 of 1122 rej09b0370-0400 if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signal line in the hi gh-impedance state again. the signal line is pulled high again by a pull-up resistor. 5. if the transmitting station does not receive an erro r signal, it proceeds to transmit the next data frame. if it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 register settings table 17.3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 17.3 smart card interface register settings bit register bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 scsmr1 gm 0 1 o/ e 1 0 cks1 cks0 scbrr1 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scscr1 tie rie te re 0 0 cke1 cke0 sctdr1 tdr7 tdr6 tdr5 t dr4 tdr3 tdr2 tdr1 tdr0 scssr1 tdre rdrf orer fer/ers per tend 0 0 scrdr1 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scscmr1 ? ? ? ? sdir sinv ? smif scsptr1 eio ? ? ? spb1io spb1dt spb0io spb0dt note: a dash indicates an unused bit. serial mode register (scsmr1) settings: the gm bit is used to select the timing of tend flag setting, and, together with the cke1 and cke0 bits in the serial control register (scscr1), to select the clock output state. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. see section 17.3.5, clock.
17. smart card interface rev.4.00 oct. 10, 2008 page 730 of 1122 rej09b0370-0400 i/o data note: etu: elementary time unit (time for transfer of 1 bit) txi (tend interrupt) guard time ds da db dc dd de df d g dh dp de 12.5 etu 11.0 etu gm = 0 gm = 1 figure 17.4 tend generation timing bit rate register (scbrr1) setting: scbrr1 is used to set the bit rate. see section 17.3.5, clock, for the method of calculating the value to be set. serial control regist er (scscr1) settings: the function of the tie, ri e, te, and re bits is the same as for the normal sci. see section 15, serial communication interface (sci), for details. the cke1 and cke0 bits specify the clock output state. see section 17.3.5, clock, for details. smart card mode register (scscmr1) settings: the sdir bit and sinv bit are both cleared to 0 if the ic card is of the direct convention t ype, and both set to 1 if of the inverse convention type. the smif bit is set to 1 when the smart card interface is used. figure 17.5 shows examples of register settings an d the waveform of the start character for the two types of ic card (direct convention and inverse convention). with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first orde r. the start character data in this case is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first orde r. the start character data in this case is h'3f. the parity bit is 0, corresponding to state z, sin ce even parity is stipul ated for the smart card.
17. smart card interface rev.4.00 oct. 10, 2008 page 731 of 1122 rej09b0370-0400 inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in scsmr1 is set to odd parity mode. (this applies to both transmission and reception). (z) (a) direct convention (sdir = sinv = o/ e = 0) (b) inverse convention (sdir = sinv = o/ e = 1) a z z a z z z a a z (z) state ds d0 d1 d2 d3 d4 d5 d6 d7 dp (z) a z z a a a a a a z (z) state ds d7 d6 d5 d4 d3 d2 d1 d0 dp figure 17.5 sample start character waveforms 17.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for th e smart card interface. the bit rate is set with the bit rate register (scbrr1) and the cks1 and cks0 bits in the serial mode register (scsmr1). the equation for calculating the bit rate is shown below. table 17.5 shows some sample bit rates. if clock output is selected with cke0 set to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = 10 6 1488 2 2n ? 1 (n + 1) pck where: n = value set in scbrr1 (0 n 255) b = bit rate (bits/s) pck = peripheral module operating frequency (mhz) n = 0 to 3 (see table 17.4)
17. smart card interface rev.4.00 oct. 10, 2008 page 732 of 1122 rej09b0370-0400 table 17.4 values of n and corres ponding cks1 and cks0 settings n cks1 cks0 0 0 0 1 0 1 2 1 0 3 1 1 table 17.5 examples of bit rate b (bits/s) for various scbrr1 settings (when n = 0) pck (mhz) n 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 0 9600.0 13440.9 14400.0 192 00.0 33602.2 44354.8 67204.3 1 4800.0 6720.4 7200.0 960 0.0 16801.1 22177.4 33602.2 2 3200.0 4480.3 4800.0 640 0.0 11200.7 14784.9 22401.4 note: bit rates are rounded to one decimal place. the method of calculating the value to be set in the bit rate register (scbrr1) from the peripheral module operating frequency and bit rate is shown below. here, n is an integer in the range 0 n 255, and the smaller error is specified. n = 10 6 ? 1 1488 2 2n ? 1 b pck table 17.6 examples of scbrr1 settings for bit rate b (bits/s) (when n = 0) pck (mhz) 7.1424 10.00 10.7136 14.2848 25.00 33.00 50.00 bits/s n error n error n error n error n error n error n error 9600 0 0.00 1 30.00 1 25.00 1 8.99 3 14.27 4 8.22 6 0.01
17. smart card interface rev.4.00 oct. 10, 2008 page 733 of 1122 rej09b0370-0400 table 17.7 maximum bit rate at various frequencies (smart card interface mode) pck (mhz) maximum bit rate (bits/s) n n 7.1424 19200 0 0 10.00 26882 0 0 10.7136 28800 0 0 16.00 43010 0 0 20.00 53763 0 0 25.0 67204 0 0 30.0 80645 0 0 33.0 88710 0 0 50.0 67204 0 0 the bit rate error is given by the following equation: error ( % ) = 1488 2 2n ? 1 b (n + 1) 10 6 ? 1 100 pck table 17.8 shows the relationship between the smar t card interface transmit/receive clock register settings and the output state. table 17.8 register setti ngs and sck pin state register values sck pin setting smif gm cke1 cke0 output state 1 * 1 1 0 0 0 port determined by setting of spb1io and spb1dt bits in scsptr1 1 0 0 1 sck (serial clock) output state 2 * 2 1 1 0 0 low output low-level output state 1 1 0 1 sck (serial clock) output state 3 * 2 1 1 1 0 high output high-level output state 1 1 1 1 sck (serial clock) output state notes: 1. the sck output state changes as soon as the cke0 bit setting is changed. clear the cke1 bit to 0. 2. stopping and starting the clock by changi ng the cke0 bit setting does not affect the clock duty cycle.
17. smart card interface rev.4.00 oct. 10, 2008 page 734 of 1122 rej09b0370-0400 port value width is undefined cke1 value specified width sck sck (a) when gm = 0 (b) when gm = 1 width is undefined specified width port value cke1 value figure 17.6 difference in clock ou tput according to gm bit setting 17.3.6 data transfer operations initialization: before transmitting and receiving data, th e smart card interface must be initialized as described below. initialization is also necessary when switching from tr ansmit mode to receive mode, or vice versa. figure 17.7 shows a sample initialization processing flowchart. 1. clear the te and re bits in the se rial control register (scscr1) to 0. 2. clear error flags fer/ers, per, and orer in the serial status regi ster (scssr1) to 0. 3. set the gm bit, parity bit (o/ e ), and baud rate generator select bits (cks1 and cks0) in the serial mode register (scsmr1). clear the chr and mp bits to 0, and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scscmr1). when the smif bit is set to 1, the txd pin and rxd pin both go to the high-impedance state. 5. set the value corresponding to the bit rate in the bit rate register (scbrr1). 6. set the clock source select bits (cke1 and cke0) in scscr1. clear the tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scscr1. do not set the te bit and re bit at the same tim e, except for self-diagnosis.
17. smart card interface rev.4.00 oct. 10, 2008 page 735 of 1122 rej09b0370-0400 initialization clear te and re bits in scscr1 to 0 clear fer/ers, per, and orer fla g s in scscr1 to 0 in scsmr1, set parity in o/ e bit, clock in cks1 and cks0 bits, and set gm set smif, sdir, and sinv bits in scscmr1 set value in scbrr1 in scscr1, set clock in cke1 and cke0 bits, and clear tie, rie, te, re, mpie, and teie bits to 0. 1-bit interval elapsed? set tie, rie, te, and re bits in scscr1 end wait no yes 1 2 3 4 5 6 7 figure 17.7 sample initialization flowchart
17. smart card interface rev.4.00 oct. 10, 2008 page 736 of 1122 rej09b0370-0400 serial data transmission: as data transmission in smart car d mode involves error signal sampling and retransmission processing, the proces sing procedure is differ ent from that for the normal sci. figure 17.8 shows a sample transmission processing flowchart. 1. perform smart card interface mode initialization as describe d in initialization above. 2. check that the fer/ers error fl ag in scssr1 is cleared to 0. 3. repeat steps 2 and 3 until it can be confirmed that the tend flag in scssr1 is set to 1. 4. write the transmit data to sctdr1, clear th e tdre flag to 0, an d perform the transmit operation. the tend flag is cleared to 0. 5. to continue transmitting data, go back to step 2. 6. to end transmission, clear the te bit to 0. with the above processing, interrupt handling is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit-d ata-empty interrupt (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transmit/receive-error in terrupt (eri) request will be generated. see interrupt operation below for details.
17. smart card interface rev.4.00 oct. 10, 2008 page 737 of 1122 rej09b0370-0400 start initialization start of transmission write transmit data to sctdr1, and clear tdre fla g in scssr1 to 0 fer/ers = 0? tend = 1? all data transmitted? fer/ers = 0? tend = 1? clear te bit in scscr1 to 0 end of transmission error handlin g error handlin g no yes yes yes yes no yes no no no 1 2 3 4 5 6 figure 17.8 sample transmission processing flowchart
17. smart card interface rev.4.00 oct. 10, 2008 page 738 of 1122 rej09b0370-0400 serial data reception: data reception in smart card mode uses the same processi ng procedure as for the normal sci. figure 17.9 shows a sample reception processing flowchart. 1. perform smart card interface mode initialization as describe d in initialization above. 2. check that the orer flag and per flag in scssr 1 are cleared to 0. if either is set, perform the appropriate receive error ha ndling, then clear both the or er and the per flag to 0. 3. repeat steps 2 and 3 until it can be confirmed that the rdrf flag is set to 1. 4. read the receive data from scrdr1. 5. to continue receiving data, clear the rdrf flag to 0 and go back to step 2. 6. to end reception, cl ear the re bit to 0. with the above processing, interrupt handling is possible. if reception ends and the rdrf flag is set to 1 wh ile the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full in terrupt (rxi) request w ill be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transmit/receive-error interrupt (eri) request will be generated. see interrupt operation below for details. if a parity error occurs during reception and the per flag is set to 1, the received data is still transferred to scrdr1 , and therefore this data can be read.
17. smart card interface rev.4.00 oct. 10, 2008 page 739 of 1122 rej09b0370-0400 start initialization start of reception read receive data from scrdr1 and clear rdrf fla g in scssr1 to 0 orer = 0 and per = 0? rdrf = 1? all data received? clear re bit in scscr1 to 0 end of reception error handlin g no yes yes yes no no 1 2 3 4 5 6 figure 17.9 sample recep tion processing flowchart mode switching operation: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from in itialization, clearing re to 0 and setting te to 1. the rdrf flag or the per and or er flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mo de, first confirm that th e transmit operation has been completed, then start from initialization, clearing te to 0 and setting re to 1. the tend flag can be used to check that the transmit operation has been completed.
17. smart card interface rev.4.00 oct. 10, 2008 page 740 of 1122 rej09b0370-0400 interrupt operation: there are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (t xi) requests, transmit/receive-error interrupt (eri) requests, and receive-data-full interrupt (rxi) requests. the tran smit-end interrupt (tei) request cannot be used in this mode. when the tend flag in scssr1 is set to 1, a txi interrupt request is generated. when the rdrf flag in scssr1 is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and fer/ers in scssr1 is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 17.9. table 17.9 smart card mode operati ng states and interrupt sources operating state flag mask bit interrupt source transmit mode normal operation tend tie txi error fer/ers rie eri receive mode normal operation rdrf rie rxi error per, orer rie eri data transfer operation by dmac: in smart card mode, as with th e normal sci, transfer can be carried out using the dmac. in a transmit operation, when the tend flag in scssr1 is set to 1, a txi interrupt is requested. if the txi request is designated beforehand as a dmac activation source, the dmac will be activated by the txi request, and transfer of the transmit data will be carried out. the tend flag is auto matically cleared to 0 when data transfer is performed by the dmac. in the event of an error, the sci retransm its the same data automatically. the tend flag remains cleared to 0 during this time, and the dm ac is not activated. thus , the number of bytes specified by the sci and dmac are transmitted automatically, including retransmission following an error. however, the ers flag is not cleared automatically when an error occurs, and therefore the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. in a receive operation, an rxi interrupt request is generated when the rdrf flag in scssr1 is set to 1. if the rxi request is designated be forehand as a dmac activ ation source, the dmac will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac. if an error occurs, an error flag is set but the rdrf flag is not. the dmac is not activated, but instead, an eri interrupt request is sent to the cpu. the error flag must therefore be cleared.
17. smart card interface rev.4.00 oct. 10, 2008 page 741 of 1122 rej09b0370-0400 when performing data transfer using the dmac, it is essential to set and enable the dmac before carrying out sci settings. for details of the dmac setting procedures, see section 14, direct memory acce ss controller (dmac). 17.4 usage notes the following points should be noted when using the sci as a smart card interface. (1) receive data sampling timing and receive margin in asynchronous mode, the sci operates on a base clock with a frequency of 372 times the transfer rate. in reception, the sci synchronizes internally w ith the fall of the start bit, which it samples on the base clock. receive data is latched at the risi ng edge of the 186th base clock pulse. the timing is shown in figure 17.10. 0 185 371 0 185 371 0 base clock 372 clocks 186 clocks start bit d0 d1 receive data (rxd) synchronization samplin g timin g data samplin g timin g figure 17.10 receive data sampling timing in smart card mode
17. smart card interface rev.4.00 oct. 10, 2008 page 742 of 1122 rej09b0370-0400 the receive margin in smart card mode can ther efore be expressed as shown in the following equation. m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n legend: m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 372) d: clock duty cycle (d = 0 to 1.0) l: frame length (l =10) f: absolute deviation of clock frequency from the above equation, if f = 0 and d = 0.5, the receive margin is 49.866 % , as given by the following equation. when d = 0.5 and f = 0: m = (0.5 ? 1/2 372) 100 % = 49.866 % (2) retransfer operations retransfer operations are performed by the sci in receive mode and transmit mode as described below. retransfer operation when sci is in receive mode: figure 17.11 illustrates the retransfer operation when the sci is in receive mode. 1. if an error is found when the received parity bit is chec ked, the per bit in scssr1 is automatically set to 1. if the rie bit in scscr1 is enabled at this time, an eri interrupt request is generated. the per bit in scssr1 should be cleared to 0 before the next parity bit is sampled. 2. the rdrf bit in scssr1 is not set for a frame in which an error has occurred. 3. if an error is found when the received parity bit is checked, th e per bit in scssr1 is not set to 1. 4. if no error is found when the received parity b it is checked, the receive operation is judged to have been completed normally, and the rdrf bit in scssr1 is automatically set to 1. if the rie bit in scscr1 is enabled at this time, an rxi interrupt request is generated. 5. when a normal frame is received, the pin reta ins the high-impedance st ate at the timing for error signal transmission.
17. smart card interface rev.4.00 oct. 10, 2008 page 743 of 1122 rej09b0370-0400 ds nth transfer frame retransferred frame transfer frame n+1 d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds ds d0 d0 d1 d1 d2 d2 de d3 d3 d4 d4 d5 d6 d7 dp rdrf per 1 2 3 4 5 figure 17.11 retransfer opera tion in sci receive mode retransfer operation when sci is in transmit mode: figure 17.12 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sent back from the r eceiving side after transmi ssion of one frame is completed, the fer/ers bit in scssr1 is set to 1. if the rie bit in scscr1 is enabled at this time, an eri interrupt request is generated. the fer/ers bit in scssr1 should be cleared to 0 before the next parity bit is sampled. 2. the tend bit in scssr1 is not set for a frame for which an error signal indicating an error is received. 3. if an error signal is not sent back from the receiving side, the fer/ers bit in scssr1 is not set. 4. if an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in scssr1 is set to 1. if the tie bit in scscr1 is enabled at this tim e, a txi interrupt request is generated. tdre ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds ds d0 d0 d1 d1 d2 d2 de d3 d3 d4 d4 d5 d6 d7 dp tend fer/ers 2 4 1 transfer from sctdr1 to sctsr1 nth transfer frame retransferred frame transfer frame n+1 transfer from sctdr1 to sctsr1 transfer from sctdr1 to sctsr1 3 figure 17.12 retransfer operation in sci transmit mode
17. smart card interface rev.4.00 oct. 10, 2008 page 744 of 1122 rej09b0370-0400 (3) standby mode and clock when switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. switching from smart card int erface mode to standby mode: 1. set the sbp1io and sbp1dt bits in scsptr1 to the values for the fixed output state in standby mode. 2. write 0 to the te and re bits in the serial co ntrol register (scscr1) to stop transmit/receive operations. at the same time, set the cke1 bit to the value for the fixed output state in standby mode. 3. write 0 to the cke0 bit in scscr1 to stop the clock. 4. wait for one serial clock cycle. during this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. write h'00 to the serial mode register (scsmr1) and smart card mode register (scsmr1). 6. make the transition to the standby state. returning from standby mode to smart card interface mode: 7. clear the standby state. 8. set the cke1 bit in scscr1 to the value for the fixed output state at the start of standby (the current sck pin state). 9. set smart card interface mode and output the cl ock. clock signal generation is started with the normal duty cycle. normal operation normal operation standby mode 1 2 3 4 5 6 7 8 9 figure 17.13 procedure for stop ping and restarting the clock
17. smart card interface rev.4.00 oct. 10, 2008 page 745 of 1122 rej09b0370-0400 (4) power-on and clock the following procedure should be used to s ecure the clock duty cycle after powering on. 1. the initial state is port input and high impedance. use pull-up or pull-down resistors to fix the potential. 2. fix at the output specified by the cke1 bit in the serial control register (scscr1). 3. set the serial mode register (scsmr1) and smart card mode register (scscmr1), and switch to smart card mode operation. 4. set the cke0 bit in scscr1 to 1 to start clock output.
17. smart card interface rev.4.00 oct. 10, 2008 page 746 of 1122 rej09b0370-0400
18. i/o ports rev.4.00 oct. 10, 2008 page 747 of 1122 rej09b0370-0400 section 18 i/o ports 18.1 overview this lsi has a 32-bit general-purpose i/o port, sci i/o port, and scif i/o port. 18.1.1 features the features of the general-pu rpose i/o port are as follows: ? available only in pci-disabled mode. ? 32-bit i/o port with input/output direction independently specifiable for each bit. ? pull-up can be specified in dependently for each bit. ? the 32 bits of the general-purpose i/o port are divided into 16-bit port a and 16-bit port b. interrupts can be input to 16-bit port a. ? use or non-use of the i/o port can be selected with the porten bit in bus control register 2 (bcr2). (do not set porten = 1 when in pci-enabled mode.) the features of the sci i/o port are as follows: ? data can be output when the i/o port is designated for output and sci enabling has not been set. this allows break function transmission. ? the rxd pin value can be read at all times, allowing break state detection. ? sck pin control is possible when the i/o port is designated for output and sci enabling has not been set. ? the sck pin value can be read at all times. the features of the scif i/o port are as follows: ? data can be output when the i/o port is designated for output and scif enabling has not been set. this allows break function transmission. ? the rxd2 pin value can be read at all times, allowing break state detection. ? sck2, cts2 , and rts2 pin control is possible when the i/o port is designated for output and scif enabling has not been set. ? the sck2, cts2 , and rts2 pin values can be read at all times.
18. i/o ports rev.4.00 oct. 10, 2008 page 748 of 1122 rej09b0370-0400 18.1.2 block diagrams figure 18.1 is a block diagram of the 16-bit general-purpose i/o port a with interrupt function. pbnpup porten adndir pbnio 0 1 pdtrw bck data input strobe d q c 0 1 0 1 mpx mpx mpx ptirenn bck c q d pull-up resistor port 15 (input / output)/ad15 to port 0 (input/ output)/ad0 adn output data internal bus interrupt controller porten 0: port not available 1: port available pbnpup 0: pull-up 1: pull-up off dndir 0: input 1: output pbnio 0: input 1: output ptirenn 0: interrupt input disabled 1: interrupt input enabled figure 18.1 16-bit port a
18. i/o ports rev.4.00 oct. 10, 2008 page 749 of 1122 rej09b0370-0400 figure 18.2 is a block diagram of the 16-bit general-purpose i/o port b, which has no interrupt function. pbnpup porten adndir pbnio 0 1 pdtrw bck d q c 0 1 0 1 bck c q d mpx mpx mpx data input strobe pull-up resistor port 31 (input/ output)/ad31 to port 16 (input/ output)/ad16 adn output data internal bus porten 0: port not available 1: port available pbnpup 0: pull-up 1: pull-up off dndir 0: input 1: output pbnio 0: input 1: output figure 18.2 16-bit port b
18. i/o ports rev.4.00 oct. 10, 2008 page 750 of 1122 rej09b0370-0400 sci i/o port block diagrams are shown in figures 18.3 to 18.5. reset reset internal data bus sptrw sptrw sci r q d spb1io c r q d spb1dt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * sck le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr1 and the c/ a bit in scsmr1. figure 18.3 sck pin
18. i/o ports rev.4.00 oct. 10, 2008 page 751 of 1122 rej09b0370-0400 reset internal data bus sptrw sci r q d spb0io c reset sptrw r q d spb0dt c txd transmit enable si g nal serial transmit data le g end: sptrw: write to sptr figure 18.4 txd pin internal data bus sci rxd sptrr serial receive data le g end: read sptr figure 18.5 rxd pin
18. i/o ports rev.4.00 oct. 10, 2008 page 752 of 1122 rej09b0370-0400 scif i/o port block diagrams are shown in figures 18.6 to 18.10. reset internal data bus sptrw mode settin g re g ister scif r q d spb2io c reset sptrw r q d spb2dt c md1/txd2 le g end: sptrw: write to sptr transmit enable si g nal serial transmit data figure 18.6 md1/txd2 pin internal data bus mode settin g re g ister scif md2/rxd2 sptrr serial receive data le g end: sptrr: read sptr figure 18.7 md2/rxd2 pin
18. i/o ports rev.4.00 oct. 10, 2008 page 753 of 1122 rej09b0370-0400 reset reset internal data bus sptrw sptrw scif r q d sckio c r q d sckdt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * md0/sck2 mode settin g re g ister le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck2 pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr2. figure 18.8 md0/sck2 pin
18. i/o ports rev.4.00 oct. 10, 2008 page 754 of 1122 rej09b0370-0400 reset internal data bus sptrw scif r q d ctsio c reset sptrr sptrw r q d ctsdt c md7/ cts2 mode settin g re g ister le g end: sptrw: write to sptr sptrr: read sptr note: * mce bit in scfcr2: si g nal that desi g nates modem control as the cts2 pin function. modem control enable si g nal * cts2 si g nal figure 18.9 md7/ cts2 pin
18. i/o ports rev.4.00 oct. 10, 2008 page 755 of 1122 rej09b0370-0400 reset internal data bus sptrw scif r q d rtsio c reset mode settin g re g ister sptrr sptrw r q d rtsdt c md8/ rts2 le g end: sptrw: write to sptr sptrr: read sptr note: * mce bit in scfcr2: si g nal that desi g nates modem control as the rts2 pin function. modem control enable si g nal * rts2 si g nal figure 18.10 md8/ rts2 pin 18.1.3 pin configuration table 18.1 shows the 32-bit general-purpose i/o port pin configuration. table 18.1 32-bit genera l-purpose i/o port pins pin name signal i/o function port 31 pin ad31/port31 i/o i/o port port 30 pin ad30/port30 i/o i/o port port 29 pin ad29/port29 i/o i/o port port 28 pin ad28/port28 i/o i/o port port 27 pin ad27/port27 i/o i/o port port 26 pin ad26/port26 i/o i/o port port 25 pin ad25/port25 i/o i/o port
18. i/o ports rev.4.00 oct. 10, 2008 page 756 of 1122 rej09b0370-0400 pin name signal i/o function port 24 pin ad24/port24 i/o i/o port port 23 pin ad23/port23 i/o i/o port port 22 pin ad22/port22 i/o i/o port port 21 pin ad21/port21 i/o i/o port port 20 pin ad20/port20 i/o i/o port port 19 pin ad19/port19 i/o i/o port port 18 pin ad18/port18 i/o i/o port port 17 pin ad17/port17 i/o i/o port port 16 pin ad16/port16 i/o i/o port port 15 pin ad15/port15 i/o * i/o port / gpio interrupt port 14 pin ad14/port14 i/o * i/o port / gpio interrupt port 13 pin ad13/port13 i/o * i/o port / gpio interrupt port 12 pin ad12/port12 i/o * i/o port / gpio interrupt port 11 pin ad11/port11 i/o * i/o port / gpio interrupt port 10 pin ad10/port10 i/o * i/o port / gpio interrupt port 9 pin ad9/port9 i/o * i/o port / gpio interrupt port 8 pin ad8/port8 i/o * i/o port / gpio interrupt port 7 pin ad7/port7 i/o * i/o port / gpio interrupt port 6 pin ad6/port6 i/o * i/o port / gpio interrupt port 5 pin ad5/port5 i/o * i/o port / gpio interrupt port 4 pin ad4/port4 i/o * i/o port / gpio interrupt port 3 pin ad3/port3 i/o * i/o port / gpio interrupt port 2 pin ad2/port2 i/o * i/o port / gpio interrupt port 1 pin ad1/port1 i/o * i/o port / gpio interrupt port 0 pin ad0/port0 i/o * i/o port / gpio interrupt note: * when port pins are used as gpio interrupts, they must be set to input mode. the input setting can be made in the pctra register.
18. i/o ports rev.4.00 oct. 10, 2008 page 757 of 1122 rej09b0370-0400 table 18.2 shows the sci i/o port pin configuration. table 18.2 sci i/o port pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin txd out put transmit data output note: they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr1 and the c/ a bit in scsmr1. break state transmission and detection can be performed by means of a setting in the sci's scsptr1 register. table 18.3 shows the scif i/o port pin configuration. table 18.3 scif i/o port pins pin name abbreviation i/o function serial clock pin md0/sc k2 i/o clock input/output receive data pin md2/rxd2 input receive data input transmit data pin md1/txd2 output transmit data output modem control pin md7/ cts2 i/o transmission enabled modem control pin md8/ rts2 i/o transmission request note: these pins function as the md0, md1, md 2, md7, and md8 mode input pins after a power- on reset. these pins are made to function as serial pins by performing scif operation settings with the te, re, cke1, and cke0 bits in scscr2 and the mce bit in scfcr2. break state transmission and detection can be set in the scif's scsptr2 register.
18. i/o ports rev.4.00 oct. 10, 2008 page 758 of 1122 rej09b0370-0400 18.1.4 register configuration the 32-bit general-purpose i/o port, sci i/o port, and scif i/o port have seven registers, as shown in table 18.4. table 18.4 i/o port registers name abbreviation r/w initial value * p4 address area 7 address access size port control register a pctra r/w h'00000000 h'ff80002c h'1f80002c 32 port data register a pdtra r/ w undefined h'ff 800030 h'1f800030 16 port control register b pctrb r/w h'00000000 h'ff800040 h'1f800040 32 port data register b pdtrb r/ w undefined h'ff 800044 h'1f800044 16 gpio interrupt control register gpioic r/w h'00000000 h'ff800048 h' 1f800048 16 serial port register scsptr1 r/ w undefined h'ffe0001c h'1fe0001c 8 serial port register scsptr2 r/w undefined h'ffe80020 h'1fe80020 16 note: * initialized by a power-on reset.
18. i/o ports rev.4.00 oct. 10, 2008 page 759 of 1122 rej09b0370-0400 18.2 register descriptions 18.2.1 port control register a (pctra) port control register a (pctra) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port a (port 15 pin to port 0 pin). as the initial value of port data register a (pdtra) is undefined, all the bits in the 16-bit port a should be set to output with pctra after writing a value to the pdtra register. pctra is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 pb15pup pb15io pb14pup pb14io pb 13pup pb13io pb12pup pb12io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 pb11pup pb11io pb10pup pb10io pb9pup pb9io pb8pup pb8io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 pb7pup pb7io pb6pup pb6io pb5pup pb5io pb4pup pb4io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb3pup pb3io pb2pup pb2io pb1pup pb1io pb0pup pb0io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
18. i/o ports rev.4.00 oct. 10, 2008 page 760 of 1122 rej09b0370-0400 bit 2n + 1 (n = 0?15)?port pull-up control (pbnpup): specifies whether each bit in the 16- bit port a is to be pulled up with a built-in resistor. pull-up is automatically turned off for a port pin set to output by bit pbnio. bit 2n + 1: pbnpup description 0 bit m (m = 0?15) of 16-bit port a is pulled up (initial value) 1 bit m (m = 0?15) of 16-bit port a is not pulled up bit 2n (n = 0?15)?port i/o control (pbnio): specifies whether each bit in the 16-bit port a is an input or an output. bit 2n: pbnio description 0 bit m (m = 0?15) of 16-bit port a is an input (initial value) 1 bit m (m = 0?15) of 16-bit port a is an output 18.2.2 port data register a (pdtra) port data register a (pdtra) is a 16-bit readable/w ritable register used as a data latch for each bit in the 16-bit port a. when a bit is set as an ou tput, the value written to the pdtra register is output from the external pin. when a value is read from the pdtra register while a bit is set as an input, the external pin value sampled on the extern al bus clock is read. when a bit is set as an output, the value written to the pdtra register is read. pdtra is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 pb15dt pb14dt pb13dt pb12dt pb11dt pb10dt pb9dt pb8dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w
18. i/o ports rev.4.00 oct. 10, 2008 page 761 of 1122 rej09b0370-0400 18.2.3 port control register b (pctrb) port control register b (pctrb) is a 32-bit readable /writable register that controls the input/output direction and pull-up for each bit in the 16-bit port b (port 31 pin to port 16 pin). as the initial value of port data register b (pdtrb) is undefined, each bit in the 16-bit port b should be set to output with pctrb after writing a value to the pdtrb register. pctrb is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 pb31pup pb31io pb30pup pb30io pb 29pup pb29io pb28pup pb28io initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 pb27pup pb27io pb26pup pb26io pb 25pup pb25io pb24pup pb24io initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 pb23pup pb23io pb22pup pb22io pb 21pup pb21io pb20pup pb20io initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pb19pup pb19io pb18pup pb18io pb 17pup pb17io pb16pup pb16io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
18. i/o ports rev.4.00 oct. 10, 2008 page 762 of 1122 rej09b0370-0400 bit 2n + 1 (n = 0?15)?port pull-up control (pbnpup): specifies whether each bit in the 16- bit port b is to be pulled up with a built-in resistor. pull-up is automatically turned off for a port pin set to output by bit pbnio. bit 2n + 1: pbnpup description 0 bit m (m = 16?31) of 16-bit port b is pulled up (initial value) 1 bit m (m = 16?31) of 16-bit port b is not pulled up bit 2n (n = 0?15)?port i/o control (pbnio): specifies whether each bit in the 16-bit port b is an input or an output. bit 2n: pbnio description 0 bit m (m = 16?31) of 16-bit port b is an input (initial value) 1 bit m (m = 16?31) of 16-bit port b is an output 18.2.4 port data register b (pdtrb) port data register b (pdtrb) is a 16-bit readable/w ritable register used as a data latch for each bit in the 16-bit port b. when a bit is set as an output, the value written to the pdtrb register is output from the external pin. when a value is read from the pdtrb register while a bit is set as an input, the external pin value sampled on the extern al bus clock is read. when a bit is set as an output, the value written to the pdtrb register is read. pdtrb is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 pb31dt pb30dt pb29dt pb28dt pb27dt pb26dt pb25dt pb24dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb23dt pb22dt pb21dt pb20dt pb19dt pb18dt pb17dt pb16dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w
18. i/o ports rev.4.00 oct. 10, 2008 page 763 of 1122 rej09b0370-0400 18.2.5 gpio interrupt control register (gpioic) the gpio interrupt control register (gpioic) is a 16-bit readable/writable register that performs 16-bit interrupt input control. gpioic is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. gpio interrupts are active-low level interrupts. b it-by-bit masking is possible, and the or of all the bits set as gpio interrupts is used for interrupt detection. which bits interrupts are input to can be identified by reading the pdtra register. bit: 15 14 13 12 11 10 9 8 ptiren15 ptiren14 ptiren13 ptiren12 ptiren11 ptiren10 ptiren9 ptiren8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ptiren7 ptiren6 ptiren5 ptiren4 ptiren3 ptiren2 ptiren1 ptiren0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit n (n = 0?15)?port interrupt enable (ptirenn): specifies whether interrupt input is performed for each bit. bit n: ptirenn description 0 port m (m = 0?15) of 16-bit port a is used as a normal i/o port (initial value) 1 port m (m = 0?15) of 16-bit port a is used as a gpio interrupt * note: * when using an interrupt, set the corresponding port to input in the pctra register before making the ptirenn setting.
18. i/o ports rev.4.00 oct. 10, 2008 page 764 of 1122 rej09b0370-0400 18.2.6 serial port register (scsptr1) bit: 7 6 5 4 3 2 1 0 eio ? ? ? spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 ? 0 ? r/w: r/w ? ? ? r/w r/w r/w r/w the serial port register (scsptr1) is an 8-bit r eadable/writable register that controls input/output and data for the port pins mu ltiplexed with the serial communi cation interface (sci) pins. input data can be read from the rxd pin, output data written to the txd pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. sck pin data reading and output data writing can be performed by means of bits 3 and 2. bit 7 controls enabling and disabling of the rxi interrupt. scsptr1 can be read or written to by the cpu at all times. all scsptr1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manua l reset; the value of bits 2 and 0 is undefined. scsptr1 is not initialized in the module standby state or standby mode. bit 7?error interrupt only (eio): see section 15.2.8, serial port register (scsptr1). bits 6 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?serial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr1 and the cke1 and cke0 b its in scscr1 should be cleared to 0. bit 3: spb1io description 0 spb1dt bit value is not output to the sck pin (initial value) 1 spb1dt bit value is output to the sck pin bit 2?serial port cloc k port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of bit 3, spb1io, for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 2: spb1dt description 0 input/output data is low-level 1 input/output data is high-level
18. i/o ports rev.4.00 oct. 10, 2008 page 765 of 1122 rej09b0370-0400 bit 1?serial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr1 should be cleared to 0. bit 1: spb0io description 0 spb0dt bit value is not output to the txd pin (initial value) 1 spb0dt bit value is output to the txd pin bit 0?serial port break data (spb0dt): specifies the serial port rxd pin input data and txd pin output data. the txd pin output condition is specified by the spb0io bit (see the description of bit 1, spb0io, for details). when the txd pin is designated as an output, the value of the spb0dt bit is output to the txd pin. the rxd pin value is read from the spb0dt bit regardless of the value of the spb0io bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb0dt description 0 input/output data is low-level 1 input/output data is high-level 18.2.7 serial port register (scsptr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 rtsio rtsdt ctsio ctsd t sckio sckdt spb2io spb2dt initial value: 0 ? 0 ? 0 ? 0 ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial port register (scsptr2) is a 16-bit read able/writable register that controls input/output and data for the port pins multip lexed with the serial communicat ion interface with fifo (scif) pins. input data can be read from the rxd2 pin, output data written to the txd2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. sck2 pin data reading and output data writing can be performed by means of bits 3 and 2. cts2 pin data reading and output
18. i/o ports rev.4.00 oct. 10, 2008 page 766 of 1122 rej09b0370-0400 data writing can be performed by means of bits 5 and 4, and rts2 pin data reading and output data writing by means of bits 7 and 6. scsptr2 can be read or written to by the cpu at all times. all scsptr2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or ma nual reset; the value of bits 6, 4, 2, and 0 is undefined. scsptr2 is not initialized in standby mode or in the module standby state. bits 15 to 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?serial port rts port i/o (rtsio): specifies serial port rts2 pin input/output. when the rts2 pin is actually set as a port output pin and outputs the value set by the rtsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 7: rtsio description 0 rtsdt bit value is not output to the rts2 pin (initial value) 1 rtsdt bit value is output to the rts2 pin bit 6?serial port rts port data (rtsdt): specifies the serial port rts2 pin input/output data. input or output is specified by the rtsio pin (see the description of bit 7, rtsio, for details). when the rts2 pin is designated as an output, the value of the rtsdt bit is output to the rts2 pin. the rts2 pin value is read from the rtsdt bit regardless of the value of the rtsio bit. the initial value of this bit after a po wer-on reset or manual reset is undefined. bit 6: rtsdt description 0 input/output data is low-level 1 input/output data is high-level bit 5?serial port cts port i/o (ctsio): specifies serial port cts2 pin input/output. when the cts2 pin is actually set as a port output pin and outputs the value set by the ctsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 5: ctsio description 0 ctsdt bit value is not output to the cts2 pin (initial value) 1 ctsdt bit value is output to the cts2 pin
18. i/o ports rev.4.00 oct. 10, 2008 page 767 of 1122 rej09b0370-0400 bit 4?serial port cts port data (ctsdt): specifies the serial port cts2 pin input/output data. input or output is specified by the ctsio pin (see the description of bit 5, ctsio, for details). when the cts2 pin is designated as an output, the value of the ctsdt bit is output to the cts2 pin. the cts2 pin value is read from the ctsdt bit regardless of the value of the ctsio bit. the initial value of this bit after a po wer-on reset or manual reset is undefined. bit 4: ctsdt description 0 input/output data is low-level 1 input/output data is high-level bit 3?serial port cloc k port i/o (sckio): sets the i/o for the sck2 pin serial port. to actually set the sck2 pin as the port output pin and output the value set in the sckdt bit, set the cke1 and cke0 bits of th e scscr2 register to 0. bit 3: sckio description 0 shows that the value of the sckdt bit is not output to the sck2 pin (initial value) 1 shows that the value of the sckdt bit is output to the sck2 pin bit 2?serial port cloc k port data (sckdt): specifies the i/o data fo r the sck2 pin serial port. the sckio bit specified input or output. (see bit 3: sckio, for details.) when set for output, the value of the sckdt bit is output to the sck2 pin. regardless of the value of the sckio bit, the value of the sck2 pin is fetche d from the sckdt bit. the initial value after a power-on reset or manual reset is undefined. bit 2: sckdt description 0 shows i/o data level is low 1 shows i/o data level is high bit 1?serial port break i/o (spb2io): specifies the serial port txd2 pin output condition. when the txd2 pin is actually set as a port output pin and outputs the value set by the spb2dt bit, the te bit in scscr2 should be cleared to 0. bit 1: spb2io description 0 spb2dt bit value is not output to the txd2 pin (initial value) 1 spb2dt bit value is output to the txd2 pin
18. i/o ports rev.4.00 oct. 10, 2008 page 768 of 1122 rej09b0370-0400 bit 0?serial port break data (spb2dt): specifies the serial port rxd2 pin input data and txd2 pin output data. the txd2 pin output condition is specified by the spb2io bit (see the description of bit 1, spb2io, for details). when the txd2 pin is designated as an output, the value of the spb2dt bit is output to the txd2 pin. the rxd2 pin value is read from the spb2dt bit regardless of the value of the spb2io bit. the init ial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb2dt description 0 input/output data is low-level 1 input/output data is high-level
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 769 of 1122 rej09b0370-0400 section 19 interrupt controller (intc) 19.1 overview the interrupt controller (intc) ascertains the prio rity of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 features the intc has the following features. ? fifteen interrupt priority levels can be set by setting the five interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. ? nmi noise canceler function the nmi input level bit indicates the nmi pin st ate. the pin state can be checked by reading this bit in the interrupt exception handler, enabling it to be used as a noise canceler. ? nmi request masking when sr.bl bit is set it is possible to select whether or not nmi requests are to be masked when the sr.bl bit is set. 19.1.2 block diagram figure 19.1 shows a block diagram of the intc.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 770 of 1122 rej09b0370-0400 legend: tmu: timer unit rtc: realtime clock unit sci: serial communication interface scif: serial communication interface with fifo wdt: watchdog timer ref: memory refresh controller section of the bus state controller dmac: direct memory access controller h-udi: high-performance user debug interface unit gpio: i/o port pcic: pci bus controller icr: interrupt control register ipra?iprd: interrupt priority registers a?d intpri00: interrupt priority register 00 sr: status register nmi input control irl3 ? irl0 tmu rtc sci scif wdt ref dmac h-udi priority identifier 4 4 (interrupt request) com- parator bus interface internal bus icr ipra?iprd, intpri00 (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) intc interrupt request imask sr cpu ipr gpio (interrupt request) pcic figure 19.1 block diagram of intc
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 771 of 1122 rej09b0370-0400 19.1.3 pin configuration table 19.1 shows the intc pin configuration. table 19.1 intc pins pin name abbreviation i/o function nonmaskable interrupt input pin nmi input input of nonmaskable interrupt request signal interrupt input pins irl3 ? irl0 input input of interrupt request signals (maskable by imask in sr) 19.1.4 register configuration the intc has the registers shown in table 19.2. table 19.2 intc registers name abbreviation r/w initial value * 1 p4 address area 7 address access size interrupt control register icr r/w * 2 h'ffd00000 h'1fd00000 16 interrupt priority register a ipra r/w h'0000 h 'ffd00004 h'1fd00004 16 interrupt priority register b iprb r/w h'0000 h 'ffd00008 h'1fd00008 16 interrupt priority register c iprc r/w h'0000 h'ffd 0000c h'1fd0000c 16 interrupt priority register d iprd r/w h'da74 h'ffd00010 h'1fd00010 16 interrupt priority register 00 intpri00 r/w h'00000000 h'fe080000 h'1e080000 32 interrupt request register 00 intreq00 r h'00000000 h'fe080020 h'1e080020 32 interrupt mask register 00 intmsk00 r/w h'000003ff h'fe080040 h'1e080040 32 interrupt mask clear register 00 intmskclr00 w ? h'fe080060 h'1e080060 32 notes: 1. initialized by a power-on reset or manual reset. 2. h'8000 when the nmi pin is hi gh, h'0000 when the nmi pin is low.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 772 of 1122 rej09b0370-0400 19.2 interrupt sources there are three types of interrupt sources: nmi, irl, and on-chip peripheral modules. each interrupt has a priority level (16?0), with level 16 as the highest and level 1 as the lowest. when level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 nmi interrupt the nmi interrupt has the highest pr iority level of 16. it is alwa ys accepted unless the bl bit in the status register in the cpu is set to 1. in sleep or standby mode, the interrupt is accepted even if the bl bit is set to 1. a setting can also be made to have the nmi inte rrupt accepted even if the bl bit is set to 1. input from the nmi pin is edge-detected. the nmi ed ge select bit (nmie) in the interrupt control register (icr) is used to select either rising or falling edge. when the nmie bit in the icr register is modified, the nmi interrupt is not detected for a maximum of 6 bus clock cycles after the modification. nmi interrupt exception handling does not affect the interrupt mask level bits (imask) in the status register (sr).
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 773 of 1122 rej09b0370-0400 19.2.2 irl interrupts irl interrupts are input by level at pins irl3 ? irl0 . the priority level is the level indicated by pins irl3 ? irl0 . an irl3 ? irl0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). a value of 15 (1111) indicates no interrupt request (interrupt priority level 0). interrupt requests priority encoder irl3 to irl0 4 sh7751/sh7751r irl3 to irl0 figure 19.2 example of irl interrupt connection
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 774 of 1122 rej09b0370-0400 table 19.3 irl3 ? irl0 pins and interrupt levels irl3 irl2 irl1 irl0 interrupt priority level interrupt request 0 0 0 0 15 level 15 interrupt request 1 14 level 14 interrupt request 1 0 13 level 13 interrupt request 1 12 level 12 interrupt request 1 0 0 11 level 11 interrupt request 1 10 level 10 interrupt request 1 0 9 level 9 interrupt request 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 6 level 6 interrupt request 1 0 5 level 5 interrupt request 1 4 level 4 interrupt request 1 0 0 3 level 3 interrupt request 1 2 level 2 interrupt request 1 0 1 level 1 interrupt request 1 0 no interrupt request a noise-cancellation feature is built in, and the irl interrupt is not detected unless the levels sampled at every bus clock cycle remain unchan ged for three consecutive cycles, so that no transient level on the irl pin change is detected. in stand by mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 khz clock for the rtc instead. when the rtc is not used, therefore, interruption by means of irl interrupts cannot be performed in standby mode. the priority level of the irl interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. however, the priority level can be changed to a higher one. the interrupt mask bits (imask) in the status re gister (sr) are not affe cted by irl interrupt handling. pins irl0 ? irl3 can be used for four independent interrupt requests by setting the irlm bit to 1 in the icr register.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 775 of 1122 rej09b0370-0400 19.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following ten modules: ? high-performance user debu g interface unit (h-udi) ? direct memory access controller (dmac) ? timer unit (tmu) ? realtime clock (rtc) ? serial communicati on interface (sci) ? serial communication inte rface with fifo (scif) ? bus state controller (bsc) ? watchdog timer (wdt) ? i/o port (gpio) ? pci bus controller (pcic) not every interrupt source is assigned a different in terrupt vector, bus sources are reflected in the interrupt event register (intevt), so it is easy to identify sources by using the intevt register value as a branch offset in the exception handling routine. a priority level from 15 to 0 can be set for each module by means of interrupt priority registers a to d (ipra?iprd) and interrupt priority register 00 (intpri00). the interrupt mask bits (imask) in the status regi ster (sr) are not affected by on-chip peripheral module interrupt handling. on-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the bl bit in th e status register (sr) is set to 1. to prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the bl bit to 0. furthermore, in case of an interrupt of tmu channels 3 and 4 and pcic, read the interrupt factor register 00 (intreq00). this will secure the necessary tim ing internally. when updating a nu mber of flags, there is no problem if only the register containing the last flag updated is read. if flag updating is performed while the bl bit is cleared to 0, the program may jump to the interrupt handling routine when the intevt register value is 0. in this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. processing can be continued without any problem by executing an rte instruction.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 776 of 1122 rej09b0370-0400 19.2.4 interrupt exceptio n handling and priority table 19.4 lists the codes for the interrupt event register (intevt), and the order of interrupt priority. each interrupt source is assigned a unique intevt code. th e start address of the interrupt handler is common to each interrupt source. this is why, for instance, the value of intevt is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. the order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority regi sters a to d (ipra?iprd) and interrupt priority register 00 (intpri00). the order of priority of the on-chip peripheral modules is set to 0 by a reset. when the priorities for multiple interrupt sources ar e set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.4. updating of interrupt priority registers a to d, and intpri00 should only be carried out when the bl bit in the status register (sr) is set to 1. to prevent erroneous interr upt acceptance, first read one of the interrupt priority regist ers, then clear the bl bit to 0. this will secure the necessary timing internally.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 777 of 1122 rej09b0370-0400 table 19.4 interrupt exception ha ndling sources and priority order interrupt source intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 16 ? ? high irl irl3 ? irl0 = 0 h'200 15 ? ? irl3 ? irl0 = 1 h'220 14 ? ? irl3 ? irl0 = 2 h'240 13 ? ? irl3 ? irl0 = 3 h'260 12 ? ? irl3 ? irl0 = 4 h'280 11 ? ? irl3 ? irl0 = 5 h'2a0 10 ? ? irl3 ? irl0 = 6 h'2c0 9 ? ? irl3 ? irl0 = 7 h'2e0 8 ? ? irl3 ? irl0 = 8 h'300 7 ? ? irl3 ? irl0 = 9 h'320 6 ? ? irl3 ? irl0 = a h'340 5 ? ? irl3 ? irl0 = b h'360 4 ? ? irl3 ? irl0 = c h'380 3 ? ? irl3 ? irl0 = d h'3a0 2 ? ? irl3 ? irl0 = e h'3c0 1 ? ? irl0 h'240 15?0 (13) iprd (15?12) ? irl1 h'2a0 15?0 (10) iprd (11?8) ? irl2 h'300 15?0 (7) iprd (7?4) ? irl3 h'360 15?0 (4) iprd (3?0) ? h-udi h-udi h'600 15?0 (0) iprc (3?0) ? gpio gpioi h'620 15?0 (0) iprc (15?12) ? dmac dmte0 h'640 15?0 (0) iprc (11?8) high dmte1 h'660 dmte2 h'680 dmte3 h'6a0 dmte4 * h'780 dmte5 * h'7a0 dmte6 * h'7c0 dmte7 * h'7e0 dmae h'6c0 low low
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 778 of 1122 rej09b0370-0400 interrupt source intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority pcic pciserr h'a00 15?0 (0) intpri00 (3?0) ? pcierr h'ae0 15?0 (0) high pcipwdwn h'ac0 pcipwon h'aa0 pcidma0 h'a80 pcidma1 h'a60 pcidma2 h'a40 pcidma3 h'a20 intpri00 (7?4) low tmu3 tuni3 h'b00 15?0 (0) intpri00 (11?8) ? tmu4 tuni4 h'b80 15?0 (0) intpri00 (15?12) ? tmu0 tuni0 h'400 15?0 (0) ipra (15?12) ? tmu1 tuni1 h'420 15?0 (0) ipra (11?8) ? tmu2 tuni2 h'440 15?0 (0) ipra (7?4) high ticpi2 h'460 low rtc ati h'480 15?0 (0) ipra (3?0) high pri h'4a0 cui h'4c0 low sci eri h'4e0 15?0 (0) iprb (7?4) high rxi h'500 txi h'520 tei h'540 low scif eri h'700 15?0 (0) iprc (7?4) high rxi h'720 bri h'740 txi h'760 low wdt iti h'560 15?0 (0) iprb (15?12) ? ref rcmi h'580 15?0 (0) iprb (11?8) high high rovi h'5a0 low low legend: tuni0?tuni4: underflow interrupts
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 779 of 1122 rej09b0370-0400 ticpi2: input capture interrupt ati: alarm interrupt pri: periodic interrupt cui: carry-up interrupt eri: receive-error interrupt rxi: receive-data-full interrupt txi: transmit-data-empty interrupt tei: transmit-end interrupt bri: break interrupt request iti: interval timer interrupt rcmi: compare-match interrupt rovi: refresh counter overflow interrupt h-udi: h-udi interrupt gpioi: i/o port interrupt dmte0?dmte7: dmac transfer end interrupts dmae: dmac address error interrupt pciserr: pcic serr error interrupt pcierr: pcic error interrupt pcipwdwn: pcic power-down request interrupt pcipwon: pcic power-on request interrupt pcidma0 to 3: pcic dma transfer end interrupts note: * sh7751r only
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 780 of 1122 rej09b0370-0400 19.3 register descriptions 19.3.1 interrupt pr iority registers a to d (ipra?iprd) interrupt priority registers a to d (ipra?iprd) are 16-bit readable/writa ble registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. ipra to iprc are initialized to h'0000 and iprd is to h'da74 by a reset. they are not initialized in standby mode. ipra to iprc bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w iprd bit: 15 14 13 12 11 10 9 8 initial value: 1 1 0 1 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 1 1 1 0 1 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 19.5 shows the relationship between the interrupt request sources and the ipra?iprd register bits.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 781 of 1122 rej09b0370-0400 table 19.5 interrupt request so urces and ipra?iprd registers bits register 15?12 11?8 7?4 3?0 interrupt priority register a tmu0 tmu1 tmu2 rtc interrupt priority register b wdt ref * 1 sci1 reserved * 2 interrupt priority register c gpio dmac scif h-udi interrupt priority register d irl0 irl1 irl2 irl3 notes: 1. ref is the memory refresh unit in t he bus state controller (bsc). see section 13, bus state controller (bsc), for details. 2. reserved bits: these bits are always re ad as 0 and should always be written with 0. as shown in table 19.5, four on-chip peripheral modules are assigned to each register. interrupt priority levels are established by setting a value from h'f (1111) to h'0 (0000) in each of the four- bit groups: 15?12, 11?8, 7?4, and 3?0. setting h'f designates priority level 15 (the highest level), and setting h'0 designates priority level 0 (requests are masked). 19.3.2 interrupt control register (icr) the interrupt control register (icr) is a 16-bit regi ster that sets the input signal detection mode for external interrupt input pin nmi an d indicates the input signal level at the nmi pin. this register is initialized by a power-on reset or manual reset. it is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: nmil mai ? ? ? ? nmib nmie initial value: 0/1 * 0 0 0 0 0 0 0 r/w: r r/w ? ? ? ? r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: irlm ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w ? ? ? ? ? ? ? note: * 1 when nmi pin input is high, 0 when low.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 782 of 1122 rej09b0370-0400 bit 15?nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. it cannot be modified. bit 15: nmil description 0 nmi pin input level is low 1 nmi pin input level is high bit 14?nmi interrupt mask (mai): specifies whether or not all interrupts are to be masked while the nmi pin input level is low, irrespective of the cpu's sr.bl bit. bit 14: mai description 0 interrupts enabled even while nmi pin is low (initial value) 1 interrupts disabled while nmi pin is low * note: * nmi interrupts are accepted in normal operation and in sleep mode. in standby mode, all interrupts are masked, and standby is not cleared, while the nmi pin is low. bit 9?nmi block mode (nmib): specifies whether an nmi request is to be held pending or detected immediately while the sr.bl bit is set to 1. bit 9: nmib description 0 nmi interrupt requests held pending while sr.bl bit is set to 1 (initial value) 1 nmi interrupt requests detected while sr.bl bit is set to 1 notes: 1. if interrupt requests are enabled while sr.bl = 1, the previous exception information will be lost, and so must be saved beforehand. 2. this bit is cleared automatically by nmi acceptance. bit 8?nmi edge select (nmie): specifies whether the falling or rising edge of the interrupt request signal to the nmi pin is detected. bit 8: nmie description 0 interrupt request detected on falling edge of nmi input (initial value) 1 interrupt request detected on rising edge of nmi input
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 783 of 1122 rej09b0370-0400 bit 7?irl pin mode (irlm): specifies whether pins irl3 ? irl0 are to be used as level- encoded interrupt requests or as four independent interrupt requests. bit 7: irlm description 0 irl pins used as level-encoded interrupt requests (initial value) 1 irl pins used as four independent in terrupt requests (level-sense irq mode) bits 13 to 10 and 6 to 0?reserved: these bits are always read as 0, and should only be written with 0. 19.3.3 interrupt priori ty level settting regi ster 00 (intpri00) the interrupt priority level setting register (intpri00 ) sets the order of priority (levels 15 to 0) of the internal peripheral module interrupts. the intpri00 register is a 32-bit read/write register. it is initialized to h'00000000 at a reset. it is not initialized in standby mode. bit: 31 30 29 . . . 19 18 17 16 . . . initial value: 0 0 0 . . . 0 0 0 0 r/w: r r r . . . r r r r bit: 15 14 13 . . . 3 2 1 0 . . . initial value: 0 0 0 . . . 0 0 0 0 r/w: r/w r/w r/w . . . r/w r/w r/w r/w table 19.6 shows the relationship between interrup t request sources and the respective bits of the intpri00 register. table 19.6 interrupt request sources and intpri00 register bits register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0 interrupt priority level setting register reserved reserved reserved reserved tmu ch4 tmu ch3 pci (1) pci (0) note: reserved bits: these bits always r ead as 0, and should only be written with 0.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 784 of 1122 rej09b0370-0400 as shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register. values of h'f (1111) to h'0 (0 000) can be set in each 4 bits, allowing the order levels of the corresponding interrupts to be set. h'f is priority le vel 15 (highest level) while h'0 is priority level 0 (request mask). reserved: these bits are always read as 0, and should only be written with 0. 19.3.4 interrupt factor register 00 (intreq00) the interrupt factor register 00 (intreq00) shows which interrupt have been requested of the intc. even when the interrupts are masked with intpri00 and intmsk00, the bits in this register are not affected. intreq00 is a 32-bit read-only register. bit: 31 30 29 . . . 11 10 9 8 . . . initial value: 0 0 0 . . . 0 0 0 0 r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 31 to 0?interrupt request: these bits indicate the existe nce of an interrupt request corresponding to each bit. for the corres pondence between bits and in terrupt sources, see section 19.3.7, intreq00, intmsk00, and intmskclr00 bit allocation. bits 31 to 0 description 0 shows no corresponding interrupt request (initial value) 1 shows existence of corresponding interrupt request 19.3.5 interrupt mask re gister 00 (intmsk00) the interrupt mask register 00 (intmsk00) specifies whether or not to mask individual interrupts each time they are requested. the intmsk00 register is a 32-bit register. it is initialized to h'000003ff at a reset. the values are retained in standby mode.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 785 of 1122 rej09b0370-0400 to clear each interrupt mask, writ e 1 to the corresponding bit of the intmskclr00 register. the values in intmsk00 do not change if you write 0 to it. bit: 31 30 29 . . . 11 10 9 8 . . . initial value: 0 0 0 . . . 0 0 1 1 r/w: r r r . . . r r r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0?in terrupt masks: these bits indicate the existence of an interrupt request corresponding to each bit. for the corres pondence between bits and in terrupt sources, see section 19.3.7, intreq00, intmsk00, and intmskclr00 bit allocation. bits 31 to 0 description 0 accept corresponding interrupt request 1 mask corresponding interrupt request 19.3.6 interrupt mask clea r register 00 (intmskclr00) the interrupt mask clear register 00 (intmskc lr00) clears the masks for each request of the corresponding interrupt. intmskclr00 is a 32-bit write-only register. bit: 31 30 29 . . . 11 10 9 8 . . . initial value: ? ? ? . . . ? ? ? ? r/w: w w w . . . w w w w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: w w w w w w w w
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 786 of 1122 rej09b0370-0400 bits 31 to 0?interrupt mask clear: these bits indicate the existence of an interrupt request corresponding to each bit. for the corres pondence between bits and in terrupt sources, see section 19.3.7, intreq00, intmsk00, and intmskclr00 bit allocation. bits 31 to 0 description 0 do not change corresponding interrupt mask 1 clear corresponding interrupt mask 19.3.7 intreq00, intmsk00, a nd intmskclr00 bit allocation the following shows the relationship between individual bits in the register and interrupt factors. table 19.7 bit allocation bit no. module interrupt 31 to 10 reserved reserved 9 tmu tuni4 8 tmu tuni3 7 pci pcierr 6 pci pcipwdwn 5 pci pcipwon 4 pci pcidma0 3 pci pcidma1 2 pci pcidma2 1 pci pcidma3 0 pci pciserr
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 787 of 1122 rej09b0370-0400 19.4 intc operation 19.4.1 interrupt operation sequence the sequence of operations when an interrupt is generated is described below. figure 19.3 shows a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller select s the highest-priority interrupt fr om the interrupt requests sent, according to the priority levels set in interr upt priority registers a to d (ipra?iprd) and interrupt priority register 00 (intpri00). lower-priority interrupts are held pending. if two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.4, inte rrupt exception handling sources and priority order, is selected. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (imask) in the status register (sr) of the cpu. if the request priority level is higher that the level in bits imask, the in terrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the cpu accepts an interrupt at a break between instructions. 5. the interrupt source code is set in the interrupt event register (intevt). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). the interrupt handler may branch with the intevt re gister value as its offset in order to identify the interrupt source. this enables it to branch to the handling routine for the particular interrupt source. notes: 1. the interrupt mask bits (imask) in the status register (sr) are not changed by acceptance of an interr upt in this lsi. 2. the interrupt source flag s hould be cleared in the exception handling routine. to ensure that an interrupt request th at should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.8 (time for priority decision and sr mask bit comparison) before clearing the bl bit or executing an rte instruction. 3. depending on the interrupt factor, the interrupt mask (intmsk00) must be cleared for each factor using th e intmskclr00 register. see s ection 19.3.5, interrupt mask register 00 (intmsk00), and section 19.3.6, interrupt mask clear register 00 (intmskclr00), for details.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 788 of 1122 rej09b0370-0400 program execution state no no yes no yes no yes yes no no yes yes no yes no no yes no yes save sr to ssr; save pc to spc set interrupt source in intevt set bl, md, rb bits in sr to 1 branch to exception handler interrupt generated? (bl bit in sr = 0) or (sleep or standby mode)? nmi? level 14 interrupt? level 1 interrupt? imask = level 13 or lower? imask = level 0? yes level 15 interrupt? imask * = level 14 or lower? note: * imask: interrupt mask bits in status register (sr) nmib in icr = 1 and nmi? figure 19.3 interrupt operation flowchart
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 789 of 1122 rej09b0370-0400 19.4.2 multiple interrupts when handling multiple interrupts, interrupt handling should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in the intevt register. the code in intevt can be used as a branch-offset for branching to the specific handler. 2. clear the interrupt source in the corresponding interrupt handler. 3. save spc and ssr to the stack. 4. clear the bl bit in sr, and set the accepted inte rrupt level in the interr upt mask bits in sr. 5. handle the interrupt. 6. set the bl bit in sr to 1. 7. restore ssr and spc from memory. 8. execute the rte instruction. when these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing bl in step 4. this enables the interrupt response time to be shortened for urgent processing. 19.4.3 interrupt ma sking with mai bit by setting the mai bit to 1 in the icr register, it is possible to mask interrupts while the nmi pin is low, irrespective of the bl and imask bits in the sr register. ? in normal operation and sleep mode all interrupts are masked while the nmi pin is low. however, an nmi interrupt only is generated by a transition at the nmi pin. ? in standby mode all interrupts are masked while the nmi pin is low, and an nmi interrupt is not generated by a transition at the nmi pin. therefore, standby cannot be cleared by an nmi interrupt while the mai bit is set to 1.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 790 of 1122 rej09b0370-0400 19.5 interrupt response time the time from generation of an interrupt reques t until interrupt exception handling is performed and fetching of the first instruct ion of the exception handler is started (the interrupt response time) is shown in table 19.8. table 19.8 interrupt response time number of states item nmi rl peripheral modules notes time for priority decision and sr mask bit comparison * 1icyc + 4bcyc 1icyc + 7bcyc 1icyc + 2bcyc wait time until end of sequence being executed by cpu s ? 1 ( 0) icyc s ? 1 ( 0) icyc s ? 1 ( 0) icyc time from interrupt exception handling (save of sr and pc) until fetch of first instruction of exception handler is started 4 icyc 4 icyc 4 icyc response time total 5icyc + 4bcyc + (s ? 1)icyc 5icyc + 7bcyc + (s ? 1)icyc 5icyc + 2bcyc + (s ? 1)icyc minimum case 13icyc 19icyc 9icyc when icyc: bcyc = 2:1 maximum case 36 + s icyc 60 + s icyc 20 + s icyc when icyc: bcyc = 8:1 legend: icyc: one cycle of internal cl ock supplied to cpu, etc. bcyc: one ckio cycle s: latency of instruction note: * in the sh7751, this includes the case where the mask bit (imask) in sr is changed and a new interrupt is generated.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 791 of 1122 rej09b0370-0400 19.6 usage notes 19.6.1 nmi interrupts (sh7751 only) when multiple nmi interrupts are input to the nmi pin within a set period of time (which is dependent on the internal state of the cpu and the external bus st ate), subsequent interrupts may not be accepted. note that this problem does not occur when sufficient time* 1 is provided between nmi interrupt inputs or with non-nmi interrupts such as irl interrupts. workarounds: any of the following methods may be used to avoid the above problem. (1) allow sufficient time between nmi interrupt inputs, as described in note 1, below. note that it may not be possible to assure the above interval between nmi interrupt inputs if hazard is input to nmi, and that this may cause the device to malfunction. design the external circuits so that no hazard is input via nmi.* 2 (2) do not use nmi interrupts. use irl interrupts instead. (3) workaround using software the above problem can be avoided by inserting the following lines of code* 3 * 4 into the nmi exception handling routine. notes: 1. if sr.bl is cleared to 0 so that one or more instructions may be executed between the handling of two nmi interrupts. 2. when changing the level of the nmi input, ensure that the high and low durations are at least 5 ckio cycles. also ensure that no noise pulses occur before or after level changes. 3. if the nmi exception handling routine contains code that changes the value of the sr.bl bit, the code listed below should be inserted before the point at which the change is made. 4. registers r0 to r3 in the code sample can be changed to any general register. also, the necessary register save and restore instructions should be inserted before and after the code listed below, as appropriate.
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 792 of 1122 rej09b0370-0400 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; r0 : tmp ;; r1 : original sr ;; r2 : original icr ;; r3 : icr address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; nmih: ; (1) set sr.imask = h'f stc sr, r1 ; store sr mov r1,r0 or #h'f0,r0 ldc r0, sr ; (2) reverse icr.nmie mov.l #icr, r3 mov.w @r3, r2 ; store icr mov.w #h'0100, r0 xor r2, r0 mov.w r0, @r3 ; write icr.nmie inverted (dummy) bra nmih1 nop .pool .align 4 nmih2: ; mov.w @r3, r0 ; dummy read mov.w r2, @r3 ; write icr.nmie stc sr, r0 ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 793 of 1122 rej09b0370-0400 ldc r1, sr ; restore sr bra nmih3 nop nmih1: bra nmih2 nop nmih3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
19. interrupt controller (intc) rev.4.00 oct. 10, 2008 page 794 of 1122 rej09b0370-0400
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 795 of 1122 rej09b0370-0400 section 20 user br eak controller (ubc) 20.1 overview the user break controller (ubc) provides functions that simplify program debugging. when break conditions are set in the ubc, a user break interrupt is generated according to the contents of the bus cycle generated by the cpu. this function makes it easy to design an effective self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. 20.1.1 features the ubc has the following features. ? two break channels (a and b) user break interrupts can be generated on independent conditions for channels a and b, or on sequential conditions (sequential break setting: channel a channel b). ? the following can be set as break compare conditions: ? address (selection of 32-bit virtual address and asid for comparison): address: all bits compared/lower 10 bits ma sked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked asid: all bits compared/all bits masked ? data (channel b only, 32-bit mask capability) ? bus cycle: instruction access/operand access ? read/write ? operand size: byte/word/longword/quadword ? an instruction access cycle break ca n be effected before or afte r the instruction is executed.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 796 of 1122 rej09b0370-0400 20.1.2 block diagram figure 20.1 shows a block diagram of the ubc. access control address bus data bus channel a access comparator address comparator channel b access comparator address comparator data comparator bbra bara basra bamra bbrb barb basrb bamrb bdrb bdmrb brcr control user break trap request le g end: bbra: break bus cycle re g ister a bara: break address re g ister a basra: break asid re g ister a bamra: break address mask re g ister a bbrb: break bus cycle re g ister b barb: break address re g ister b basrb: break asid re g ister b bamrb: break address mask re g ister b bdrb: break data re g ister b bdmrb: break data mask re g ister b brcr: break control re g ister figure 20.1 block diagra m of user break controller
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 797 of 1122 rej09b0370-0400 table 20.1 shows the ubc registers. table 20.1 ubc registers name abbreviation r/w initial value p4 address area 7 address access size break address register a bara r/w undefined h'ff200000 h' 1f200000 32 break address mask register a bamra r/w undefined h'ff200004 h'1f200004 8 break bus cycle register a bbra r/w h'0000 h'ff200008 h'1f200008 16 break asid register a basra r/w undefined h'ff000014 h'1f000014 8 break address register b barb r/w undefined h'ff20000c h'1f20000c 32 break address mask register b bamrb r/w undefined h'ff200010 h'1f200010 8 break bus cycle register b bbrb r/w h'0000 h'ff200014 h'1f200014 16 break asid register b basrb r/w undefined h'ff000018 h'1f000018 8 break data register b bdrb r/w undefined h'ff200018 h' 1f200018 32 break data mask register b bdmrb r/w undefined h'ff20001c h'1f20001c 32 break control register brcr r/w h'0000 * h'ff200020 h'1f200020 16 note: * some bits are not initialized. see section 20.2.12, break control register (brcr), for details.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 798 of 1122 rej09b0370-0400 20.2 register descriptions 20.2.1 access to ubc registers the access size must be the same as the control regi ster size. if the sizes are different, a write will not be effected in a ubc register write operation, and a read operation will return an undefined value. ubc register contents cannot be transferred to a floating-point register using a floating- point memory load instruction. when a ubc register is updated, use either of the following methods to make the updated value valid: 1. execute an rte instruction after the memory store instruction that upd ated the register. the updated value will be valid from the rte instruction jump destination onward. 2. execute instructions requiring 5 states for execution after the memory store instruction that updated the register. as the cpu executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. the updated value will be valid from the 6th state onward.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 799 of 1122 rej09b0370-0400 20.2.2 break address register a (bara) bit: 31 30 29 28 27 26 25 24 baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined break address register a (bara) is a 32-bit readable/writable regi ster that specifies the virtual address used in the channel a break conditions. bara is not initialized by a power-on reset or manual reset. bits 31 to 0?break address a31 to a0 (baa31?baa0): these bits hold the virtual address (bits 31?0) used in the channel a break conditions.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 800 of 1122 rej09b0370-0400 20.2.3 break asid register a (basra) bit: 7 6 5 4 3 2 1 0 basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined break asid register a (basra) is an 8-bit read able/writable register th at specifies the asid used in the channel a break conditions. basra is not initialized by a power-on reset or manual reset. bits 7 to 0?break asid a7 to a0 (basa7?basa0): these bits hold the asid (bits 7?0) used in the channel a break conditions. 20.2.4 break address ma sk register a (bamra) bit: 7 6 5 4 3 2 1 0 ? ? ? ? bama2 basma bama1 bama0 initial value: 0 0 0 0 * * * * r/w: r r r r r/w r/w r/w r/w note: * undefined break address mask register a (b amra) is an 8-bit readable/writable register that specifies which bits are to be masked in the break asid set in basra and the break address set in bara. bamra is not initialized by a power-on reset or manual reset. bits 7 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 2?break asid mask a (basma): specifies whether all bits of the channel a break asid (basa7?basa0) are to be masked. bit 2: basma description 0 all basra bits are incl uded in break conditions 1 no basra bits are include d in break conditions
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 801 of 1122 rej09b0370-0400 bits 3, 1, and 0?break address mask a2 to a0 (bama2?bama0): these bits specify which bits of the channel a break address (baa31?baa0) set in bara are to be masked. bit 3: bama2 bit 1: bama1 bit 0: bama0 description 0 0 0 all bara bits are included in break conditions 1 lower 10 bits of bara are masked, and not included in break conditions 1 0 lower 12 bits of bara are masked, and not included in break conditions 1 all bara bits are masked, and not included in break conditions 1 0 0 lower 16 bits of bara are masked, and not included in break conditions 1 lower 20 bits of bara are masked, and not included in break conditions 1 * reserved (cannot be set) legend: * don't care 20.2.5 break bus cycl e register a (bbra) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? sza2 ida1 ida0 rwa1 rwa0 sza1 sza0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w break bus cycle register a (bbra) is a 16-bit readable/writable register that sets three conditions?(1) instruction access/operand access, (2) read/write, and (3) operand size?from among the channel a break conditions. bbra is initialized to h'0000 by a power-on reset. it retains its value in standby mode. bits 15 to 7?reserved: these bits are always read as 0, and should only be written with 0.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 802 of 1122 rej09b0370-0400 bits 5 and 4?instruction access/opera nd access select a (ida1, ida0): these bits specify whether an instruction access cycle or an operan d access cycle is used as the bus cycle in the channel a break conditions. bit 5: ida1 bit 4: ida0 description 0 0 condition comparison is not performed (initial value) 1 instruction access cycle is used as break condition 1 0 operand access cycle is used as break condition 1 instruction access cycle or operand access cycle is used as break condition bits 3 and 2?read/write select a (rwa1, rwa0): these bits specify whether a read cycle or write cycle is used as the bus cycle in the channel a break conditions. bit 3: rwa1 bit 2: rwa0 description 0 0 condition comparison is not performed (initial value) 1 read cycle is used as break condition 1 0 write cycle is used as break condition 1 read cycle or write cycle is used as break condition bits 6, 1, and 0?operand si ze select a (sza2?sza0): these bits select the operand size of the bus cycle used as a channel a break condition. bit 6: sza2 bit 1: sza1 bit 0: sza0 description 0 0 0 operand size is not included in break conditions (initial value) 1 byte access is used as break condition 1 0 word access is used as break condition 1 longword access is used as break condition 1 0 0 quadword access is used as break condition 1 reserved (cannot be set) 1 * reserved (cannot be set) legend: * don't care
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 803 of 1122 rej09b0370-0400 20.2.6 break addres s register b (barb) barb is the channel b break address register. th e bit configuration is the same as for bara. 20.2.7 break asid register b (basrb) basrb is the channel b break asid register. the bit configuration is the same as for basra. 20.2.8 break address ma sk register b (bamrb) bamrb is the channel b break address mask regist er. the bit configuration is the same as for bamra. 20.2.9 break data register b (bdrb) bit: 31 30 29 28 27 26 25 24 bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 804 of 1122 rej09b0370-0400 break data register b (bdrb) is a 32-bit readable/w ritable register that specifies the data (bits 31? 0) to be used in the channel b break conditions. bdrb is not initialized by a power-on reset or manual reset. bits 31 to 0?break data b31 to b0 (bdb31?bdb0): these bits hold the data (bits 31?0) to be used in the channel b break conditions. 20.2.10 break data mask register b (bdmrb) bit: 31 30 29 28 27 26 25 24 bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined break data mask register b (bdmrb) is a 32-bit readable/writable register that specifies which bits of the break data set in bdrb are to be masked. bdmrb is not initialized by a power-on reset or manual reset.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 805 of 1122 rej09b0370-0400 bits 31 to 0?break data mask b31 to b0 (bdmb31?bdmb0): these bits specify whether the corresponding bit of the channel b break data (bdb31?bdb0) set in bdrb is to be masked. bit 31?0: bdmbn description 0 channel b break data bit bdbn is included in break conditions 1 channel b break data bit bdbn is masked, and not included in break conditions notes: n = 31 to 0 when the data bus value is included in the br eak conditions, the operand size should be specified. when byte size is specified, set the same data in bits 15?8 and 7?0 of bdrb and bdmrb. 20.2.11 break bus cycle register b (bbrb) bbrb is the channel b bus break register. the b it configuration is the same as for bbra. 20.2.12 break contro l register (brcr) bit: 15 14 13 12 11 10 9 8 cmfa cmfb ? ? ? pcba ? ? initial value: 0 0 0 0 0 * 0 0 r/w: r/w r/w r r r r/w r r bit: 7 6 5 4 3 2 1 0 dbeb pcbb ? ? seq ? ? ubde initial value: * * 0 0 * 0 0 0 r/w: r/w r/w r r r/w r r r/w note: * undefined the break control register (brcr) is a 16-bit readab le/writable register that specifies (1) whether channels a and b are to be used as two independ ent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the bdrb register is to be included in the channel b break conditions, and (4) whether the user break debug function is to be used. brcr also contains condition match flags. the cmfa, cmfb, and ubde bits in brcr are initialized to 0 by a power-on re set, but retain their value in standby mode. the value of the pcba, dbeb, pcbb, and seq bits is undefined after a power-on reset or manual reset, so these bits should be in itialized by software as necessary.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 806 of 1122 rej09b0370-0400 bit 15?condition match flag a (cmfa): set to 1 when a break condition set for channel a is satisfied. this flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). bit 15: cmfa description 0 channel a break condition is not matched (initial value) 1 channel a break condition match has occurred bit 14?condition match flag b (cmfb): set to 1 when a break condition set for channel b is satisfied. this flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). bit 14: cmfb description 0 channel b break condition is not matched (initial value) 1 channel b break condition match has occurred bits 13 to 11?reserved: these bits are always read as 0, and should only be written with 0. bit 10?instruction access break select a (pcba): specifies whether a channel a instruction access cycle break is to be effected before or af ter the instruction is executed. this bit is not initialized by a power-on reset or manual reset. bit 10: pcba description 0 channel a pc break is effect ed before instruction execution 1 channel a pc break is effected after instruction execution bits 9 and 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?data break enable b (dbeb): specifies whether the data bus condition is to be included in the channel b break conditions. this bit is not initialized by a power-on reset or manual reset. bit 7: dbeb description 0 data bus condition is not included in channel b conditions 1 data bus condition is included in channel b conditions note: when the data bus is included in the break conditions, bits idb1?0 in break bus cycle register b (bbrb) should be set to 10 or 11.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 807 of 1122 rej09b0370-0400 bit 6?pc break select b (pcbb): specifies whether a channel b instruction access cycle break is to be effected before or after the instruction is executed. this bit is not initialized by a power-on reset or manual reset. bit 6: pcbb description 0 channel b pc break is effect ed before instruction execution 1 channel b pc break is effected after instruction execution bits 5 and 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?sequence condition select (seq): specifies whether the conditi ons for channels a and b are to be independent or sequential. this bit is no t initialized by a power-on reset or manual reset. bit 3: seq description 0 channel a and b comparisons are performed as independent conditions 1 channel a and b comparisons are performed as sequential conditions (channel a channel b) bits 2 and 1?reserved: these bits are always read as 0, and should only be written with 0. bit 0?user break debug enable (ubde): specifies whether the user break debug function (see section 20.4, user break debug support function) is to be used. bit 0: ubde description 0 user break debug function is not used (initial value) 1 user break debug function is used
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 808 of 1122 rej09b0370-0400 20.3 operation 20.3.1 explanation of t erms relating to accesses an instruction access is an access that obtains an instruction. for example, the fetching of an instruction from the branch destination when a br anch instruction is exec uted is an instruction access. an operand access is any memory access fo r the purpose of instru ction execution. for example, the access to address pc+disp 2+4 in the instruction mov.w@(disp,pc), rn is an operand access. as the term ?data? is used to distin guish data from an addr ess, the term ?operand access? is used in this section. in this lsi, all operand accesses are treated as either read accesses or write accesses. the following instructions require special attention: ? pref, ocbp, and ocbwb instructio ns: treated as read accesses. ? movca.l and ocbi instructions: treated as write accesses. ? tas.b instruction: treated as one read access and one write access. the operand accesses for the pref , ocbp, ocbwb, and ocbi inst ructions are accesses with no access data. this lsi handles all operand accesses as having a data size. the data size can be byte, word, longword, or quadword. the operand data si ze for the pref, ocbp, ocbwb, movca.l, and ocbi instructions is treated as longword. 20.3.2 explanation of terms relating to instruction intervals in this section, ?1 (2, 3, ...) instruction(s) af ter...?, as a measure of the distance between two instructions, is defined as follows. a branch is counted as an interval of two instructions. ? example of sequence of instructions with no branch: 100 instruction a (0 instructions after instruction a) 102 instruction b (1 instruction after instruction a) 104 instruction c (2 instructions after instruction a) 106 instruction d (3 instructions after instruction a)
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 809 of 1122 rej09b0370-0400 ? example of sequence of instruc tions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 instruction a: bt/s l200 (0 instructions after instruction a) 102 instruction b (1 instruction after instruction a, 0 instructions after instruction b) l200 200 instruction c (3 instructions after inst ruction a, 2 instructions after instruction b) 202 instruction d (4 instructions after instruction a, 3 instructions after instruction b) 20.3.3 user break operation sequence the sequence of operations from setting of brea k conditions to user break exception handling is described below. 1. specify pre- or post-execu tion breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel a and b break conditions, in the break control register (brcr). set the break addresses in the break address registers for each channel (bara, barb), the asids corr esponding to the break space in the break asid registers (basra, basrb), and the address and asid masking methods in the break address mask registers (bamra, bamrb). if the data bus value is to be included in the break conditions, also set the break data in the break data regist er (bdrb) and the data mask in the break data mask register (bdmrb). 2. set the break bus conditions in the break bus cycle registers (bbra, bbrb). if even one of the bbra/bbrb instruction access/operand access select (id bit) and read/write select groups (rw bit) is set to 00, a user break interrupt w ill not be generated on the corresponding channel. make the bbra and bbrb settings after all other br eak-related register settings have been completed. if breaks are enabled with bbra/ bbrb while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. the operation when a break condition is satisfied depends on the bl bit (in the cpu's sr register). when the bl bit is 0, exception handling is started and the condition match flag (cmfa/cmfb) for the respective channel is set fo r the matched condition. when the bl bit is 1, the condition match flag (cmfa/cmfb) for the respective channel is set for the matched condition but exception handling is not started. the condition match flags (cmfa, cmfb) are set by a branch condition match, but are not reset. therefore, a memory store instruction should be used on the brcr register to clear the flags to 0. see section 20.3.6, condition match flag setting, for the exact setting conditions for the condition match flags.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 810 of 1122 rej09b0370-0400 4. when sequential condition mode has been se lected, and the channel b condition is matched after the channel a condition has been matched, a break is effected at the instruction at which the channel b condition was matched. see section 20.3.8, contiguous a and b settings for sequential conditions, for the operation when the channel a condition match and channel b condition match occur close together. with sequential conditions, only the channel b condition match flag is set. when sequential condition mode has been selected, if it is wished to clear the channel a match when the channel a condition has been matched but the channel b condition has not yet been matched, this can be done by writing 0 to the seq bit in the brcr register. 20.3.4 instruction access cycle break 1. when an instruction access/re ad/word setting is made in the break bus cycle register (bbra/bbrb), an instruction access cycle can be used as a break condition. in this case, breaking before or after execution of the re levant instruction can be selected with the pcba/pcbb bit in the br eak control register (brcr). when an instruction access cycle is used as a break condition, clear the lsb of the break address registers (bara, barb) to 0. a break will not be generated if this bit is set to 1. 2. when a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. therefore, overrun-fetched instructions (instructions that are fetched but not executed when a branch or exception occurs) cannot be used in a break. however, if a tlb miss or tlb protection violation exception occurs at the time of the fetch of instructions subject to a break, the break exception handling is carried out first. the instruction tlb exception handling is performed when the instruction is re-executed (see section 5.4, exception types and priorities). also , since a delayed branch instruction and the delay slot instruction are executed as a single in struction, if a pre-execu tion break is specified for a delay slot instruction, the break will be e ffected before execution of the delayed branch instruction. however, a pre-execution break cannot be specified for the delay slot instruction for an rte instruction. 3. with a post-execution break, the instruction se t as a break condition is executed, then a break interrupt is generated before the next instruction is executed. when a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). 4. when an instruction access cycle is set for cha nnel b, break data register b (bdrb) is ignored in judging whether there is an instruction acce ss match. therefore, a br eak condition specified by the dbeb bit in brcr is not executed.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 811 of 1122 rej09b0370-0400 20.3.5 operand access cycle break 1. in the case of an operand access cycle break, the bits included in addre ss bus comparison vary as shown below according to the data size sp ecification in the break bus cycle register (bbra/bbrb). data size address bits compared quadword (100) address bits a31?a3 longword (011) address bits a31?a2 word (010) address bits a31?a1 byte (001) address bits a31?a0 not included in condition (000) in quadword access, address bits a31?a3 in longword access, address bits a31?a2 in word access, address bits a31?a1 in byte access, address bits a31?a0 2. when data bus is included in break conditions in channel b when a data value is included in the break conditions, set the dbeb bit in the break control register (brcr) to 1. in this case, break data register b (bdrb) and break data mask register b (bdmrb) settings are necessary in addition to the address condition. a user break interrupt is generated when all three conditions?address, asid, and data?are matched. when a quadword access occurs, the 64-bit access data is di vided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. a break is generated if either of the 32-bit data units satisfies the data match condition. set the idb1?0 bits in break bus cycle regist er b (bbrb) to 10 or 11. when byte data is specified, the same data should be set in the two bytes comprising bits 15?8 and bits 7?0 in break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31?16 of bdrb and bdmrb are ignored. 3. when the dbeb bit in the break control register (brcr) is set to 1, a break is not generated by an operand access with no access data (an operand access in a pref, ocbp, ocbwb, or ocbi instruction).
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 812 of 1122 rej09b0370-0400 20.3.6 condition ma tch flag setting 1. instruction access with post-e xecution condition, or operand access the flag is set when execution of the instructi on that causes the break is completed. as an exception to this, however, in the case of an in struction with more th an one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. example 1: 100 bt l200 (branch performed) 102 instruction (operand access break on channel a) flag not set example 2: 110 fadd (fpu exception) 112 instruction (operand access break on channel a) flag not set 2. instruction access with pre-execution condition the flag is set when the break match condition is detected. example 1: 110 instruction (pre-execution break on channel a) flag set 112 instruction (pre-execution break on channel b) flag not set example 2: 110 instruction (pre-execution break on channel b, instruction access tlb miss) flag set 20.3.7 program counter (pc) value saved 1. when instruction access (pre-ex ecution) is set as a break cond ition, the program counter (pc) value saved to spc in user break interrupt handling is the address of the instruction at which the break condition match occurred. in this case, a user break interrupt is generated and the fetched instruction is not executed. 2. when instruction access (post-ex ecution) is set as a break cond ition, the program counter (pc) value saved to spc in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. in this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. when an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). in this case, the pc
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 813 of 1122 rej09b0370-0400 value saved to spc is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. when operand access (address only) is set as a break condition, the addr ess of the instruction to be executed after the instruction at which the condition match occurred is saved to spc. 5. when operand access (address + data) is set as a break condition, execut ion of the instruction at which the condition match occurre d is completed. a user break interrupt is generated before execution of instructions from one instruction later to four instructions later. it is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. the start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to spc. if an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. designating the exception ca used by the break as exception 1, and the exception caused by an instruction between one in struction later and four instructions later as exception 2, memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the exis tence of exception 1. the program counter value saved is the address of the first instruction for which execution is suppressed. whether exception 1 or exception 2 is used for the exception jump destination and the value written to the excep tion register (expevt/intevt) is not guaranteed. however, if exception 2 is from a source no t synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (expevt/intevt). 20.3.8 contiguous a and b settings for sequential conditions when channel a match and channel b match timings are close together, a sequential break may not be guaranteed. rules relating to the guaranteed range are given below. 1. instruction access matches on both channel a and channel b instruction b is 0 instructions after instruction a equivalent to setting the same address. do not use this setting instruction b is 1 instruction after instruction a sequential operation is not guaranteed instruction b is 2 or more instructions after instruction a sequential operation is guaranteed
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 814 of 1122 rej09b0370-0400 2. instruction access match on channe l a, operand access match on channel b instruction b is 0 or 1 instruction after instruction a sequential operation is not guaranteed instruction b is 2 or more instructions after instruction a sequential operation is guaranteed 3. operand access match on channel a, instruction access match on channel b instruction b is 0 to 3 instructions after instruction a sequential operation is not guaranteed instruction b is 4 or more instructions after instruction a sequential operation is guaranteed 4. operand access matches on bo th channel a and channel b do not make a setting such that a single operand access will match th e break conditions of both channel a and channel b. there are no other restrictions. for example, sequential operation is guaranteed even if two accesses with in a single instruction match channel a and channel b conditions in turn. 20.3.9 usage notes 1. do not execute a post-exe cution instruction access break for the sleep instruction. 2. do not make an operand access break setting between 1 and 3 instructions before a sleep instruction. 3. the value of the bl bit referenced in a user break exception depends on the break setting, as follows. a. pre-execution in struction access break: the bl bit value before the executed instruction is referenced. b. post-execution instruction access break: the or of the bl bit values before and after the executed instruction is referenced. c. operand access break (address/data): the bl bit value after the exec uted instruction is referenced. d. in the case of an instruction that modifies the bl bit
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 815 of 1122 rej09b0370-0400 sl.bl pre- execution instruction access post- execution instruction access pre- execution instruction access post- execution instruction access operand access (address/data) 0 0 a a a a a 1 0 m m m m a 0 1 a m a m m 1 1 m m m m m legend: a: accepted m: masked e. in the case of an rte delay slot the bl bit value before execution of a delay slot instruction is the same as the bl bit value before execution of an rte instruction. the bl bit value after execution of a delay slot instruction is the same as the first bl bit value for the first instruction executed on returning by means of an rte instruction (the same as the value of the bl bit in ssr before execution of the rte instruction). f. if an interrupt or exception is accepted with th e bl bit cleared to 0, the value of the bl bit before execution of the first instruction of the exception handling routine is 1. 4. if channels a and b both match independently at virtually the same time, and, as a result, the spc value is the same for both user break interrupt s, only one user break interrupt is generated, but both the cmfa bit and the cmfb bit are set. for example: 110 instruction (post-execution instruction break on channel a) spc = 112, cmfa = 1 112 instruction (pre-execution instruction break on channel b) spc = 112, cmfb = 1 5. the pcba or pcbb bit in brcr is valid for an inst ruction access break setting. 6. when the seq bit in brcr is 1, the internal sequential break state is initialized by a channel b condition match. for example: a a b (user break generated) b (no break generated) 7. in the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type excep tion is generated. in this case, the cmf bit may or may not be set to 1 when the break condition occurs. 8. a post-execution break is cla ssified as a completion type excep tion. consequently, in the event of contention between a completion type exce ption and a post-execution break, the post- execution break is suppressed in accordance with th e priorities of the tw o events. for example,
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 816 of 1122 rej09b0370-0400 in the case of contention between a trapa inst ruction and a post-execu tion break, the user break is suppressed. however, in this case, the cmf bit is set by the occurrence of the break condition. 20.4 user break debug support function the user break debug support function enables the processing used in the event of a user break exception to be changed. when a user break exception occurs, if the ubde bit is set to 1 in the brcr register, the dbr register value will be used as the branch destination address instead of [vbr + offset]. the value of r15 is saved in the sgr register regardless of the value of the ubde bit in the brcr register or the kind of exception event. a flowch art of the user break debug support function is shown in figure 20.2.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 817 of 1122 rej09b0370-0400 spc pc ssr sr sr.bl b'1 sr.md b'1 sr.rb b'1 exception/interrupt g eneration exception exception/ interrupt/trap? trap interrupt pc h'a0000000 pc vbr + vector offset exception handlin g routine execute rte instruction pc spc sr ssr sgr r15 expevt h'160 tra trapa (imm) pc dbr debu g pro g ram r15 sgr (stc instruction) reset exception? (brcr.ubde == 1) && (user break exception)? end of exception operations intevt interrupt code expevt exception code yes no no yes hardware operation figure 20.2 user break debug support function flowchart
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 818 of 1122 rej09b0370-0400 20.5 examples of use instruction access cycle br eak condition settings ? register settings: basra = h'80 / bara = h'00000404 / bamra = h'00 / bbra = h'0014 / basrb = h'70 / barb = h'00008010 / bamrb = h'01 / bbrb = h'0014 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0400 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00000404 / address mask: h'00 bus cycle: instruction access (pos t-instruction-execution), read (operand size not included in conditions) ? channel b: asid: h'70 / address: h'00008010 / address mask: h'01 data: h'00000000 / data mask: h'00000000 bus cycle: instruction access (pre -instruction-execution), read (o perand size not included in conditions) a user break is generated after execution of the instruction at address h'00000404 with asid = h'80, or before execution of an instruction at addresses h'00008000?h'000083fe with asid = h'70. ? register settings: basra = h'80 / bara = h'00037226 / bamra = h'00 / bbra = h'0016 / basrb = h'70 / barb = h'0003722e / bamrb = h'00 / bbrb = h'0016 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0008 conditions set: channel a channel b sequential mode ? channel a: asid: h'80 / address: h'00037226 / address mask: h'00 bus cycle: instruction access (pre-i nstruction-executio n), read, word ? channel b: asid: h'70 / address: h'0003722e / address mask: h'00 data: h'00000000 / data mask: h'00000000 bus cycle: instruction access (pre-i nstruction-executio n), read, word the instruction at address h'00 037266 with asid = h'80 is ex ecuted, then a user break is generated before execution of the instruction at address h'0003722e with asid = h'70. ? register settings: basra = h'80 / bara = h'00027128 / bamra = h'00 / bbra = h'001a / basrb = h'70 / barb = h'00031415 / bamrb = h'00 / bbrb = h'0014 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0000
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 819 of 1122 rej09b0370-0400 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00027128 / address mask: h'00 bus cycle: cpu, instruction access (pre -instruction-execution), write, word ? channel b: asid: h'70 / address: h'00031415 / address mask: h'00 data: h'00000000 / data mask: h'00000000 bus cycle: cpu, instruction access (pre-instr uction-execution), read (operand size not included in conditions) a user break interrupt is not generated on cha nnel a since the instruction access is not a write cycle. a user break interrupt is not generated on ch annel b since instructio n access is performed on an even address. operand access cycle break condition settings ? register settings: basra = h'80 / bara = h'00123456 / bamra = h'00 / bbra = h'0024 / basrb = h'70/ barb = h'000abcde / bamrb = h'02 / bbrb = h'002a / bdrb = h'0000a512 / bdmrb = h'00000000 / brcr = h'0080 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00123456 / address mask: h'00 bus cycle: operand access, read (operand size not included in conditions) ? channel b: asid: h'70 / address: h'000abcde / address mask: h'02 data: h'0000a512 / data mask: h'00000000 bus cycle: operand access, write, word data break enabled on channel a, a user break interrupt is generated in the event of a longword read at address h'00123454, a word read at address h'00123456, or a byte read at address h'00123456, with asid = h'80. on channel b, a user break interrupt is genera ted when h'a512 is written by word access to any address from h'000ab000 to h'000abffe with asid = h'70.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 820 of 1122 rej09b0370-0400 20.6 user break controller stop function this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. note that, if you use this function, you cannot use the user break controller. 20.6.1 transition to user br eak controller stopped state setting the mstp5 bit of the stbcr2 (inside the cpg) to 1 stops the clock supply and causes the user break controller to enter the stopped state. follow steps (1) to (5) below to set the mstp5 bit to 1 and enter the stopped state. (1) initialize bbra and bbrb to 0; (2) initialize brcr to 0; (3) make a dummy read of brcr; (4) read stbcr2, then set the mstp5 bit in the read data to 1 and write back. (5) make two dummy reads of stbcr2. make sure that, if an exception or interrupt occu rs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. do not read or write the following registers wh ile the user break controller clock is stopped: bara, bamra, bbra, barb, bamrb, bbrb, bdrb, bdmrb, and brcr. if these registers are read or written, the value cannot be guaranteed. 20.6.2 cancelling the user break controller stopped state the clock supply can be restarted by setting the ms tp5 bit of stbcr2 (inside the cpg) to 0. the user break controller can then be operated again. follow steps (6) and (7) below to clear the mstp5 bit to 0 to cancel the stopped state. (6) read stbcr2, then clear the mstp5 bit in the read data to 0 and write the modified data back; (7) make two dummy reads of stbgr2. as with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine.
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 821 of 1122 rej09b0370-0400 20.6.3 examples of stopping and restarting the user break controller the following are example programs: ; transition to user break controller stopped state ; (1) initialize bbra and bbrb to 0. mov #0, r0 mov.l #bbra, r1 mov.w r0, @r1 mov.l #bbrb, r1 mov.w r0, @r1 ; (2) initialize brcr to 0. mov.l #brcr, r1 mov.w r0, @r1 ; (3) dummy read brcr. mov.w @r1, r0 ; (4) read stbcr2, then set mstp5 bit in the read data to 1 and write it back mov.l #stbcr2, r1 mov.b @r1, r0 or #h'1, r0 mov.b r0, @r1 ; (5) twice dummy read stbcr2. mov.b @r1, r0 mov.b @r1, r0 ; canceling user break controller stopped state ; (6) read stbcr2, then clear mstp5 bit in the read data to 0 and write it back mov.l #stbcr2, r1 mov.b @r1, r0 and #h'fe, r0 mov.b r0, @r1 ; (7) twice dummy read stbcr2. mov.b @r1, r0 mov.b @r1, r0
20. user break controller (ubc) rev.4.00 oct. 10, 2008 page 822 of 1122 rej09b0370-0400
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 823 of 1122 rej09b0370-0400 section 21 high-performan ce user debug interface (h-udi) 21.1 overview 21.1.1 features the high-performance user debug in terface (h-udi) is a serial inpu t/output interface supporting a subset of the jtag, ieee 1149.1, ieee sta ndard test access port and boundary-scan architecture. this lsi h-udi support boundary-scan, and is used for emulator connection. the functions of this interf ace should not be used when using an emulator. refer to the emulator manual for the method of connecting the emulat or. the h-udi uses six pins (tck, tms, tdi, tdo, trst , and asebrk /brkack). in this lsi, six dedicated emulator pins have been added (audsync, audck, and audata3 to audata0). the pin functions and serial transfer protocol conform to the jtag specifications. 21.1.2 block diagram figure 21.1 shows a block diagram of the h- udi. the tap (test access port) controller and control registers are reset independently of the chip reset pin by driving the trst pin low or setting tms to 1 and applying tck for at least five clock cycles. the other circuits are reset and initialized in an ordinary reset. the h-udi circ uit has six internal registers: sdbpr, sdbsr, sdir, sdint, sddrh, and sddrl (these last two together designated sddr). the sdbpr register supports the jtag bypass mode, sdbsr is a shift register forming a jtag boundary scan, sdir is the command register, sddr is the data register, and sdint is the h-udi interrupt register. sdir can be accessed dir ectly from the tdi and tdo pins.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 824 of 1122 rej09b0370-0400 sdir sddrh sddrl sdbpr mux tck asebrk /brkack tms trst tdi tdo audsync audck audata3?0 sdint interrupt/reset etc. tap controller break control decoder shift re g ister sdbsr peripheral module bus trace control figure 21.1 block di agram of h-udi circuit
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 825 of 1122 rej09b0370-0400 21.1.3 pin configuration table 21.1 shows the h-udi pin configuration. table 21.1 h-udi pins pin name abbreviation i/o function when not used clock pin tck input same as the jtag serial clock input pin. data is transfe rred from data input pin tdi to the h-udi circuit, and data is read from data output pin tdo, in synchronization with this signal. open * 1 mode pin tms input the mode select input pin. changing this signal in synchronization with tck determines the meaning of the data input from tdi. the protocol conforms to the jtag (ieee std 1149.1) specification. open * 1 reset pin trst input the input pin that resets the h-udi. this signal is received asynchronously with respect to tck, and effects a reset of the jtag interface circuit when low. trst must be driven low for a certain period when powering on, regardless of whether or not jtag is used. this differs from the ieee specification. * 2, * 3 data input pin tdi input the data input pin. data is sent to the h-udi circuit by changing this signal in synchronization with tck. open * 1 data output pin tdo output the data output pin. data is sent to the h-udi circuit by reading this signal in synchronization with tck. open asebrk / brkack input/ output dedicated emulator pin open * 1 emulator pin audsync audck audata3? audata0 output dedicated emulator pin open notes: 1. pulled up inside the chip. when designi ng a board that allows use of an emulator, or when using interrupts and resets via the h- udi, there is no problem in connecting a pullup resistance externally. 2. when designing a board that enables the use of an emulator, or when using interrupts and resets via the h-udi, drive trst low for a period overlapping reset at power-on, and also provide for control by trst alone.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 826 of 1122 rej09b0370-0400 3. fixed to the ground or connected to the same signal line as reset , or to a signal line that behaves in the same way. however, there is a problem when this pin is fixed to the ground. trst is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. the size of this current is determined by the rating of the pull-up resistor. although th is current has no effect on the chip's operation, unnecessary current will be dissipated. the maximum frequency of tck (tms, tdi, tdo) is 20 mhz. make the tck or this lsi cpg setting so that the tck frequency is lower than that of this lsi ' s peripheral module clock. 21.1.4 register configuration table 21.2 shows the h-udi regist ers. except for sdbp r and sdbsr, these registers are mapped in the control register space and can be referenced by the cpu. table 21.2 h-udi registers cpu side h-udi side name abbre- viation r/w p4 address area 7 address access size initial value * 1 r/w access size initial value * 1 instruction register sdir r h'fff00000 h'1ff00000 16 h'ffff r/w 32 h'fffffffd (fixed value * 2 ) data register h sddr/ sddrh r/w h'fff00008 h'1ff00008 32/16 unde- fined ? ? ? data register l sddrl r/w h'fff0000a h'1ff0000a 16 unde- fined ? ? ? bypass register sdbpr ? ? ? ? unde- fined r/w 1 ? interrupt factor register sdint r/w h'fff00014 h'1ff00014 16 h'0000 w * 3 32 h'00000000 boundary scan register sdbsr ? ? ? ? unde- fined r/w ? undefined notes: 1. initialized when the trst pin goes low or when the tap is in the test-logic-reset state. 2. the value read from h-udi is fixed (h'fffffffd). 3. 1 can be written to the lsb using the h-udi interrupt command.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 827 of 1122 rej09b0370-0400 21.2 register descriptions 21.2.1 instruction register (sdir) the instruction register (sdir) is a 16-bit register that can only be read by the cpu. in the initial state, bypass mode is set. the value (command) is set from the serial input pin (tdi). sdir is initialized by the trst pin or in the tap test-logic-reset stat e. when this register is written to from the h-udi, writing is possible regardless of the cpu mode. operation is undefined if a reserved command is set in this register. bit: 15 14 13 12 11 10 9 8 ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bits 15 to 8?test instruction bits (ti7?ti0) bit 15: ti7 bit 14: ti6 bit 13: ti5 bit 12: ti4 bit 11: ti3 bit 10: ti2 bit 9: ti1 bit 8: ti0 description 0 0 0 0 0 0 0 0 extest 0 0 0 0 0 1 0 0 sample/preload 0 1 1 0 ? ? ? ? h-udi reset negate 0 1 1 1 ? ? ? ? h-udi reset assert 1 0 1 ? ? ? ? ? h-udi interrupt 1 1 1 1 1 1 1 1 bypass mode (initial value) other than above reserved bits 7 to 0?reserved: these bits are always read as 1, and should only be written with 1.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 828 of 1122 rej09b0370-0400 21.2.2 data register (sddr) the data register (sddr) is a 32-bit register, comprising the two 16-bit registers sddrh and sddrl, that can be read and written to by the cpu. the value in this register is initialized by trst , but not by a cpu reset. bit: 31 30 29 28 27 26 25 24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined bits 31 to 0?dr data: these bits store the sddr value. 21.2.3 bypass register (sdbpr) the bypass register (sdbpr) is a one-bit register that cannot be accessed by the cpu. when bypass mode is set in sdir, sdbpr is connected between the tdi pin and tdo pin of the h-udi.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 829 of 1122 rej09b0370-0400 21.2.4 interrupt fact or register (sdint) the interrupt factor register (sdint) is a 16-bit re gister that can be read /written from the cpu. when a (h-udi interrupt) command is set in the sdir (update-ir) via the h-udi pin, the intreq bit is set to 1. while sdir has the ?h-udi interrupt? command, the sdint register is connected between h-udi pins tdi and tdo, and can be read as a 32-bit register. the high 16 bits are 0 and the low 16 bits are sdint. only 0 can be written to the intreq bit from the cpu. while this bit is 1, the interrupt request continues to be generated, and must therefore be cleared to 0 by the interrupt handler. this register is initialized by trst or when in the test logic reset state. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? intreq initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 15 to 1? reserved: these bits always read as 0, and should only be written with 0. bit 0?interrupt request bit (intreq): shows the existence of an interrupt request from the ?h-udi interrupt? command. the interrupt request ca n be cleared by writing 0 to this bit from the cpu. when 1 is written to this bit, the existing value is retained. 21.2.5 boundary scan register (sdbsr) the boundary scan register (sdbsr) is a shift regi ster that is placed on the pads to control the chip ' s i/o pins. this register can perform a boundar y scan test equivalent to the jtag (ieee std 1149.1) standard using extest, sample, an d preload commands. table 21.3 shows the relationship between this lsi pins and the boundary scan register.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 830 of 1122 rej09b0370-0400 table 21.3 structure of boundary scan register no. pin name type to tdo 418 cs0 out 417 cs0 ctl 416 cs1 out 415 cs1 ctl 414 cs4 out 413 cs4 ctl 412 cs5 out 411 cs5 ctl 410 cs6 out 409 cs6 ctl 408 bs out 407 bs ctl 406 we0 / reg out 405 we0 / reg ctl 404 we1 out 403 we1 ctl 402 d0 out 401 d0 ctl 400 d0 in 399 d1 out 398 d1 ctl 397 d1 in 396 d2 out 395 d2 ctl 394 d2 in 393 d3 out 392 d3 ctl 391 d3 in 390 d4 out 389 d4 ctl
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 831 of 1122 rej09b0370-0400 no. pin name type 388 d4 in 387 d5 out 386 d5 ctl 385 d5 in 384 d6 out 383 d6 ctl 382 d6 in 381 d7 out 380 d7 ctl 379 d7 in 378 d8 out 377 d8 ctl 376 d8 in 375 d9 out 374 d9 ctl 373 d9 in 372 d10 out 371 d10 ctl 370 d10 in 369 d11 out 368 d11 ctl 367 d11 in 366 d12 out 365 d12 ctl 364 d12 in 363 d13 out 362 d13 ctl 361 d13 in 360 d14 out 359 d14 ctl 358 d14 in 357 d15 out 356 d15 ctl
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 832 of 1122 rej09b0370-0400 no. pin name type 355 d15 in 354 cas0 /dqm0 out 353 cas0 /dqm0 ctl 352 cas1 /dqm1 out 351 cas1 /dqm1 ctl 350 rd/ wr out 349 rd/ wr ctl 348 rd / cass / frame out 347 rd / cass / frame ctl 346 cke out 345 cke ctl 344 ras out 343 ras ctl 342 cs2 out 341 cs2 ctl 340 cs3 out 339 cs3 ctl 338 a0 out 337 a0 ctl 336 a1 out 335 a1 ctl 334 a2 out 333 a2 ctl 332 a3 out 331 a3 ctl 330 a4 out 329 a4 ctl 328 a5 out 327 a5 ctl 326 a6 out 325 a6 ctl 324 a7 out 323 a7 ctl
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 833 of 1122 rej09b0370-0400 no. pin name type 322 a8 out 321 a8 ctl 320 a9 out 319 a9 ctl 318 a10 out 317 a10 ctl 316 a11 out 315 a11 ctl 314 a12 out 313 a12 ctl 312 a13 out 311 a13 ctl 310 a14 out 309 a14 ctl 308 a15 out 307 a15 ctl 306 a16 out 305 a16 ctl 304 a17 out 303 a17 ctl 302 cas2 /dqm2 out 301 cas2 /dqm2 ctl 300 cas3 /dqm3 out 299 cas3 /dqm3 ctl 298 d16 out 297 d16 ctl 296 d16 in 295 d17 out 294 d17 ctl 293 d17 in 292 d18 out 291 d18 ctl 290 d18 in
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 834 of 1122 rej09b0370-0400 no. pin name type 289 d19 out 288 d19 ctl 287 d19 in 286 d20 out 285 d20 ctl 284 d20 in 283 d21 out 282 d21 ctl 281 d21 in 280 d22 out 279 d22 ctl 278 d22 in 277 d23 out 276 d23 ctl 275 d23 in 274 d24 out 273 d24 ctl 272 d24 in 271 d25 out 270 d25 ctl 269 d25 in 268 d26 out 267 d26 ctl 266 d26 in 265 d27 out 264 d27 ctl 263 d27 in 262 d28 out 261 d28 ctl 260 d28 in 259 d29 out 258 d29 ctl 257 d29 in
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 835 of 1122 rej09b0370-0400 no. pin name type 256 d30 out 255 d30 ctl 254 d30 in 253 d31 out 252 d31 ctl 251 d31 in 250 a18 out 249 a18 ctl 248 a19 out 247 a19 ctl 246 a20 out 245 a20 ctl 244 a21 out 243 a21 ctl 242 a22 out 241 a22 ctl 240 a23 out 239 a23 ctl 238 a24 out 237 a24 ctl 236 a25 out 235 a25 ctl 234 we2 / iciord out 233 we2 / iciord ctl 232 we3 / iciowr out 231 we3 / iciowr ctl 230 sleep in 229 pcignt4 out 228 pcignt4 ctl 227 pcignt3 out 226 pcignt3 ctl 225 pcignt2 out 224 pcignt2 ctl
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 836 of 1122 rej09b0370-0400 no. pin name type 223 pcireq4 out 222 pcireq4 ctl 221 pcireq4 in 220 pcireq3 /md10 out 219 pcireq3 /md10 ctl 218 pcireq3 /md10 in 217 pcireq2 /md9 out 216 pcireq2 /md9 ctl 215 pcireq2 /md9 in 214 idsel in 213 inta out 212 inta ctl 211 pcirst out 210 pcirst ctl 209 pciclk in 208 pcignt1 / reqout out 207 pcignt1 / reqout ctl 206 pcireq1 / gntin out 205 pcireq1 / gntin ctl 204 pcireq1 / gntin in 203 serr out 202 serr ctl 201 serr in 200 ad31 out 199 ad31 ctl 198 ad31 in 197 ad30 out 196 ad30 ctl 195 ad30 in 194 ad29 out 193 ad29 ctl 192 ad29 in 191 ad28 out
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 837 of 1122 rej09b0370-0400 no. pin name type 190 ad28 ctl 189 ad28 in 188 ad27 out 187 ad27 ctl 186 ad27 in 185 ad26 out 184 ad26 ctl 183 ad26 in 182 ad25 out 181 ad25 ctl 180 ad25 in 179 ad24 out 178 ad24 ctl 177 ad24 in 176 c/ be3 out 175 c/ be3 ctl 174 c/ be3 in 173 ad23 out 172 ad23 ctl 171 ad23 in 170 ad22 out 169 ad22 ctl 168 ad22 in 167 ad21 out 166 ad21 ctl 165 ad21 in 164 ad20 out 163 ad20 ctl 162 ad20 in 161 ad19 out 160 ad19 ctl 159 ad19 in 158 ad18 out
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 838 of 1122 rej09b0370-0400 no. pin name type 157 ad18 ctl 156 ad18 in 155 ad17 out 154 ad17 ctl 153 ad17 in 152 ad16 out 151 ad16 ctl 150 ad16 in 149 c/ be2 out 148 c/ be2 ctl 147 c/ be2 in 146 pciframe out 145 pciframe ctl 144 pciframe in 143 irdy out 142 irdy ctl 141 irdy in 140 trdy out 139 trdy ctl 138 trdy in 137 devsel out 136 devsel ctl 135 devsel in 134 pcistop out 133 pcistop ctl 132 pcistop in 131 pcilock out 130 pcilock ctl 129 pcilock in 128 perr out 127 perr ctl 126 perr in 125 par out
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 839 of 1122 rej09b0370-0400 no. pin name type 124 par ctl 123 par in 122 c/ be1 out 121 c/ be1 ctl 120 c/ be1 in 119 ad15 out 118 ad15 ctl 117 ad15 in 116 ad14 out 115 ad14 ctl 114 ad14 in 113 ad13 out 112 ad13 ctl 111 ad13 in 110 ad12 out 109 ad12 ctl 108 ad12 in 107 ad11 out 106 ad11 ctl 105 ad11 in 104 ad10 out 103 ad10 ctl 102 ad10 in 101 ad9 out 100 ad9 ctl 99 ad9 in 98 ad8 out 97 ad8 ctl 96 ad8 in 95 c/ be0 out 94 c/ be0 ctl 93 c/ be0 in 92 ad7 out
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 840 of 1122 rej09b0370-0400 no. pin name type 91 ad7 ctl 90 ad7 in 89 ad6 out 88 ad6 ctl 87 ad6 in 86 ad5 out 85 ad5 ctl 84 ad5 in 83 ad4 out 82 ad4 ctl 81 ad4 in 80 ad3 out 79 ad3 ctl 78 ad3 in 77 ad2 out 76 ad2 ctl 75 ad2 in 74 ad1 out 73 ad1 ctl 72 ad1 in 71 ad0 out 70 ad0 ctl 69 ad0 in 68 irl0 in 67 irl1 in 66 irl2 in 65 irl3 in 64 nmi in 63 back / bsreq out 62 back / bsreq ctl 61 breq / bsack in 60 md6/ iois16 in 59 rdy in
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 841 of 1122 rej09b0370-0400 no. pin name type 58 txd out 57 txd ctl 56 txd in 55 md2/rxd2 in 54 rxd in 53 tclk out 52 tclk ctl 51 tclk in 50 rts2 /md8 out 49 rts2 /md8 ctl 48 rts2 /md8 in 47 sck out 46 sck ctl 45 sck in 44 md1/txd2 out 43 md1/txd2 ctl 42 md1/txd2 in 41 md0/sck2 out 40 md0/sck2 ctl 39 md0/sck2 in 38 md7/ cts2 out 37 md7/ cts2 ctl 36 md7/ cts2 in 35 audsync out 34 audsync ctl 33 audck out 32 audck ctl 31 audata0 out 30 audata0 ctl 29 audata1 out 28 audata1 ctl 27 audata2 out 26 audata2 ctl
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 842 of 1122 rej09b0370-0400 no. pin name type 25 audata3 out 24 audata3 ctl 23 md3/ ce2a out 22 md3/ ce2a ctl 21 md3/ ce2a in 20 md4/ ce2b out 19 md4/ ce2b ctl 18 md4/ ce2b in 17 md5 out 16 md5 ctl 15 md5 in 14 dack0 out 13 dack0 ctl 12 dack1 out 11 dack1 ctl 10 drak0 out 9 drak0 ctl 8 drak1 out 7 drak1 ctl 6 status0 out 5 status0 ctl 4 status1 out 3 status1 ctl 2 dreq0 in 1 dreq1 in from tdi note: ctl is a low-active signal. the relevant pin is driven to the out state when ctl is set low.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 843 of 1122 rej09b0370-0400 21.3 operation 21.3.1 tap control figure 21.2 shows the internal states of the tap control circuit. thes e conform to the state transitions specified by jtag. ? the transition condition is the tms value at the rising edge of tck. ? the tdi value is sampled at the rising edge of tck, and shifted at the falling edge. ? the tdo value changes at the falling edge of tck. when not in the shift-dr or shift-ir state, tdo is in the high-impedance state. ? in a transition to trst = 0, a transition is made to the test-logic-reset state asynchronously with respect to tck. 1 0 0 0 run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr test-lo g ic-reset 0 11 1 0 0 1 0 1 1 1 1 0 0 0 0 select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 0 1 0 1 1 1 1 0 0 figure 21.2 tap control state transition diagram
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 844 of 1122 rej09b0370-0400 21.3.2 h-udi reset a power-on reset is effected by an sdir command . a reset is effected by sending a h-udi reset assert command, and then sending a h-udi reset negate command, from the h-udi pin (see figure 21.3). the interval required between the h-udi reset assert command and the h-udi reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. h-udi pin chip internal reset cpu state h-udi reset assert normal h-udi reset ne g ate reset processin g reset figure 21.3 h-udi reset 21.3.3 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command value in sdir from the h-udi. the h-udi interrupt is of general exception /interrupt operation type, with a branch to an address based on vbr and return effected by me ans of an rte instruction. the exception code stored in control register intevt in this case is h'600. the priority of the h-udi interrupt can be controlled with bits 3 to 0 of control register iprc. the h-udi interrupt request signal is asserted when, after the command is set (update-ir), the intreq bit of the sdint register is set to 1. the interrupt request signal is not negated until 0 is written to the intreq bit by software, and there is therefore no risk of the interrupt request being unexpectedly missed. while the h- udi interrupt command is set in sdir, the sdint register is connected between tdi and tdo.
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 845 of 1122 rej09b0370-0400 21.3.4 boundary scan (extes t, sample/preload, bypass) in this lsi, setting a command from the h- udi in sdir can place th e h-udi pins in the boundary scan mode. however, the following limitations apply. 1. clock-related signals (extal, extal2, xtal, xtal2, and ckio) are excluded from the boundary scan. 2. reset-related signals ( reset , mreset , and ca) are excluded from the boundary scan. 3. h-udi signals (tck, tdi, tdo, tms, and trst ) are excluded from the boundary scan. 4. with extest, assert the mreset pin (low), negate the reset pin (high), and assert the ca pin (high). with sample/preload, assert the ca pin (high). 5. when executing a boundary scan (extest, sample/preload, and bypass), supply a clock signal to the extal pin. the allowed range of input clock frequencies is from 1 to 33.3 mhz. execute the boundary scan after t osc1 (the power-on oscillation-stabilization time) has elapsed. the clock signal need not be supplied to the extal pin after t osc1 has elapsed. for details on t osc1 (the power-on oscillation-stabilizat ion time), see section 23, electrical characteristics. 21.4 usage notes 1. sdir command once an sdir command is set, it does not change until another command is written from the h-udi, unless initialized by asserting trst or the tap is set in the test-logic-reset state. 2. sdir commands in sleep mode sleep mode is cleared by an h-udi interrupt or h-udi reset, and these exception requests are accepted in this mode. in standby mode, neithe r an h-udi interrupt nor an h-udi reset is accepted. 3. in standby mode, the h-udi function cannot be used. furthermore, tck must be retained at a high level when entering the standby mode in order to retain the tap state before and after standby mode. 4. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when an emulator is used. 5. when the sh7751 is in bypass mode, the bypass register (sdbpr) is not fixed in the capture- dr state. (it is cleared to 0 in the sh7751r.)
21. high-performance user debug interface (h-udi) rev.4.00 oct. 10, 2008 page 846 of 1122 rej09b0370-0400
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 847 of 1122 rej09b0370-0400 section 22 pci controller (pcic) 22.1 overview the pci controller (pcic) controls the pci bus and transfers data between memory connected to the external bus and a pci device connected to th e pci bus. the ability for pci devices to be connected directly not only facilitates the design of systems using pci buses but also enables systems to be more comp act and capable of high -speed data transfer. 22.1.1 features the pcic has the following features: ? supports a subset of pci version 2.1. ? compatible with pci bus operating speeds of 33 mhz/66 mhz. ? compatible with 32-bit pci bus. ? up to four pci master devices running at 33 mhz or one pci master device at 66 mhz can be connected. ? arbitration control is available as a pci host function. ? can operate as master or target. ? when operating as master, pio an d dma transfer are available. ? four dma transfer channels. ? six 32-bit x 16 longword internal fifo (one for target reading, one for target writing, and four for dma transfer). ? asynchronous operation of bsc bus clock and pci bus clock available, and ckio can be used as pci bus clock. ? sram, dram, sdram, and mpx* can be used as external memory for pci bus data transfers. ? 32-bit or 16-bit memory data bus for data transfers with pci bus (32-bit bus when connected to sdram). ? support for big endian and little endian local bu s (pci bus operates with little endian, while internal bus for peripheral modul es operates with big endian). note: * mpx is only supported by the sh7751r and is not supported by the sh7751.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 848 of 1122 rej09b0370-0400 22.1.2 block diagram figure 22.1 is a block diagram of the pcic. interrupt control local register pci bus pci configuration register pci bus interface internal peripheral module bus interface local register fifo 32b 2 sides 6 data transfer control local register bus request acknowledge local register pcic bus controller pci clock 33/66 mhz (pciclk) local bus feedback input clock from ckio local bus clock (bck) cycle: bcyc interrupts pcic module internal peripheral module bus (peripheral bus) figure 22.1 pcic block diagram
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 849 of 1122 rej09b0370-0400 22.1.3 pin configuration table 22.1 shows the configuration of i/o pins of the pcic. table 22.1 pin configuration i/o status in operating modes host non-host no. pin name pci standard signal name function i/o type pull-up resistor * 1 master target master target remarks 1 pciclk clk pci input clock (33 mhz/66 mhz) in i i i i 2 pcirst ? reset output out o o ? ? 3 ad31 to ad0 ad[31:0] address/data t/s i/o i/o i/o i/o low level output at reset 4 c/ be3 to c/ be0 c/ be [3:0] command/byte enable t/s o i o i low level output at reset 5 par par parity t/s i/o i/o i/o i/o low level output at reset 6 pciframe frame bus cycle s/t/s yes o i o i 7 irdy irdy initiator ready s/t/s yes o i o i 8 trdy trdy target ready s/t/s yes i o i o 9 pcistop stop transaction stop s/t/s yes i o i o 10 pcilock lock exclusive access control s/t/s yes o i o i 11 devsel devsel device select s/t/s yes i o i o req1 bus request (host function) t/s yes i i ? 12 pcireq1 / gntin gnt bus grant t/s yes ? ? i ? gnt1 bus grant (host function) t/s no o o ? 13 pcignt1 / reqout req bus request t/s no ? ? o ? 14 perr perr parity error s/t/s yes i/o o i/o o 15 serr serr system error o/d yes o o o o 16 inta inta interrupt (async) o/d yes ? ? o o
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 850 of 1122 rej09b0370-0400 i/o status in operating modes host non-host no. pin name pci standard signal name function i/o type pull-up resistor * 1 master target master target remarks bus request (host function) t/s yes i i ? ? 17 pcireq2 / md9 req2 pci clock switch (bclk/pciclk) in i i i i * 2 bus request (host function) t/s yes i i ? ? 18 pcireq3 / md10 req3 host bridge function on/off in i i i i * 2 19 pcireq4 req4 bus request (host function) t/s yes i i ? ? 20 pcignt4 to pcignt2 gnt4 to gnt2 bus grant (host function) t/s o o ? ? 21 idsel idsel config device select in ? ? i i * 3 legend: in: input out: output s/t/s: sustained try state o/d: open drain t/s: try state notes: 1. terminal provided with a pull-up resistor. 2. the values of external pins are sa mpled in a power-on reset by means of the reset pin. 3. pull down this pin to low level when idsel is not in use. if a configuration access to an external pci device occurs while idsel is high level, the pcic itself may respond. 22.1.4 register configuration the pcic has the pci configuration registers and pci control registers shown in table 22.2, 22.3 and 22.4. also, the pci bus addr ess space is allocated to the in ternal bus for the peripheral modules, making it possible to access the pci bus by program io (pio). not only do these registers control the pci bus but also enable hi gh-speed data transfers between the pci device and memory on the sh-4 external data bus (hereinafter, the sh-4 external data bus is referred to as the local bus to distinguish it from the pci bus).
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 851 of 1122 rej09b0370-0400 table 22.2 list of pci configuration registers name abbreviation pci r/w pp-bus r/w initial value pci configu- ration address p4 address area 7 address access size pci configuration register 0 pciconf0 r r * 1 h'00 h'fe200000 h'1e200000 32 pci configuration register 1 pciconf1 r/w r/w h'02900080 h'04 h'fe200004 h'1e200004 32 pci configuration register 2 pciconf2 r r/w[31:8] r (other) h'xxxxxx * 2 h'08 h'fe200008 h'1e200008 32 pci configuration register 3 pciconf3 r/w[15:8] r (other) r/w[15:8] r (other) h'00000000 h'0c h'fe20000c h'1e20000c 32 pci configuration register 4 pciconf4 r/w r/w h'00000001 h'10 h'fe200010 h'1e200010 32 pci configuration register 5 pciconf5 r/w r/w h'00000000 h'14 h'fe200014 h'1e200014 32 pci configuration register 6 pciconf6 r/w r/w h'00000000 h'18 h'fe200018 h'1e200018 32 pci configuration register 7 pciconf7 r r h'00000000 h'1c h'fe20001c h'1e20001c 32 pci configuration register 8 pciconf8 r r h'00000000 h'20 h'fe200020 h'1e200020 32 pci configuration register 9 pciconf9 r r h'00000000 h'24 h'fe200024 h'1e200024 32 pci configuration register 10 pciconf10 r r h'00000000 h'28 h'fe200028 h'1e200028 32 pci configuration register 11 pciconf11 r r/w h'xxxxxxxx h'2c h'fe20002c h'1e20002c 32 pci configuration register 12 pciconf12 r r h'00000000 h'30 h'fe200030 h'1e200030 32 pci configuration register 13 pciconf13 r r h'00000040 h'34 h'fe200034 h'1e200034 32 pci configuration register 14 pciconf14 r r h'00000000 h'38 h'fe200038 h'1e200038 32 pci configuration register 15 pciconf15 r/w[7:0] r (other) r/w[7:0] r (other) h'00000100 h'3c h'fe20003c h'1e20003c 32 pci configuration register 16 pciconf16 r r r/w[18:16] r (other) h'00010001 h'40 h'fe200040 h'1e200040 32 pci configuration register 17 pciconf17 r/w[1:0] r (other) r/w[1:0] r (other) h'00000000 h'44 h'fe200044 h'1e200044 32 reserved ? r r h'00000000 h'48 to h'fc h'fe200048 to h'fe2000fc h'1e200048 to h'1e2000fc 32 legend: x: undefined value notes: 1. varies with the logic versions of the chip. 2. h'35051054 for the sh7751; h'350e1054 for the sh7751r.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 852 of 1122 rej09b0370-0400 table 22.3 pci configuration register configuration pci configuration register pci configu- ration address p4 address area 7 address 31 to 24 23 to 16 15 to 8 7 to 0 pci r/w pp-bus r/w h'00 h'fe200000 h'1e200000 device id device id vendor id vendor id r r h'04 h'fe200004 h'1e200004 status stat us command command r/w r/w h'08 h'fe200008 h'1e200008 class code class code class code revision id r r/w[31:8] r (other) h'0c h'fe20000c h'1e20000c bist header type pci latency timer cache line size r/w[15:8] r (other) r/w[15:8] r (other) h'10 h'fe200010 h'1e200010 base address (i/o area) base address (i/o area) base address (i/o area) base address (i/o area) r/w r/w h'14 h'fe200014 h'1e200014 base address (local address area 0) base address (local address area 0) base address (local address area 0) base address (local address area 0) r/w r/w h'18 h'fe200018 h'1e200018 base address (local address area 1) base address (local address area 1) base address (local address area 1) base address (local address area 1) r/w r/w h'1c h'fe20001c h'1e20001c reserved reserved reserved reserved r r h'20 h'fe200020 h'1e200020 reserved reserved reserved reserved r r h'24 h'fe200024 h'1e200024 reserved reserved reserved reserved r r h'28 h'fe200028 h'1e200028 reserved reserved reserved reserved r r h'2c h'fe20002c h'1e20002c subsystem id subsystem id subsystem vendor id subsystem vendor id r r/w h'30 h'fe200030 h'1e200030 reserved reserved reserved reserved r r h'34 h'fe200034 h'1e200034 reserved reserved reserved extended function pointer r r h'38 h'fe200038 h'1e200038 reserved reserved reserved reserved r r h'3c h'fe20003c h'1e20003c max_lat min_gnt interrupt pin interrupt line r/w[7:0] r (other) r/w[7:0] r (other) h'40 h'fe200040 h'1e200040 power management related power management related power management related power management related r r/w[18:16] r (other) h'44 h'fe200044 h'1e200044 power management related power management related power management related power management related r/w[1:0] r (other) r/w[1:0] r (other) h'48 to h'0fc h'fe200048 to h'fe2000fc h'1e200048 to h'1e2000fc reserved reserved reserved reserved r r
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 853 of 1122 rej09b0370-0400 table 22.4 list of pcic local registers name abbre- viation pci r/w pp-bus r/w initial value pci i/o address (sh7751/ sh7751r) p4 address area 7 address access size pci control register pcicr r r/w h'000000 * 0 h'100/ h'00 h'fe200100 h'1e200100 32 local space register 0 for pci pcilsro r r/w h'00000000 h'104/ h'04 h'fe200104 h'1e200104 32 local space register 1 for pci pcilsr1 r r/w h'00000000 h'108/ h'08 h'fe200108 h'1e200108 32 local address register 0 for pci pcilar0 r/w r/w h'00000000 h'10c/ h'0c h'fe20010c h'1e20010c 32 local address register 1 for pci pcilar1 r/w r/w h'00000000 h'110/ h'10 h'fe200110 h'1e210110 32 pci interrupt register pciint r/w r/w h'00000000 h'114/ h'14 h'fe200114 h'1e200114 32 pci interrupt mask register pciintm r/w r/w h'00000000 h'118/ h'18 h'fe200118 h'1e200118 32 error address data register for pci pcialr r r h'xxxxxxxx h'11c/ h'1c h'fe20011c h'1e20011c 32 error command data register for pci pciclr r r h'0000000x h'120/ h'20 h'fe200120 h'1e200120 32 reserved ? ? ? h'00000000 h'124 to h'12c/ h'24 to h'2c h'fe200124 to h'fe20012c h'1e200124 to h'1e20012c 32 pci arbiter interrupt register pciaint r/w r/w h'00000000 h'130/ h'30 h'fe200130 h'1e200130 32 pci arbiter interrupt mask register pciaintm r/w r/w h'00000000 h'134/ h'34 h'fe200134 h'1e200134 32 error bus master data register for pci pcibmlr r r h'00000000 h'138/ h'38 h'fe200138 h'1e200138 32 reserved ? ? ? h'00000000 h'13c/ h'3c h'fe20013c h'1e20013c 32 dma transfer arbitration register for pci pcidmabt r/w r/w h'00000000 h'140/ h'40 h'fe200140 h'1e200140 32 reserved ? ? ? h'00000000 h'144 to h'17c/ h'44 to h'7c h'fe200144 to h'fe20017c h'1e200144 to h'1e20017c 32 dma transfer pci address register 0 for pci pcidpa0 r/w r/w h'00000000 h'180/ h'80 h'fe200180 h'1e200180 32 dma transfer local bus starting address regsiter 0 for pci pcidla0 r/w r/w h'00000000 h'184/ h'84 h'fe200184 h'1e200184 32
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 854 of 1122 rej09b0370-0400 name abbre- viation pci r/w pp-bus r/w initial value pci i/o address (sh7751/ sh7751r) p4 address area 7 address access size dma transfer count register 0 for pci pcidtc0 r/w r/w h'00000000 h'188/ h'88 h'fe200188 h'1e200188 32 dma control register 0 for pci pcidcr0 r/w r/w h'00000000 h'18c/ h'8c h'fe20018c h'1e20018c 32 dmapci address register 1 for pci pcidpa1 r/w r/w h'00000000 h'190/ h'90 h'fe200190 h'1e200190 32 dma transfer local bus starting address register 1 for pci pcidla1 r/w r/w h'00000000 h'194/ h'94 h'fe200194 h'1e200194 32 dma transfer count register 1 for pci pcidtc1 r/w r/w h'00000000 h'198/ h'98 h'fe200198 h'1e200198 32 dma control register 1 for pci pcidcr1 r/w r/w h'00000000 h'19c/ h'9c h'fe20019c h'1e20019c 32 dma transfer pci address register 2 for pci pcidpa2 r/w r/w h'00000000 h'1a0/ h'a0 h'fe2001a0 h'1e2001a0 32 dma transfer local bus starting address register 2 for pci pcidla2 r/w r/w h'00000000 h'1a4/ h'a4 h'fe2001a4 h'1e2001a4 32 dma transfer count register 2 for pci pcidtc2 r/w r/w h'00000000 h'1a8/ h'a8 h'fe2001a8 h'1e2001a8 32 dma control register 2 for pci pcidcr2 r/w r/w h'00000000 h'1ac/ h'ac h'fe2001ac h'1e2001ac 32 dma transfer pci address register 3 for pci pcidpa3 r/w r/w h'00000000 h'1b0/ h'b0 h'fe2001b0 h'1e2001b0 32 dma transfer local bus starting address register 3 for pci pcidla3 r/w r/w h'00000000 h'1b4/ h'b4 h'fe2001b4 h'1e2001b4 32 dma transfer count register 3 for pci pcidtc3 r/w r/w h'00000000 h'1b8/ h'b8 h'fe2001b8 h'1e2001b8 32 dma control register 3 for pci pcidcr3 r/w r/w h'00000000 h'1bc/ h'bc h'fe2001bc h'1e2001bc 32 pio address register pcipar ? r/w h'80xxxxxx ? h'fe2001c0 h'1e2001c0 32 memory space base register pcimbr ? r/w h'xx000000 ? h'fe2001c4 h'1e2001c4 32 io space base register pciiobr ? r/ w h'xxxx0000 ? h'fe2001c8 h'1e2001c8 32 pci power management interrupt register pcipint ? r/w h'00000000 ? h'fe2001cc h'1e2001cc 32 pci power management interrupt mask register pcipintm ? r/w h'00000000 ? h'fe2001d0 h'1e2001d0 32 pci clock control register pciclkr ? r/w h'00000000 ? h'fe2001d4 h'1e2001d4 32
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 855 of 1122 rej09b0370-0400 name abbre- viation pci r/w pp-bus r/w initial value pci i/o address (sh7751/ sh7751r) p4 address area 7 address access size reserved ? h'00000000 ? h'fe2001d8 to h'fe2001dc h'1e2001d8 to h'1e2001dc 32 pci bus control register 1 pcibcr1 ? r/w h' * 0000000 ? h'fe2001e0 h'1e2001e0 32 pci bus control register 2 pcibcr2 ? r/w h'0000 * ffc ? h'fe2001e4 h'1e2001e4 32 pci wait control register 1 pciwcr1 ? r/w h'77777777 ? h'fe2001e8 h'1e2001e8 32 pci wait control register 2 pciwcr2 ? r/w h'fffeefff ? h'fe2001ec h'1e2001ec 32 pci wait control register 3 pciwcr3 ? r/w h'07777777 ? h'fe2001f0 h'1e2001f0 32 pcic discrete memory control register pcimcr ? r/w h'00000000 ? h'fe2001f4 h'1e2001f4 32 pcic bus control register 3 * 1 pcibcr3 ? r/w h'00000001 ? h'fe2001f8 h'1e2001f8 32 reserved ? h'00000000 h'fe2001fc h'1e2001fc 32 port control register pcipctr ? r/w h'00000000 ? h'fe200200 h'1e200200 32 port data register pcipdtr ? r/w h'00000000 ? h'fe200204 h'1e200204 32 reserved ? h'00000000 ? h'fe200208 to h'fe20021c h'1e200208 to h'1e20021c 32 pio data register pcipdr ? r/w h'xxxxxxxx ? h'fe200220 h'1e200220 32 notes: * the values of some external pins are sampled in a power-on reset by means of the reset pin. x indicates ?undefined.? 1. pcic bus control register 3 is provided on ly in the sh7751r. the relevant areas of the sh7751 are reserved areas.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 856 of 1122 rej09b0370-0400 22.2 pcic register descriptions 22.2.1 pci configuration register 0 (pciconf0) bit: 31 30 29 28 27 26 25 24 devid15 devid14 devid13 devid1 2 devid11 devid10 devid9 devid8 initial value: 0 0 1 1 0 1 0 1 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 devid7 devid6 devid5 devid4 devid3 devid2 devid1 devid0 initial value: 0 0 0 0 0/1 * 1 0/1 * 1/0 * pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 vndid15 vndid14 vndid13 vndid1 2 vndid11 vndid10 vndid9 vndid8 initial value: 0 0 0 1 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 vndid7 vndid6 vndid5 vndid4 vndid3 vndid2 vndid1 vndid0 initial value: 0 1 0 1 0 1 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r note: * these values differ between sh7751 and sh7751r. pci configuration register 0 (pciconf0) is a 32-bit read-only register that includes the device id and vendor id pci configuration registers sti pulated in the pci local bus specifications. the sh7751 id (h'3505) or the sh7751r id (h'350e) is read from bits 31 to 16; the vendor id (h'1054*) is read from bits 15 to 0. all bits of the pciconf0 are fixed in hardware.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 857 of 1122 rej09b0370-0400 bits 31 to 16?devid15 to 0: these bits specify the device id of the sh7751 or sh7751r allocated by the pci device vendor. h'3505 (fixed in hardware) for the sh7751, and h'350e (fixed in hardware) for the sh7751r. bits 15 to 0?dnvid15 to 0: these bits specify the pci device maker (vendor id). (h'1054*: fixed in hardware) note: * the vendor id h'1054 sp ecifies hitachi, ltd., but th e sh7751 and sh7751r are now products of renesas technology corp. for information on these products, contact renesas technology corp. 22.2.2 pci configuration register 1 (pciconf1) bit: 31 30 29 28 27 26 25 24 dpe sse rma rta sta dev1 dev0 dpd initial value: 0 0 0 0 0 0 1 0 pci-r/w: r/wc r/wc r/wc r/wc r/wc r r r/wc pp bus-r/w: r/wc r/wc r/wc r/wc r/wc r r r/wc bit: 23 22 21 20 19 18 17 16 fbbc udf 66m pm ? ? ? ? initial value: 1 0 0 1 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r/w r/w r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? pbbe ser initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r/w pp bus-r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 wcc per vps mwie spc bum mes ios initial value: 1 0 0 0 0 0 0 0 pci-r/w: r/w r/w r r r r/w r/w r/w pp bus-r/w: r/w r/w r r r r/w r/w r/w note: cleared by writing wc: 1. (writing of 0 is ignored.)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 858 of 1122 rej09b0370-0400 pci configuration register 1 (pciconf1) is a 32-b it read/partial-write register that includes the status and command pci configuration registers s tipulated in the pci local bus specifications. the status is read from bits 31 to 16 (status register) in the event of an error on the pci bus. bits 15 to 0 (command register) contain the settings required for initiating transfers on the pci bus. bits 31 to 27, 24, 8 to 6, and 2 to 0 can be written to from both the pp and pci buses. however, bits 31 to 27 and 24 are write-cl ear bits that are cleared when 1 is written to them. bits 22 and 21 can be written to from the pp bus. other bits are fixed in hardware. the pciconf1 register is initialized to h'029 00080 at a power-on reset or software reset. always write to this register before initiating transfers on the pci bus. bit 31?parity error detection status (dpe): indicates the detection of a parity error in read data when the pcic is operating as the master, or a party error in write data when the pcic is operating as a target. bit 31: dpe description 0 no parity error detected by device (initial value) 1 parity error detected by device set this bit regardless of the parity error response bit (bit 6) on the device bit 30?system error output status (sse): indicates the serr assert operation of the pcic. bit 30: sse description 0 device not asserting serr (initial value) 1 device asserting serr (value retained until cleared) bit 29?master abort receive status (rma): indicates the termination of transaction by master abort when the pcic is operating as the master. bit 29: rma description 0 no transaction termination using bus master abort (initial value) 1 detection by bus master of trans action termination by bus master abort however, in the case of a master abort in a special cycle, notify the master devices that are not set
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 859 of 1122 rej09b0370-0400 bit 28?target abort receive status (rta): indicates the termination of transaction by master abort when the pcic is operating as the master. bit 28: rta description 0 no transaction termination using target abort (initial value) 1 detection by bus master of transaction termination by target abort bit 27?target abort execution status (sta): indicates the termination of transaction by target abort when the pcic is operating as the target. bit 27: sta description 0 no transaction termination using target a bort by target device (initial value) 1 transaction termination by target abort by target device. notification by target device bits 26 and 25? devsel timing status (dev1 and 0): these bits indicate the devsel response timing when the pcic is operating as a target. bit 26: dev1 bit 25: dev0 description 0 0 high-speed (not supported) 1 medium speed (initial value) 1 0 low speed (not supported) 1 reserved bit 24?data parity status (dpd): indicates the perr assert operation or the detection of perr when the pcic is operating as the master. this bit is set only when the parity error response bit (bit 6) is 1. bit 24: dpd description 0 data parity not detected (initial value) 1 data parity occurred
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 860 of 1122 rej09b0370-0400 bit 23?high-speed back-to-back status (fbbc): shows whether a high-speed back-to-back transfer to a different target can be accepted when the pcic is operating as a target. bit 23: fbbc description 0 the target does not have a high-speed back-to-back transaction function for use with other targets 1 the target has a high-speed back-to- back transaction function for use with other targets (initial value) bit 22?user defined function system (udf): shows whether user defined functions are supported. bit 22: udf description 0 this device does not support user functions (initial value) 1 this device supports user functions bit 21?66 mhz operating status (66m): shows whether 66 mhz operation is supported. bit 21: 66m description 0 this device supports 33 mhz operation (initial value) 1 this device supports 66 mhz operation bit 20?pci power management (pm): shows whether the pci power management is supported. bit 20: pm description 0 power management not supported 1 power management supported (initial value) bits 19 to 10?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 9?high-speed back-to-back control (pbbe): selects whether or not to allow high-speed back-to-back control with different targets when privileged as the master. bit 9: pbbe description 0 allows high-speed back-to-back control only with same target (initial value) 1 allows high-speed back-to-back control wit h different target (not supported)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 861 of 1122 rej09b0370-0400 bit 8? serr output control (ser): controls the serr output. bit 8: ser description 0 serr output disabled (hi-z) (initial value) 1 serr output enabled bit 7?wait cycle control (wcc): controls the address/data stepping. when wcc=1, address and data are output in master write operations, only address is output in master read operations, and only data is output in target r ead operations, at least in two clocks. bit 7: wcc description 0 disable address/data stepping control 1 enable address/data stepping control (initial value) bit 6?parity error response (per): controls the device response when a parity error is detected or a parity error report is received. perr is asserted only when per = 1. bit 6: per description 0 ignore detected parity errors (initial value) 1 respond to detected parity error bit 5?vga pallet snoop control (vps) bit 5: vps description 0 vga-compatible device (initial value) 1 the device does not respond to palle t register writes (not supported) bit 4?memory write and invalidate control (mwie): controls the issuance of memory and invalidate command when the pcic is operating as the master. bit 4: mwie description 0 the device uses memory write (initial value) 1 the device can execute memory wr ite and invalidate commands (not supported)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 862 of 1122 rej09b0370-0400 bit 3?special cycle control (spc): shows whether special cycles are supported when the pcic is operating as a target. bit 3: spc description 0 ignore special cycle (initial value) 1 monitor special cycl e (not supported) bit 2?pci bus master control (bum): controls the bus master operation. bit 2: bum description 0 disable bus master operation (initial value) 1 enable bus master operation bit 1?memory space control (mes): controls the access to the memory space when the pcic is operating as a target. when this bit is 0, al l memory transfers to the pcic are terminated by master abort. bit 1: mes description 0 disable access to memory space (initial value) 1 enable access to memory space bit 0?i/o space control (ios): controls the access to the i/o space when the pcic is operating as a target. when this bit is 0, all i/ o transfers to the pcic ar e terminated by master abort. bit 0: ios description 0 disable access to i/o space (initial value) 1 enable access to i/o space
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 863 of 1122 rej09b0370-0400 22.2.3 pci configuration register 2 (pciconf2) bit: 31 30 29 28 27 26 25 24 class23 class22 class21 class2 0 class19 class18 class17 class16 initial value: ? ? ? ? ? ? ? 0 pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 class15 class14 class13 class1 2 class11 class10 class9 class8 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 class7 class6 class5 class4 class3 class2 class1 class0 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 revid7 revid6 revid5 revid4 revid3 revid2 revid1 revid0 initial value: * * * * * * * * pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r note: * initial values vary with the logic versions of the chip. the pci configuration register 2 (pciconf2) is a 32-bit read/partial-write register that includes the class code and revision id pci configura tion registers stipulated in the pci local bus specifications. bits 31 to 8 (class code) set the device functions. the chip logic version can be read from bits 7 to 0 (revision id). bits 31 to 8 can be written to from the pp bus. bits 7 to 0 are fixed in hardware. the pciconf2 register class codes are not initiali zed at a reset. they mu st be initialized while cfinit (bit 0) of the pci control registers (pcicr) is cleared.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 864 of 1122 rej09b0370-0400 bits 31 to 24?base class code (class23 to 16): these bits indicate the base class code. for details of setting values, refer to table 22.5. table 22.5 list of class23 to 16 base class codes (class23 to 16) class23 to 16 base class meaning h'00 device designed prior to class code being defined h'01 high-capacity storage controller h'02 network controller h'03 display controller h'04 multimedia device h'05 memory controller h'06 bridge device h'07 simple communication device h'08 basic peripheral device h'09 input device h'0a docking station h'0b processor h'0c serial bus controller h'0d to h'fe reserved h'ff device not categorized in defined class bits 23 to 16?sub class codes (class15 to 8): shows the subclass code. for details, please see appendix d, pin functions of the pci local bus specifications, revision 2.1. bits 15 to 8?register level programming interface (class7 to 0): shows the register level programming interface. for details, please see appe ndix d, pin functions of the pci local bus specifications, revision 2.1. bits 7 to 0?revision id (revid7 to 0): shows the pcic revision. the initial value differs according to the logic ve rsion of the chip.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 865 of 1122 rej09b0370-0400 22.2.4 pci configuration register 3 (pciconf3) bit: 31 30 29 28 27 26 25 24 bist7 bist6 bist5 bist 4 bist3 bist2 bist1 bist0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 head7 head6 head5 head4 head3 head2 head1 head0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 lat7 lat6 lat5 lat4 lat3 lat2 lat1 lat0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 cache7 cache6 cache5 cache4 cache3 cache2 cache1 cache0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci configuration register 3 (pciconf3) is a 32-bit read/partial-write register that includes the bist function, header type, latency timer, and cache line size pci configuration registers stipulated in the pci local bus sp ecification. the bist function is read from bits 31 to 24, the header type from bits 23 to 16, the cache line si ze from bits 7 to 0. the guaranteed time for the pcic to occupy the pci bus when the pcic is master is set in bits 15-8 (latency timer). bits 15 to 8 can be written to. other bits are fixed in hardware. the pciconf3 register is initialized to h'00000000 at a power-on reset and software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 866 of 1122 rej09b0370-0400 bit 31?bist7: bist function support bit 31: bist7 description 0 function not supported (initial value) 1 function supported (not supported) bit 30?bist6: used to control the bist starting. bit 30: bist6 description 0 execution completed (initial value) 1 executing (not supported) bits 29 and 28?bist5 and 4: these bits always return 0 when read. bits 27 to 24?bist3 to 0: bist status on completion of operation. bits 27 to 24: bist3 to 0 description h'0 passed test (initial value) h'1 to h'f test failed (not supported) bit 23?multifunction status (head7): shows whether the device is a multi-function unit or a single-function unit. bit 23: head7 description 0 single-function device (initial value) 1 device has between 2 and 8 functions (not supported) bits 22 to 16?configuration layout type (head6 to 0): these bits indicate the layout type of the configuration register. bits 22 to 16: head6 to 0 description h'00 type 00h layout supported (initial value) h'01 type 01h layout supported (not supported) h'02 to h'3f reserved
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 867 of 1122 rej09b0370-0400 bits 15 to 8?latency timer register (lat7 to 0): these bits specify the latency time of the pci bus when the pcic is operating as the master. bits 7 to 0?cache line size (cache7 to 0): not supported. memory target is set cache- disabled, and sdone and sbo are ignored. 22.2.5 pci configuration register 4 (pciconf4) bit: 31 30 29 28 27 26 25 24 base31 base30 base29 base28 base27 base26 base25 base24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 base23 base22 base21 base20 base19 base18 base17 base16 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w * r/w * r/w * r/w * pp bus-r/w: r/w r/w r/w r/w r/w * r/w * r/w * r/w * bit: 15 14 13 12 11 10 9 8 base15 base14 base13 base12 base11 base10 base9 base8 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * pp bus-r/w: r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * bit: 7 6 5 4 3 2 1 0 base7 base6 base5 base4 base3 base2 ? asi initial value: 0 0 0 0 0 0 0 1 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r note: * these bits are read-only in the sh7751 and can be read from and written to in the sh7751r. pci configuration register 4 (pci conf4) is a 32-bit read/partial- write register that accommodates the i/o-space base address register, which is one of the pci configuration registers that are stipulated in the pci's local-b us specifications. pciconf4 holds the higher-order bits of the
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 868 of 1122 rej09b0370-0400 address used when a device on th e pci bus uses i/o transfer co mmands to access a local register in the pcic. in the sh7751, the 12 higher-order bits (bits 31 to 8) are set; in the sh7751r, the 24 higher-order bits are set. as the i/o space for the pci bus, allocate 1 mbyt e of space for th e sh7751 and 256 bytes of space fo r the sh7751r. in the sh7751, bits 30 to 20 are writable, and bits 19 to 2 and 0 are fixed by the hardware. in the sh7751r, bits 31 to 8 are writable, and bits 7 to 2 and 0 are fixed by the hardware. the pciconf4 register is initialized to h'00000001 at a power-on reset and software reset. always write to this register prior to executing i/o transfers (accessing the local registers in the pcic) to or from the pcic from the pci bus. bits 31 to 8?base address of the i/o space (base 31 to 8): sets the base address of the local registers (i/o space) in the pcic . in the sh7751, bits 19 to 8 are fixed to h'000 in hardware. bits 7 to 2?base address of the i/o space (base 7 to 2): fixed at h'00 in hardware. bit 1?reserved: this bit always returns 0 when read. always write 0 to this bit. bit 0?address space indicator (asi): shows whether the base ad dress specified by this register is an i/o space or memory space. bit 0: asi description 0 memory space 1 i/o space (initial value)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 869 of 1122 rej09b0370-0400 22.2.6 pci configuration register 5 (pciconf5) bit: 31 30 29 28 27 26 25 24 base031 base030 base029 base028 base027 base026 base025 base024 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 base023 base022 base021 base020 base019 base018 base017 base016 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r r r r pp bus-r/w: r/w r/w r/w r/w r r r r bit: 15 14 13 12 11 10 9 8 base015 base014 base013 base012 base011 base010 base09 base08 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 base07 base06 base05 base04 la0pref la0type1 la0type0 la0asi initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci configuration register 5 (pciconf5) is a 32-bit read/partial-write register that accommodates the memory space base address pci c onfiguration register s tipulated in the pci local bus specifications. this register holds the high bits (12 max. in bits 31 to 20) of the address used when a device on the pci bus accesses local memory on the sh local bus using memory transfer commands. allocate at l east the capacity set in the local space register 0 (pcilsr0) as pci bus memory space. bits 19 to 0 are fixed in hardware. of writable bits 31 to 20, those that hold valid values differ according to the value set in pcilsr0.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 870 of 1122 rej09b0370-0400 table 22.6 memory space base address register (base0) pcilsr0 [28:20] register value required address space base0[31:20] valid writable bits b'0_0000_0000 1 mb bits 31 to 20 b'0_0000_0001 2 mb bits 31 to 21 b'0_0000_0011 4 mb bits 31 to 22 : : : b'0_1111_1111 256 mb bits 31 to 28 b'1_1111_1111 512 mb bits 31 to 29 the pciconf5 register is initialized to h'00000000 at a power-on reset and software reset. always write to this register before transferring data to and from the pcic memory from the pci bus. bits 31 to 20?base address of the memory space 0 (base0 31 to 20): these bits specify the base address of the local address sp ace 0 (this lsi external bus space). bits 19 to 4?base address of the memory space 0 (base0 19 to 4): fixed at h'0000 in hardware. bit 3?pre-fetch control (la0pref): shows availability of prefetching of the local address space 0. bit 3: la0pref description 0 prefetch disabled (initial value) 1 prefetch enabled (not supported) bits 2 and 1?la0type1 and 0: in the case of i/o space, can be set as the base address. shows the memory type of the local address space 0. bit 2: la0type1 bit 1: la0type0 description 0 0 base address can be set to 32-bit width, 32-bit space (initial value) 1 base address can be set to 32-bit width, less than 1mb space (not supported) 1 0 base address is 64-bit width (not supported) 1 reserved
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 871 of 1122 rej09b0370-0400 bit 0?la0asi: shows whether the base address specified by this register is an i/o space or memory space. bit 0: la0asi description 0 memory space (initial value) 1 i/o space 22.2.7 pci configuration register 6 (pciconf6) bit: 31 30 29 28 27 26 25 24 base131 base130 base129 base128 base127 base126 base125 base124 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 base123 base122 base121 base120 base119 base118 base117 base116 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r r r r pp bus-r/w: r/w r/w r/w r/w r r r r bit: 15 14 13 12 11 10 9 8 base115 base114 base113 base112 base111 base110 base19 base18 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 base17 base16 base15 base14 la1pref la1type1 la1type0 la1asi initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci configuration register 6 (pciconf6) is a 32-bit read/partial-write register that accommodates the memory space base address pci c onfiguration register s tipulated in the pci local bus specifications. this register contains the mo st significant bits (maximum 12 in bits 31 to
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 872 of 1122 rej09b0370-0400 20) of the address used when a device on the pc i bus accesses local memory on the sh local bus using memory transfer co mmands. minimally, allocate the capacity set in the local space register 1 (pcilsr1) to pci bus memory space. bits 19 to 0 are fixed in hardware. the number of valid bits of those that can be written to (bit 31 to 20) differs according to the value set in pcilsr1. table 22.7 memory space base address register (base1) pcilsr1 [28:20] register value required address space valid base1 [31:20] write bits b'0_0000_0000 1 mb bits 31 to 20 b'0_0000_0001 2 mb bits 31 to 21 b'0_0000_0011 4 mb bits 31 to 22 : : : b'0_1111_1111 256 mb bits 31 to 28 b'1_1111_1111 512 mb bits 31 to 29 the pciconf6 register is initialized to h'00000000 at a power-on reset and software reset. always write to this register prior to transferring data to or from the pcic memory from the pci bus. bits 31 to 20?base address of the memory space 1 (base1 31 to 20): specifies the base address of the local address space 1 (this lsi external bus space). bits 19 to 4?base address of the memory space 1 (base1 19 to 4): fixed at h'0000 in hardware. bit 3?pre-fetch control (la1pref): shows whether the local address space 1 can be pre- fetched. bit 3: la1pref description 0 prefetch disabled (initial value) 1 prefetch enabled (not supported)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 873 of 1122 rej09b0370-0400 bits 2 and 1?memory type (la1type1 to 0): these bits indicate the memory type of the local address space 1. bit 2: la1type1 bit 1: la1type0 description 0 0 the base address can be set to 32-bit width, 32-bit space (initial value) 1 the base address can be set to 32-bit width, but less than 1mb (not supported) 1 0 the base address has 64-bit width (not supported) 1 reserved bit 0?address space indicator (la1asi): shows whether the base a ddress specified by this register is an i/o space or memory space. bit 0: la1asi description 0 memory space (initial value) 1 i/o space 22.2.8 pci configuration register 7 (pciconf7) to pci configuration register 10 (pciconf10) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bits 31 to 0?reserved: these bits are always read as 0.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 874 of 1122 rej09b0370-0400 22.2.9 pci configuration register 11 (pciconf11) bit: 31 30 29 28 27 26 25 24 ssid15 ssid14 ssid13 ssid 12 ssid11 ssid10 ssid9 ssid8 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ssid7 ssid6 ssid5 ssid4 ssid3 ssid2 ssid1 ssid0 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 svid15 svid14 svid13 svid 12 svid11 svid10 svid9 svid8 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 svid7 svid6 svid5 svid4 svid3 svid2 svid1 svid0 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w the pci configuration register 11 (pciconf11) is a 32-bit read/write register that accommodates the subsystem id and subsystem vendor id pci configuration registers stipulated in the pci local bus specifications. the register contai ns the id of the add-in board that this lsi is installed on its subsystem (bits 31 to 16) as well as the subsystem vendor id (bits 15 to 0). all bits can be written to from the pp bus. the pciconf11 register is not initialized at a reset. always initialize this register while the cfinit bit (bit 0) of the pcicr register is cleared. bits 31 to 16?ssid15 to 0: specifies the subsystem id.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 875 of 1122 rej09b0370-0400 bits 15 to 0?svid15 to 0: specifies the pci subsystem vendor id. 22.2.10 pci configuration register 12 (pciconf12) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bits 31 to 0?reserved: these bits are always read as 0. 22.2.11 pci configuration register 13 (pciconf13) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 capptr7 capptr6 capptr5 capptr4 c apptr3 capptr2 capptr1 capptr0 initial value: 0 1 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci configuration register 13 (pciconf13) is a 32-bit read-only register that accommodates the extended function pointer pci configuration register stipulated in the pci power management specifications. the address offset of the extended function is read from bits 7 to 0.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 876 of 1122 rej09b0370-0400 all bits are fixed in hardware. bits 31 to 8?reserved: these bits are always read as 0. bits 7 to 0?capptr7 to 0: these bits specify the address o ffset of the extended functions (power management). the initial value is h'40 (fixed). 22.2.12 pci configuration register 14 (pciconf14) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bits 31 to 0?reserved: these bits are always read as 0.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 877 of 1122 rej09b0370-0400 22.2.13 pci configuration register 15 (pciconf15) bit: 31 30 29 28 27 26 25 24 mlat7 mlat6 mlat5 mlat 4 mlat3 mlat2 mlat1 mlat0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 mgnt7 mgnt6 mgnt5 mgnt 4 mgnt3 mgnt2 mgnt1 mgnt0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ipin7 ipin6 ipin5 ipin4 ipin3 ipin2 ipin1 ipin0 initial value: 0 0 0 0 0 0 0 1 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ilin7 ilin6 ilin5 ilin 4 ilin3 ilin2 ilin1 ilin0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w the pci configuration register 15 (pciconf15) is a 32-bit read/partial-write register that accommodates the maximum latenc y, minimum grant, interrupt pin, and interrupt line pci configuration registers stipulated in the pci local bus specificati ons. the interrupt pins used by this lsi is read from bits 15 to 8. bits 7 to 0 indicate to which of the interrupt request signal lines of an interrupt controller the interrupt line is connected. bits 31 to 8 are fixed in hardware. bits 7 to 0 can be written to from both the pp bus and pci bus. the pciconf15 register is initialized to h'0000 0100 at a power-on reset and software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 878 of 1122 rej09b0370-0400 bits 31 to 24?designation of maximum latency (mlat7 to 0): these bits specify the maximum time from the time the pci master device demands bus privileges and to the time it obtains the privileges (not supported). bits 23 to 16?minimum latency specification (mgnt 7 to 0): specify the burst interval required by the pci device (not supported). bits 15 to 8?interrupt pin specification (ipin7 to 0) bits 15 to 8: ipin7 to 0 description h'01 inta used (initial value) h'02 intb used h'03 intc used h'04 intd used h'05 to h'ff reserved bits bits 7 to 0?interrupt line specification (ilin7 to 0): specifies an interrupt line of a system to which interrupt output used by the pcic is connected.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 879 of 1122 rej09b0370-0400 22.2.14 pci configuration register 16 (pciconf16) bit: 31 30 29 28 27 26 25 24 pmespt4 pmespt3 pmespt2 pmespt1 pmespt0 d2spt d1spt ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ds1 ? pmeclk ver2 ver1 ver0 initial value: 0 0 0 0 0 0 0 1 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r/w r/w r/w bit: 15 14 13 12 11 10 9 8 nip7 nip6 nip5 nip4 nip3 nip2 nip1 nip0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 capid7 capid6 capid5 capid4 capid3 capid2 capid1 capid0 initial value: 0 0 0 0 0 0 0 1 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci configuration register 16 (pciconf16) is a 32-bit read/partial-write register than accommodates the power ma nagement function (pmc), next-item pointer, an d extended function id power management registers stipulated in the pci power management specifications. pciconf16 is valid only when the pcic is functioning not as the host. the power management related functions are read from bits 31 to 16 (pmc), the address offset of the next function in the extended function list is read from bits 15 to 8 (next item pointer), and the power management id (h'01) is read from bits 7 to 0 (extended function id). bits 18 to 16 can be written to from the pp bus only. other bits are fixed in hardware. the pciconf16 regsiter is initialized to h'0001000 1 at a power-on reset and a software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 880 of 1122 rej09b0370-0400 bits 31 to 27?pme support (pmespt4 to 0): not supported. defines the function state supporting pme output. bit 26?d2 support (d2spt): not supported. specifies whethe r d2 state is supported. bit 25?d1 support (d1spt): not supported. specifies whethe r d1 state is supported. bits 24 to 22?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 21?dsi: specifies whether bit-device-speci fic initialization is required. bit 20?reserved: this bit always returns 0 when read. always write 0 to this bit. bit 19?pme clock (pmeclk): not supported. specifies whethe r a clock is required for pme support. bits 18 to 16?version (ver2 to 0): specify the version of power management specifications. bits 15 to 8?next item pointer ( nip7 to 0): specify the offset to the next extended function register bits 7 to 0?extended function id (capid7 to 0): extended function (capability identifier) id. these bits always return h'01 when read.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 881 of 1122 rej09b0370-0400 22.2.15 pci configuration register 17 (pciconf17) bit: 31 30 29 28 27 26 25 24 data7 data6 data5 data4 data3 data2 data1 data0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 pmest dtatscl1 dtatscl0 dat asel3 datasel2 datasel1 datasel0 pmeen initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? pwrst1 pwrst0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r/w r/w pp bus-r/w: r r r r r r r/w r/w the pci configuration register 17 (pciconf17) is a 32-bit read/partial-write register that accommodates the power manage ment control/status (pmcsr), bridge-compatible pmcsr extended (pmcsr_bse), and data power management registers stipulated in the pci power management specifications. pciconf17 is valid only when the pcic is operating not as the host. bits 31 to 24 (data) and bits 23 to 16 (pmcsr_bse) are not supported. the power management status is read from bits 15 to 0 (pmcsr). bits 1 and 0 can be written to from both the pp bus and the pci bus. other bits are fixed in hardware. pciconf17 is initialized to h'00000000 at a power-on reset and software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 882 of 1122 rej09b0370-0400 when b'11 is written to bits 1 and 0 and a tran sition is made to power state d3 (power down mode), pcic operation as a master target is disabled, regardless of the setting of bits 2 to 0 of the pciconf1 (bus master control, memory and i/o space access control) (these bits are masked). when b'00 is written to bits 1 and 0 and a transition is made to power state d0 (normal operating mode), the mask is canceled. bits 31 to 24?data (data7 to 0): not supported. data field for power management. bits 23 to 16?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 15?pme status (pmest): not supported. shows the status of the pme bit. this bit is set when the signal is output. bits 14 and 13?data scale (dtatscl1 to 0): not supported. these bits specify the scaling value for the data field value. bits 12 to 9?data select (datasel3 to 0): not supported. select the value to be output to the data field. bit 8? pme enable (pmeen): not supported. controls the pme signal output. bits 7 to 2?reserved: these bits always return 0 when r ead. always write 0 to these bits. bits 1 and 0?power state ( pwrst1 and 0): specifies the power state. no state transition is effected when a non-su pported state is specified. (normal termination, no error output.) bit 1: pwrst1 bit 0: pwrst0 description 0 0 d0 state (initial value, normal state) 1 d1 state (not supported) 1 0 d2 state (not supported) 1 d3 state (power down mode)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 883 of 1122 rej09b0370-0400 22.2.16 reserved area reserved area. bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r note: pci configuration addresses h'48 to h'fc are reserved. bits 31 to 0?reserved: these bits always return 0 when read.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 884 of 1122 rej09b0370-0400 22.2.17 pci control register (pcicr) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? trdsgl byteswap initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r/w r/w pp bus-r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 pcipup bmabt md10 md9 serr inta rstctl cfinit initial value: 0 0 0/1 * 0/1 * 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r r r/w r/w r/w r/w note: * the value of the external pin is samp led in a power-on reset by means of the reset pin. the pci control register (pcicr) is a 32-bit register that monitors the status of the mode pin at initialization and controls the basic operation of the pcic. bits 5 (md10) and 4 (md9) are read- only bits from the pp bus. other bits are read /write bits. bits 9 (trdsgl) and 8 (byteswap) are read/write bits from the pci bus. other bits are read-only. in pcic host operation, a software reset can be applied to the pci bus by means of bit 1 (rstctl) of pcicr. when a so ftware reset is executed, the pcirst pin is asserted and the internal state of the pcic is initialized.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 885 of 1122 rej09b0370-0400 the pcicr register is initialized at a power-on reset to h'000000*0 (bits 7 and 6 are initialized to b'00, and bits 5 and 4 sample the value of mode pins 9 and 10). at a software reset, bit 1 (rstctl) is not initialized. all other bits are initialized in the same way as at a software reset. this register can be written to only when bits 31 to 24 are h'a5. always set bit 0 (cfinit) to 1 on completion of pcic register initialization. bits 31 to 10?reserved: these bits are always read as 0. when writing, write h'a5 to bits 31 to 24, and 0 to others. bit 9?target read single buffer (trdsgl): this bit specifies whether one target read buffer (32 bytes) or two target read buffers (64 bytes) are used for target me mory read access to the pcic. when two target read buffers faces are used, the data from two buffers are read via the local bus in advanced. bit 9: trdsgl description 0 use 2 target read buffers (initial value) 1 use 1 target read buffer only bit 8?data byte swap ( byteswap): specifies whether the data byte is swapped when the pcic performs pio transfer. bit 8: byteswap description 0 send data as-is (initial value) 1 swap data byte before sending note: for details, refer to section 22.4, endians. bit 7?pci signal pull-up (pciup): controls the pull-up resistance of the pci signal. regarding the pins that are subject to pull-up, refer to table 22.1. regarding the pull-up control provided when the pcipeq2 /md9, pcireq3 /md10 or pcireq4 is used as a port, refer to the section on port control register (pcipctr). bit 7: pciup description 0 pull-up (initial value) 1 no pull-up
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 886 of 1122 rej09b0370-0400 bit 6?bus master arbitration ( bmabt): controls the pci bus arbitration mode of the pcic when the pcic is operating as the host. when the pcic is non-host, the value of this bit is ignored. bit 6: bmabt description 0 fixed priority order (device 0 (pci c) > device 1 > device 2 > device 3 > device 4) (initial value) 1 pseudo round-ribbon (the priority leve l of the device with bus privileges is set lowest at the next access.) bit 5?mode 10 pin monitor (md10): monitors the pcireq3 /md10 pin value in a power-on reset by means of the reset pin. bit 5: md10 description 0 host bridge function (arbitration) enabled 1 host bridge function disabled bit 4?mode 9 pin monitor (md9): monitors the pcireq2 /md9 pin value in a power-on reset by means of the reset pin. bit 4: md9 description 0 pciclk used as pci clock 1 feedback input clock from ckio used as pci clock bit 3? serr output (serr): software control of serr output. this bit is valid only when bit 8 (ser) of the pciconfi register is ?1 ?. when ?1? is written to this bit, serr is asserted for 1 clock. this bit always returns ?0? when read. used when the pcic is not the host. if used when the pcic is the host, an serr assert interrupt is generated to the cpu. bit 3: serr description 0 serr pin at hi-z (driven to high by pull-up resistor) (initial value) 1 assert serr (low output)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 887 of 1122 rej09b0370-0400 bit 2? i nta output ( inta): software control of inta (valid only when pcic is not host) bit 2: inta description 0 inta pin at hi-z (driven to high by pull-up resistor) (initial value) 1 assert inta (low output) bit 1?pcirst output control (rstctl): controls the pcirst output. this field is reset only at a power-on reset. do not use the field when the pcic is non-host. bit 1: pcirst description 0 negate pcirst (high output) (initial value) 1 assert pcirst (low output) bit 0?pcic internal register init ialization control bit (cfinit): after the sh initializes the pci registers, setting this bit enables access from the pci bus. during initialization, no bus privileges are granted to other devices on the pci bus while operating as the host. when operating not as the host, a retry is returned wit hout the access from the pci bus being accepted. bit 0: cfinit description 0 initialization busy (initial value) 1 initialization complete
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 888 of 1122 rej09b0370-0400 22.2.18 pci local space register [1:0] (pcilsr [1:0]) bit: 31 30 29 28 27 26 25 24 ? ? ? plsr28 plsr27 plsr26 plsr25 plsr24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 plsr23 plsr22 plsr 21 plsr20 ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci local space register [1:0] (pcilsr [1:0]) specifies the cap acities of the two local address spaces (address space 0 and address space 1) supp orted when a device on the pci bus performs a memory read/memory write of the pcic using target transfers. this is a 32-bit register that can be read and written from the pp bus, or read only from the pci bus. the pcilsr [1:0] register is initialized to h'0000 0000 at a power-on reset and software reset. always write to this register before performing target transfers to specify the capacity of the address space being used. specify th e value ?(capacity ?1) bytes? in bi ts 28 to 20. for example, to secure a 32mb space, set the value h'01f00000.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 889 of 1122 rej09b0370-0400 if you specify all zeros, a 1mb space is reserved. you can specify an addr ess space up to 512mb. refer to table 22.6 in section 22.2.6, pci configuration register 5 (pciconf5). bits 31 to 29?reserved: these bits always return 0 when r ead. always write 0 to these bits when writing. bits 28 to 20?capacities of the local address spaces 0, 1 ( plsr28 to 20): these bits specify the capacities of the address space 0 and address sp ace 1 in bytes. specifying (capacity ?1) bytes. a 1mb space is secured if all zeros are specified. bits 19 to 0?reserved: these bits always return 0 when r ead. always write 0 to these bits.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 890 of 1122 rej09b0370-0400 22.2.19 pci local address register [1:0] (pcilar [1:0]) bit: 31 30 29 28 27 26 25 24 ? ? ? lar28 lar27 lar26 lar25 lar24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 lar23 lar22 lar21 lar20 ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r/w r/w r/w r/w r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci local address register [1:0] (pcilar [1 :0]) specifies the starting address (external address of local bus) of the two local address spaces (add ress space 0 and address space 1) supported when performing memory read/memory write operations due to target transfers to the pcic. it is a 32-bit register that can be read and written from the pp bus and is read-only from the pci bus. the pcilar [1:0] register is in itialized to h'00000000 at a powe r-on reset and software reset. the valid bits of the local address specified by this register vary according to the capacity of the address space specified in the pcil sr [1:0] register. in other words, set 0 in the least significant address bit which corresponds to the capacity set by pcilsr0, 1, and set the starting address only
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 891 of 1122 rej09b0370-0400 in the most significant address b it. for example, when the capacity of the local address space is set to 32mb (pcilsr: h'01f00000), bits 28 to 25 of the local address are valid. only the value set in these bits is used as the physical address of the local address space. always write to this register prior to target transfers. specify the st arting addres s (physical address) of the memory installed on the local bus according to the address space being used. bits 28 to 26 of the pci local address register 0 select the local addres s area. bits 25 to 20 show the address within that area. bits 31 to 29?reserved: these bits always return 0 when r ead. always write 0 to these bits. bits 28 to 20?local address ( lar28 to 20): specify bits 28 to 20 of the starting address of the local address space. bits 19 to 0?reserved: these bits always return 0 when r ead. always write 0 to these bits.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 892 of 1122 rej09b0370-0400 22.2.20 pci interrupt register (pciint) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 m_lock on t_tgt_a bort ? ? ? ? tgt_ret ry mst_dis initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/wc r/wc r r r r r/wc r/wc pp bus-r/w: r/wc r/wc r r r r r/wc r/wc bit: 7 6 5 4 3 2 1 0 adrper r serr_d et t_dper r_wt t_perr_ det m_tgt_a bort m_mst_ abort m_dper r_wt m_dper r_rd initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc pp bus-r/w: r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc note: wc: cleared by writing ?1?. (writing of 0 is ignored.) the pci interrupt register (pciint) is a 32-bit re gister that saves the error source when an error occurs on the pci bus as a result of the pcic attempting to invoke a transfer on the pci bus, or when the pcic is the pci master or pci target. th is register can be read from both the pp bus and pci bus. also, 1 can be written from either the pp bus or pci bus to perform a write-clear in which the detection bit is cleared to its initial value (0). the pciint register is initialized to h'00000000 at a power-on reset or software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 893 of 1122 rej09b0370-0400 when an error occurs, the bit co rresponding to the error content is set to 1. each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (write clear) note that the error detection bits can be set even when the interrupt is masked. the error source holding ci rcuit can only store one error source . for this reason, any second or subsequent error factors are not stor ed if errors occur consecutively. bits 31 to 16?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 15?unlocked transfer detection interrupt (m_lockon): when the pcic is master, an unlocked pio transfer was performed when the i-specified target was locked. bit 14?target target abor t interrupt (t _tgt_abort): indicates the termination of transaction by target abort when the pcic is a ta rget. target abort is generated when the 2 least significant address bits (bits 1, 0) and byte enable constitute an illegal combination (illegal byte enable) during i/o transfer. bits 13 to 10?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 9?target memory read retr y timeout interru pt (tgt_retry): when the pcic is target, the master did not attempt a retry within the prescribed number of pci bus clocks (2 15 ) (detected only in the case of memory read operations). bit 8?master function disabl e error interrupt (mst_dis): indicates that an attempt was made to conduct a master operation (pio transfer, dma transfer) when bit 2 (bum) of the pciconf1 was set to 0 to prohibit bus master operations. bit 7?address parity error de tection interrupt (adrperr): address parity error detected. detects only when bit 6 (per) and bit 8 (ser) of the pciconf1 are both 1. bit 6? serr detection interrupt (serr_det): when the pcic is host, assertion of the serr signal was detected. bit 5?target write data parity error interrupt (t_dperr_wt): when the pcic is target, a data parity error was detected while receiving a target write transfer (only detected when pciconfi bit 6 (per) is 1). bit 4?target read perr detection interrupt (t_perr_det): when the pcic is target, perr was detected when receiving a target read transfer. detects only when bit 6 (ser) of the pciconf1 is 1.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 894 of 1122 rej09b0370-0400 bit 3?master target abort interrupt (m_tgt_abort): when the pcic is master. indicates the termination of transaction by target abort. bit 2?master master abort interrupt (m_mst_abort): when the pcic is master. indicates the termination of tr ansaction by master abort. bit 1?master write perr detection interrupt ( m_dperr_wt): when the pcic is master. perr received from the target while writing data to the target. detects only when bit 6 (per) of the pciconf1 is 1. bit 0?master read data parity error interrupt (m_dperr_rd): when the pcic is master, a parity error was detected during a data read fr om the target. detects only when bit 6 (per) of the pciconf1 is 1.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 895 of 1122 rej09b0370-0400 22.2.21 pci interrupt mask register (pciintm) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 m_lock on t_tgt_a bort ? ? ? ? tgt_ret ry mst_dis initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r r r r r/w r/w pp bus-r/w: r/w r/w r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 adrper r serr_d et t_dper r_wt t_perr_ det m_tgt_a bort m_mst_ abort m_dper r_wt m_dper r_rd initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w the pci interrupt mask register (pciintm) sets the respective interrupt masks for the interrupts generated when errors occur in pci transfers. it is a 32-bit read/write register that can be accessed from both the pp bus and pci bus. when set to 0, the respective interrupt is disabled, and enabled when set to 1. the pciintm register is initialized to h'00000000 at a power-on reset and software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 896 of 1122 rej09b0370-0400 bits 31 to 16?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 15?unlocked transfer detection interrupt mask (m_lockon) bit 14?target target abort in terrupt mask (t_tgt_abort) bits 13 to 10?reserved: these bits always return 0 when r ead. always write 0 to these bits. bit 9?target retry timeout interrupt mask (tgt_retry) bit 8?master function disable error interrupt mask (mst_dis) bit 7?address parity error det ection interrupt mask (adrperr) bit 6? serr detection interrupt mask (serr_det) bit 5?target write data parity error interrupt mask (t_dperr_wt) bit 4?target read perr detection interrupt mask (t_perr_det) bit 3?master target abort in terrupt mask (m_tgt_abort) bit 2?master master abort interrupt mask (m_mst_abort) bit 1?master write data pa rity error interrupt mask ( m_dperr_wt) bit 0?master read data parity error interrupt mask (m_dperr_rd)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 897 of 1122 rej09b0370-0400 22.2.22 pci address data re gister at error (pcialr) bit: 31 30 29 28 27 26 25 24 alog31 alog30 alog29 alog2 8 alog27 alog26 alog25 alog24 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 alog23 alog22 alog21 alog2 0 alog19 alog18 alog17 alog16 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 alog15 alog14 alog13 alog1 2 alog11 alog10 alog9 alog8 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 alog7 alog6 alog5 alog4 alog3 alog2 alog1 alog0 initial value: ? ? ? ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci address data register at error (pcialr) stores the pci address data (alog [31:0]) of errors that occur on the pci bus. it is a 32-bit register that can be read from both the pp bus and pci bus. the pcialr register is not initialized at a power-o n reset or software reset. the initial value is undefined. a valid value is retained only when one of the pciint register bits is set to 1. the error source holding ci rcuit can only store one error source . for this reason, any second or subsequent error factors are not stor ed if errors occur consecutively.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 898 of 1122 rej09b0370-0400 bits 31 to 0?address log ( alog31 to 0): pic address data (value of a/d line) at time of error. (initial value is undefined.) 22.2.23 pci command data register at error (pciclr) bit: 31 30 29 28 27 26 25 24 mstpio mstdma0 mstdma1 mstdma2 mstdma3 tgt ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? cmdlog3 cmdlog2 cmdlog1 cmdlog0 initial value: 0 0 0 0 ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci command data register at error (pcicl r) stores the type of transfer (mstpio, mstdma0, mstdma1, mstdma2, mstdma3, or tgt) when an error occurs on the pci bus, and the pci command (cmdlog [3:0]). it is a 32-bit register that can be read from both the pp bus and pci bus. although bits 31 to 26 of the pciclr register are initialized at a power-on reset and a software reset, bits 3 through 0 are not initialized. when an erro r is detected, 1 is set in one of bits 31 to 26, and the relevant command value is retained in bits 3 to 0.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 899 of 1122 rej09b0370-0400 a valid value is retained only when one of the pciint register bits is set to 1. the error source holding ci rcuit can only store one error source . for this reason, any second or subsequent error factors are not stor ed if errors occur consecutively. bit 31?pio error ( mstpio): error occurred in pio transfer. bit 30?dma0 error ( mstdma0): error occurred in dm a channel 0 transfer. bit 29?dma1 error (mstdma1): error occurred in dm a channel 1 transfer. bit 28?dma2 error (mstdma2): error occurred in dm a channel 2 transfer. bit 27?dma3 error (mstdma3): error occurred in dm a channel 3 transfer. bit 26?target error (tgt): error occurred in target read or target write transfer. bits 25 to 4?reserved: these bits are always read as 0. bits 3 to 0?command log (cmdlog3 to 0): these bits retain the pci transfer command information (value of c/ be line) upon detection of an error. (initial value is undefined.)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 900 of 1122 rej09b0370-0400 22.2.24 pci arbiter int errupt register (pciaint) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? mst_brkn tgt_busto mst_busto ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r/wc r/wc r/wc r r r pp bus-r/w: r r r/wc r/wc r/wc r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? tgt_abort mst_abort dperr_wt dperr_rd initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r/wc r/wc r/wc r/wc pp bus-r/w: r r r r r/wc r/wc r/wc r/wc note: cleared by writing wc:1. (writing of 0 is ignored.) the pci arbiter interrupt register (pciaint) is a 32 -bit register that stores the sources of pci bus errors occurring during transfers by another pci master device when the pcic is operating as the host with the arbitration function. the register can be read from both the pp bus and the pci bus. also, each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it from either the pp bus or the pci bus. (write clear) the pciaint register is initialized to h'00000000 at a power-on reset or software reset. when an error is detected, the bit corresponding to the error type is set to 1. each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (write clear)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 901 of 1122 rej09b0370-0400 the error detection bits are set even when the interrupts are masked. bits 31 to 14?reserved: these bits always return 0 when r ead. always write 0 to these bits when writing. bit 13?master broken interrupt (mst_brkn): detects when the master granted with bus privileges does not start a transaction ( frame not asserted) within 16 clocks. for the sh7751, see 22.12, usage notes. bit 12?target bus timeout interrupt (tgt_busto): neither trdy nor stop are not returned within 16 clocks in the case of the first data transfer, or within 8 clocks in the case of second and subsequent data transfers. for the sh7751, see 22 .12, usage notes. bit 11?master bus timeou t interrupt (mst_busto): indicates the detection that irdy was not asserted within 8 clock cycles in a transaction initiated by a device including pcic. bits 10 to 4?reserved: these bits always return 0 when read . always write 0 to these bits when writing. bit 3?target abort interrupt (tgt_abort): indicates the termination of transaction by target abort when a device other than th e pcic is operating as the bus master. bit 2?master abort interrupt (mst_abort): indicates the terminati on of transaction by master abort when a device other than th e pcic is operating as the bus master. bit 1?write data parity error interrupt (dperr_wt): indicates the detection of the assertion of perr in a data write operation when a device other than the pcic is operating as the bus master. bit 0?read data parity error interrupt (dperr_rd): indicates the detection of the assertion of perr in a data read operation when a device other than the pcic is operating as the bus master.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 902 of 1122 rej09b0370-0400 22.2.25 pci arbiter interrupt mask register (pciaintm) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? mst_brkn tgt_busto mst_busto ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r/w r/w r/w r r r pp bus-r/w: r r r/w r/w r/w r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? tgt_abort mst_abort dperr_wt dperr_rd initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r/w r/w r/w r/w pp bus-r/w: r r r r r/w r/w r/w r/w the pci arbiter interrupt mask register (pciai ntm) sets interrupt masks for the individual interrupts that occur due to errors generated during pci transfers performed by other pci devices when the pcic is operating as the host with the arbitration function. it is a 32-bit register that is readable and writable from both the peripheral bus and the pci bus. each bit is set to 0 to disable the respective interrupt, or 1 to enable that interrupt. the pciintm register is initialized to h'00000000 at a power-on reset or software reset. bits 31 to 14?reserved: these bits always return 0 when r ead. always write 0 to these bits when writing.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 903 of 1122 rej09b0370-0400 bit 13?master broken interrupt mask (mst_brkn) bit 12?target bus timeout interrupt mask (tgt_busto) bit 11?master bus timeout in terrupt mask (mst_busto) bits 10 to 4?reserved: these bits always return 0 when read . always write 0 to these bits when writing. bit 3?target abort interrupt mask (tgt_abort) bit 2?master abort interrupt mask (mst_abort) bit 1?read data parity erro r interrupt mask (dperr_wt) bit 0?write data parity erro r interrupt mask (dperr_rd) 22.2.26 pci error bus mast er data register (pcibmlr) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? req4id req3id req2id req1id req0id initial value: 0 0 0 ? ? ? ? ? pci-r/w: r r r r r r r r pp bus-r/w: r r r r r r r r the pci error bus master data register (pcibmlr) stores the device number of the bus master at the time an error occurred in pci transfer by another pci device when the pcic was operating as the host with the arbitration function. it is a 32-bit register than can be read from both the pp bus and pci bus. the pciintm register is initialized to h'00000000 at a power-on reset or software reset. a valid value is retained only when one of the pciaint register bits is set to 1.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 904 of 1122 rej09b0370-0400 the bus master data holding circuit can only stor e data for one master. for this reason, no bus master data is stored for any second or subsequent errors if errors occur consecutively. bits 31 to 5?reserved: these bits always return 0 when read . always write 0 to these bits when writing. bit 4?req4 error (req4id): error occurred when device 4 (req4) was bus master. bit 3?req3 error (req3id): error occurred when device 3 (req3) was bus master. bit 2?req2 error (req2id): error occurred when device 2 (req2) was bus master. bit 1?req1 error (req1id): error occurred when device 1 (req1) was bus master. bit 0?req0 error (req0id): error occurred when device 0 (req0) was bus master. 22.2.27 pci dma transfer arbitration register (pcidmabt) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? dmabt initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r r/w pp bus-r/w: r r r r r r r r/w the pci dma transfer arbitration re gister (pcidmabt) is a register that controls the arbitration mode in the case of dma transfers. two types of dma arbitration mode can be selected: priority- fixed and pseudo round-robin. this 32-bit read/wr ite register can be accesse d from both the pp bus and pci bus. the pcidmabt register is initialized to h'0000 0000 at a power-on reset or software reset. always write to this register to specify the dma transfer arbitration mode prior to starting dma transfers.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 905 of 1122 rej09b0370-0400 bits 31 to 1?reserved: these bits always returns 0 when read . always write 0 to these bits when writing. bit 0?dma arbitration mode ( dmabt): controls the dma arbitration mode. bit 0: dmabt description 0 priority-fixed (channel 0 > channel 1 > channel 2 > channel 3) (initial value) 1 pseudo round-robin 22.2.28 pci dma transfer pci address register [3:0] (pcidpa [3:0]) bit: 31 30 29 28 27 26 25 24 pdpa31 pdpa30 pdpa29 pdpa28 pdpa27 pdpa26 pdpa25 pdpa24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 pdpa23 pdpa22 pdpa21 pdpa20 pdpa19 pdpa18 pdpa17 pdpa16 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 pdpa15 pdpa14 pdpa13 pdpa12 pdpa11 pdpa10 pdpa9 pdpa8 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pdpa7 pdpa6 pdpa5 pdpa4 pdpa3 pdpa2 pdpa1 pdpa0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 906 of 1122 rej09b0370-0400 the dma transfer pci address register [3:0] (pcidp a [3:0]) specifies the starting address at the pci when performing dma transfers. this 32-bit read/write register can be accessed from both the pp bus and pci bus. the pcidpa register is initialized to h'00000000 at a power-on reset and a software reset. the transfer address of a byte boundary or ch aracter boundary can be set, but the 2 least significant bits of this register are ignored, and the data of the longword boundary is transferred. before starting a dma transfer, be sure to write to this register. after a dma transfer starts, the value in the register is not retained. always re-s et the register value before starting a new dma transfer after a dma transfer has been completed. bits 31 to 0?dma transfer pci starting address ( pdpa31 to 0): set the pci starting address for dma transfer.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 907 of 1122 rej09b0370-0400 22.2.29 pci dma transfer local bus start address register [3:0] (pcidla [3:0]) bit: 31 30 29 28 27 26 25 24 ? ? ? pdla28 pdla27 pdla26 pdla25 pdla24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r/w r/w r/w r/w r/w pp bus-r/w: r r r r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 pdla23 pdla22 pdla21 pdla20 pdla19 pdla18 pdla17 pdla16 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 pdla15 pdla14 pdla13 pdla12 pdla11 pdla10 pdla9 pdla8 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pdla7 pdla6 pdla5 pdla4 pdla3 pdla2 pdla1 pdla0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w the dma transfer local bus star t address register [3:0] (pcidl a [3:0]) specifies the starting address at the local bus when performing dma transfers. this 32-bit read/write register can be accessed from both the pp bus and pci bus. the pcidla register is initialized to h'00000000 at a power-on reset and a software reset. the transfer address of a byte boundary or ch aracter boundary can be set, but the 2 least significant bits of the register are ignored, and the data of the longword boundary is transferred. note that the local bus starting address set in this register is the external address of the sh bus.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 908 of 1122 rej09b0370-0400 always write to this register prior to starting dma transfers. after a dm a transfer starts, the register value is not retained. always re-set this register before starting a new dma transfer after a dma transfer has completed. bits 31 to 29?reserved: these bits always return 0 when r ead. always write 0 to these bits. bits 28 to 0?dma transfer local bus starting address (pdla28 to 0): these bits set the starting address of the local bus (external address of sh bus) for dma transfer. bits 28 to 26 indicate the local bus area. 22.2.30 pci dma transfer counter register [3:0] (pcidtc [3:0]) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ptc25 ptc24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r r/w r/w pp bus-r/w: r r r r r r r/w r/w bit: 23 22 21 20 19 18 17 16 ptc23 ptc22 ptc21 ptc 20 ptc19 ptc18 ptc17 ptc16 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ptc15 ptc14 ptc13 ptc 12 ptc11 ptc10 ptc9 ptc8 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/w r/w r/w r/w r/w r/w r/w pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 909 of 1122 rej09b0370-0400 the dma transfer counter register [3:0] (pcidtc [3:0]) specifies the nu mber of bytes for dma transfers. this 32-bit r ead/write register can be accessed from both the pp bus and pci bus. when read during a dma transfer, it returns the rema ining number of bytes in the dma transfer. the pcidtc register is initialized to h'00000000 at a power-on reset and a software reset. bits 25 to 0 are used to specify the number of transfer bytes. when set to h'00000000, the maximum 64mb transfer is performe d. since the transfer data size corresponds only to longword data, the 2 least signifi cant bits are ignored. always write to this register prior to starting a dma transfer. please re-set this register when starting a new dma transfer after a dma transfer completes. bits 31 to 26?reserved: these bits always return 0 when r ead. always write 0 to these bits. bits 25 to 0?dma transfer byte count (ptc25 to 0): specify the number of bytes in dma transfer. the maximum number of transfer bits are 64 mb (when set to h'00000000).
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 910 of 1122 rej09b0370-0400 22.2.31 pci dma control register [3:0] (pcidcr [3:0]) bit: 31 30 29 . . . 19 18 17 16 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: r r r . . . r r r r pp bus-r/w: r r r . . . r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? alnmd10 almmd9 dmast initial value: 0 0 0 0 0 0 0 0 pci-r/w: r r r r r r/w r/w r pp bus-r/w: r r r r r r/w r/w r bit: 7 6 5 4 3 2 1 0 dmaim dmais lahold ? iosel0 dir dmastop dmastrt initial value: 0 0 0 0 0 0 0 0 pci-r/w: r/w r/wc r/w r r/w r/w r/w r/w pp bus-r/w: r/w r/wc r/w r r/w r/w r/w r/w note: cleared by writing wc:1. (writing of 0 is ignored.) the dma transfer control regist er [3:0] (pcidcr [3:0]) specifi es the operating mode of the respective channels and the method of transfer, etc. this 32-bit r ead/write register can be accessed from the pp bus and pci bus. the pcidcr register is initialized to h'00000000 at a power-on reset and software reset. writing 1 to bit 0 (dmastrt) starts dma transfer. al ways re-set the value in this register before starting a new dma transfer after completion of a dma transfer. when setting the dmastop bit, do not write 1 to the dmastart bit. also, write the same setting at the start of tran sfer to the dmaim, dmais, lahold, iosel and dir bits. example: starting transfer with pcidcr = h'00000085 forced dma termination pcidcr = h'00000086 if dma is forcibly terminated with a value othe r than the setting used in the transfer being performed, data accuracy is not guaranteed.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 911 of 1122 rej09b0370-0400 bits 31 to 11?reserved: these bits always return 0 when r ead. always write 0 to these bits. bits 10 and 9?alignment mode (alnmd): sets data alignment when local bus is big endian bit 10: alnmd10 bit 9: alnmd9 description 0 0 byte boundary mode (initial value) 1 w/lw boundary mode 1 (lw data is sent as byte 4) 1 0 w/lw boundary mode 2 (lw data is sent as word 2) 1 w/lw boundary mode 3 (lw data is sent as longword) legend: w: word lw: longword note: for details, refer to section 22.4, endians. bit 8?dma transfer end status (dmast): indicates the dma transfer end status. bit 8: dmast description 0 normal termination (initial value) 1 abnormal termination (error detection or forced dma transfer termination) bit 7?dma transfer terminatio n interrupt mask (dmaim): specifies the dma transfer termination interrupt mask. bit 7: dmaim description 0 interrupt disabled (initial value) 1 interrupt enabled bit 6?dma transfer termination interrupt status (dmais): indicates the dma transfer termination interrupt status. the interrupt status is set even when the interrupt mask is set. bit 6: dmais description when writing 0 ignored 1 status clear when reading 0 interrupt not detected (initial value) 1 interrupt detected
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 912 of 1122 rej09b0370-0400 bit 5?local address control (lahold): local address control during dma transfer bit 5: lahold description 0 incremented (initial value) 1 high address fixed (address a[4:0] is incremented) bit 4?reserved: this bit always returns 0 when read. always write 0 to this bit. bit 3?pci address space type (iosel): type of pci address sp ace during transfer bit 3: iosel description 0 memory space (initial value) 1 i/o space bit 2?transfer direction ( dir): transfer direction during dma transfer bit 2: dir description 0 transfer from pci bus to local bus (sh bus) (initial value) 1 transfer from local bus (sh bus) to pci bus bit 1?forced dma transfer termination ( dmastop): forced termination of dma transfer bit 1: dmastop description when writing 0 writing of 0 is ignored. 1 forced termination of dma transfer when reading when dma transfer stops due to forced dma transfer termination, 1 is set bit 0?dma transfer start control ( dmastrt): controls the starting of dma transfer. bit 0: dmastrt description when writing 0 ignored 1 start when reading 0 end of transfer (initial value) 1 busy (in transfer)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 913 of 1122 rej09b0370-0400 22.2.32 pio address register (pcipar) bit: 31 30 29 28 27 26 25 24 cfgen ? ? ? ? ? ? ? initial value: 1 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 busno23 busno22 busno21 busno20 busno19 busno18 busno17 busno16 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 devno15 devno14 devno13 devno12 devno11 fncno10 fncno9 fncno8 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 regadr7 regadr6 regadr5 regadr4 regadr3 regadr2 ? ? initial value: ? ? ? ? ? ? 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r r the pio address register (pcipar) is used when issuing configuration cycles on the pci bus when the pcic is host. the pcic supports the configuration mechanism 1 stipulated in the pci local bus specifications. this register is equivalent to the configuration register of configuration mechanism 1. this register is equivalent to the config_address of configuration mechanism 1. the check that the issuance of the pci configuration cycl e is enabled, and access the pci configuration space, this register contains the pci bus no., devi ce no., function no., and lw (longword) boundary of th e configuration register. this 32-bit read/write register can be accessed from the pp bus. bit 31 (cfgen) is set in hardware and none of the other bits of the pcipar register are initialized at a power-on reset or software reset.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 914 of 1122 rej09b0370-0400 always write to this register prior to accessing the pci configuration spac e. after setting a value in this register, generate the configuration cycle by reading or writing to the pio data register (pcipdr). also, a special cycle is issued by setting h'8000f f00 in this register and writing to the pcipdr. bit 31?configuration cycle generate enable (cfgen) : indicates the configuration cycle generation enable. bits 30 to 24?reserved: these bits always return 0 when r ead. always write 0 to these bits when writing. bits 23 to 16?pci bus no. (busno): these bits specify the no. of the pci bus subject to configuration access. bus no. d indicates the bus connected with the pcic. the bus no. is expressed with 8 bits, and its maximum value is 255. bits 15 to 11?device no. (devno): these bits specify the no. of the device subject to configuration access. the device no. is expressed with 5 bits, and takes a value from bits 0 to 31. in place of idsel, one of bits 31 to 16 of the a/ d line, corresponding to th e device no. set in this field, is driven to ?1?. the following table shows the relationship between the device no. and idsel (a/d [31 to 16]). when th e device no. is 10h or greater, a/d [31 to 16]) are all zeros. devno idsel devno idsel devno idsel devno idsel h'0 ad[16] = 1 h'4 ad[20] = 1 h'8 ad[24] = 1 h'c ad[28] = 1 h'1 ad[17] = 1 h'5 ad[21] = 1 h'9 ad[25] = 1 h'd ad[29] = 1 h'2 ad[18] = 1 h'6 ad[22] = 1 h'a ad[26] = 1 h'e ad[30] = 1 h'3 ad[19] = 1 h'7 ad[23] = 1 h'b ad[27] = 1 h'f ad[31] = 1 bits 10 to 8: function no. (fncno): these bits specify the no. of the function subject to configuration access. the function no. is expressed with 3 bits, and takes a value of 0 to 7. bits 7 to 2?configuration register address (regadr): these bits set the register subject to configuration access with a longword boundary. bits 1 and 0?reserved: these bits always return 0 when read. always write 0 to these bits when writing.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 915 of 1122 rej09b0370-0400 22.2.33 memory space base register (pcimbr) bit: 31 30 29 28 27 26 25 24 mbr31 mbr30 mbr29 mbr28 mbr27 mbr26 mbr25 mbr24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? lock initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r/w the memory space base register (p cimbr) specifies the most signif icant 8 bits of the address of the pci memory space when perfor ming a memory read/write opera tion using pio transfers. it also specifies locked transfers. this 32-bit read/write register can be accessed from the pp bus. all bits of the pcimbr register are initialized to 0 at a power-on reset. they are not initialized at a software reset. setting bit 0 (lock) to 1 locks the memory space for pio transfer s while the bit remains set. a locked transfer consists of the combined read and write operations. do not attempt to perform other pio transfers during the locked combination of read and write operations.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 916 of 1122 rej09b0370-0400 always write to this register prior to performing memory read/write operations by pio transfer. bits 31 to 24?memory space base address ( mbr31 to 24): sets the base address for the pci memory space in pio transfers. (initial value is undefined.) bits 23 to 1?reserved: these bits always return 0 when read. always write 0 to these bits when writing. bit 0?lock transfer ( lock): specifies the locking of the memo ry space during pio transfer. bit 0: lock description 0 not locked (initial value) 1 locked
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 917 of 1122 rej09b0370-0400 22.2.34 i/o space base register (pciiobr) bit: 31 30 29 28 27 26 25 24 iobr31 iobr30 iobr29 iobr28 iobr27 iobr26 iobr25 iobr24 initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 iobr23 iobr22 iobr21 iobr20 iobr19 iobr18 ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? lock initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r/w the i/o space base register (pci iobr) species the most significant 14 bits of the address of the pci i/o space when performi ng i/o read and i/o write operations by pio transf er. it also specifies locked transfers. this 32-b it read/write register can be accessed from the pp bus. all bits of the pcii0br register are initialized to 0 at a power-on reset. they are not initialized at a software reset. setting bit 0 (lock) to 1 locks the i/o space for pi o transfers while the bit remains set. a locked transfer consists of the combined read and write operations. do not attempt to perform other pio transfers during the lock ed combination of read and write operations.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 918 of 1122 rej09b0370-0400 always write to this register prior to i/o sp ace read and i/o space write operations by pio transfer. bits 31 to 18?i/o space base address ( iobr31 to 18): sets the base register for the pci i/o space in pio transfers. bits 17 to 1?reserved: these bits always return 0 when read. always write 0 to these bits when writing. bit 0?lock transfer ( lock): specifies the locking of the i/o space during pio transfer. bit 0: lock description 0 not locked (initial value) 1 locked 22.2.35 pci power management interrupt register (pcipint) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: ? ? ? . . . ? ? ? ? pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? pwrst_ d3 pwrst_ d0 initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r/wc r/wc note: cleared by setting wc: 1. (writing of 0 is ignored.) the pci power management interrupt register (pcipint) controls the power management interrupts. it provides the interrupt bits for a tr ansition to the power state d3 (power down mode) and recovery to the power state d0 (normal state) . this 32-bit read/write register can be accessed from the pp bus.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 919 of 1122 rej09b0370-0400 the pcipint register is initialized to h'00000000 at a power-on reset. it is not initialized at a software reset. when an interrupt is detected, the bit corresponding to the content of that interrupt is set to 1. each interrupt detection bit can be cleared to 0 by writing 1 to it (write clear). the power state d0 interrupt is no t generated at a power-on reset. bits 31 to 2?reserved: these bits always return 0 when read . always write 0 to these bits when writing. bit 1?power state d3 (pwrst_d3): transition request to power-down mode interrupt for this lsi. bit 0?power state d0 (pwrst_d0): restore from power-down mode interrupt for this lsi. note: the power states d3, d0 are not masked even when the interrupt mask bit is set on. 22.2.36 pci power man agement interrupt mask register (pcipintm) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: ? ? ? . . . ? ? ? ? pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? dperr_ wt dperr_ rd initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r/w r/w the pci power management interrupt mask register (pcipintm) sets the interrupt mask for the power management interrupts. this 32-bit read/wr ite register can be acces sed from the pp bus. the pcipintm register is initialized to h'00000000 at a power-on reset. it is not initialized at a software reset. interrupt masks can be set for both the interrupt for a transition to the power state d3 (power down mode) and recovery to the power state d0 (normal status). setting the respective bit to 0 disables the interrupt and setting it to 1 enables the interrupt.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 920 of 1122 rej09b0370-0400 bits 31 to 2?reserved: these bits always return 0 when read. always write 0 to these bits when writing. bit 1?power state d3 (dperr_wt): transition request to power-down mode interrupt mask for this lsi. bit 0?power state d0 (dperr_rd): restore from power-down mode interrupt mask for this lsi. 22.2.37 pci clock control register (pciclkr) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: ? ? ? . . . ? ? ? ? pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? pciclks top bclkst op initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r/w r/w the pci clock control register (pciclkr) controls the stopping of the local bus clock (bclk) in the pcic and the pci bus clock. this 32-bit read/w rite register can be acc essed from the pp bus. the pciclkr register is initialized to h'00000000 at a power-on reset. it is not initialized at a software reset. when the pci bus clock is input from the external input pin pciclk , the pci bus clock can be stopped by setting the pciclkstop bit to 1. likewise, the local bus clock can be stopped by setting the bclkstop bit to 1. when the pci bus clock is input via the ckio pin, setting bclkstop to 1 stops both the bck in the pcic and the feedback input clock from ckio. writing to this register is valid only when bits 31 to 24 are h'a5.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 921 of 1122 rej09b0370-0400 bits 31 to 2?reserved: these bits are always read as 0. when writing, always write h'a5 to bits 31 to 24, and 0 to the other bits. always write 0 to these bits when writing. bit 1?pciclk stop control ( pciclkstop): controls the stopping of the clock input via the pciclk pin. bit 1: pciclkstop description 0 pciclk input enabled (initial value) 1 stop pciclk input bit 0?bclk stop control ( bclkstop): controls the stopping of the bck input clock and ckio input clock in the pcic. bit 0: bclkstop description 0 bck input enabled (initial value) 1 stop bck input 22.2.38 pcic-bsc registers pcic bus control register 1 (pcibcr1) pcic bus control register 2 (pcibcr2) pcic bus control register 3 (pcibcr3)* 1 pcic wait control register 1 (pciwcr1) pcic wait control register 2 (pciwcr2) pcic wait control register 3 (pciwcr3) pcic discrete memory cont rol register (pcimcr) because pci bus data is stored, in the pcic, in memory on the local bus, the pcic is equipped with an internal bus controller (pcic-bsc). the pcic-bsc performs the same type of control as the slave function of the bus controller (bsc). however, the pcic-bsc returns bus rights to the bsc after each data transfer of up to 32 bytes of data. there are six registers in the pcic-bsc: pcibcr1 (equivalent to the bcr1 of the bsc), pcibcr2 (equivalent to the bcr2 of the bsc), pcibcr3 (equivalent to the bcr3 of the bsc)* 1 , pciwcr1 (equivalent to the wcr1 of the bsc), pciwcr2 (equivalent to the wcr2 of th e bsc), pciwcr3 (equival ent to the wcr3 of the bsc), and pcimcr (equivalent to the mcr of th e bsc). each is a 32-bit register. bcr2 and bcr3 are 16-bit registers, but pcibcr2 and pcibcr3 should be accessed by longword access. the low 16 bits of pcibcr2 and pcibcr3 corres ponds to the 16 bits of these registers, respectively. see section 13, bus state controller (bsc), for details of the initial values, etc.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 922 of 1122 rej09b0370-0400 ? the pcic-bsc performs the same operations as the slave mode of the bsc. therefore, the mater bit of the pci bus control register 1 (pcibcr1) shows the slave status. ? because the pcic-bsc operates in slave mode, the bus privile ge is handed to the bsc once per bus cycle. ? the external memory capable of data transfer s to the pci bus is sram, dram, synchronous dram, and mpx* 2 . ? the memory data width is 32-bit or 16-bit only (only 32-bit in the case of synchronous dram). ? do not specify other external memory types (burst rom, mpx, byte control sram or pcmcia) as the external memory for data transfers with the pci bus. ? because the pcic-bsc operates in slave mode, the ras-down mode of dram and sdram is not available. ? the local bus supports both big and little endian. however, the pci bus supports only little endian. the pci-bsc does not support mode register se tting of synchronous dram nor refreshing of synchronous dram or dram. these must be executed by the bsc. also, do not implement any settings that are not allowed in slave mode in the pcic-bsc registers. this is because bit 30: master/slave flag (mas ter) of the pcibcr1 is fixed low, regardless of the value of the external master/slave setting pi n (md7) at a power-on reset, and the pcic-bsc therefore is set in slave mode. in the case of external memory not used for da ta transfers with the pci bus, make the same settings as the corresponding bus state controller register. these registers are initialized at a power- on reset, but not by a software reset. notes: 1. this register is provided only in the sh7751r, not provided in the sh7751. 2. mpx is supported only in the sh7751r, not supported in the sh7751.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 923 of 1122 rej09b0370-0400 22.2.39 port control register (pcipctr) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? port2en port1en port0en initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? pb2pup pb2io pb1pup pb1io pb0pup pb0io initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r/w r/w r/w r/w r/w r/w the port control register (pcipctr) selects whethe r to enable or disable port function allocation for pins for unwanted pci bus arbitration when the pcic is used in non-host mode. it also specifies the swithing on/off of pin pull-up resistances and between input and output. this 32- bit read/write register can be accessed from the pp bus. the pcipctr register is initialized to h'00000000 at a power-on reset. it is not initialized at a software reset. when the pcic is operating as host, the port function cannot be used if the arbitration function is enabled.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 924 of 1122 rej09b0370-0400 bits 31 to 19?reserved: these bits always return 0 when r ead. always write 0 to these bits when writing. bit 18?port 2 enable (port2en): provides the enable control for the port 2. bit 18: port2en description 0 do not use pins pcignt4 or pcireq4 as ports (initial value) 1 use pins pcignt4 or pcireq4 as ports bit 17?port 1 enable (port1en): provides the enable control for the port 1. bit 17: port1en description 0 do not use pins pcignt3 or pcireq3 as ports (initial value) 1 use pins pcignt3 or pcireq3 as ports bit 16?port 0 enable (port0en): provides the enable control for the port 0. bit 16: port0en description 0 do not use pins pcignt2 or pcireq2 as ports (initial value) 1 use pins pcignt2 or pcireq2 as ports bits 15 to 6?reserved: these bits always return 0 when read. always write 0 to these bits when writing. bit 5?port 2 pull-up resistance control ( pb2pup): controls pull-up resistance when pcireq4 pin is used as port. bit 5: pb2pup description 0 pull-up pcireq4 pin (initial value) 1 do not pull-up pcireq4 pin bit 4?port 2 input/output control ( pb2io): controls input or output when pcireq4 is used as a port. bit 4: pb2io description 0 set pcireq4 pin for input (initial value) 1 set pcireq4 pin for output
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 925 of 1122 rej09b0370-0400 bit 3?port 1 pull-up resistance control ( pb1pup): controls pull-up resistance when pcireq3 pin is used as port. bit 3: pb1pup description 0 pull-up pcireq3 pin (initial value) 1 do not pull-up pcireq3 pin bit 2?port 1 input/output control ( pb1io): controls input or output when pcireq3 is used as a port. bit 2: pb1io description 0 set pcireq3 pin for input (initial value) 1 set pcireq3 pin for output bit 1?port 0 pull-up resistance control ( pb0pup): controls pull-up resistance when pcireq2 pin is used as port. bit 1: pb0pup description 0 pull-up pcireq2 pin (initial value) 1 do not pull-up pcireq2 pin bit 0?port 0 input/output control ( pb0io): controls input or output when pcireq2 is used as a port. bit 0: pb0io description 0 set pcireq2 pin for input (initial value) 1 set pcireq2 pin for output
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 926 of 1122 rej09b0370-0400 22.2.40 port data register (pcipdtr) bit: 31 30 29 . . . 11 10 9 8 ? ? ? . . . ? ? ? ? initial value: 0 0 0 . . . 0 0 0 0 pci-r/w: ? ? ? . . . ? ? ? ? pp bus-r/w: r r r . . . r r r r bit: 7 6 5 4 3 2 1 0 ? ? pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value: 0 0 0 0 0 0 0 0 pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r r r/w r/w r/w r/w r/w r/w the port data register (pcipdtr) inputs and ou tputs the port data when allocation of the port function to the unwanted pci bus arbitration pins is enabled when the pcic is operating in non- host mode. this 32-bit read/write regi ster can be accessed from the pp bus. the pcipdtr register is intialized to h'00000000 at a power-on reset. it is not initialized at a software reset. data is output in sync with the local bus clock. input data is fetched at the rising edge of the local bus clock. bits 31 to 6?reserved: these bits always return 0 when read. always write 0 to these bits when writing. bit 5?port 2 output data (pb5dt): output data when pcignt4 pin is used as port. ( pcignt4 pin is output-only.) bit 4?port 2 input/output data (pb4dt): receives input data and sets output data when the pcireq4 pin is used as a port. bit 3?port 1 output data (pb3dt): output data when pcignt3 pin is used as port. ( pcignt3 pin is output-only.) bit 2?port 1 input/output data (pb2dt): receives input data and sets output data when the pcireq3 pin is used as a port.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 927 of 1122 rej09b0370-0400 bit 1?port 0 output data (pb1dt): output data when pcignt2 pin is used as port. ( pcignt2 pin is output-only.) bit 0?port 0 input/output data (pb0dt): receives input data and sets output data when the pcireq2 pin is used as a port. 22.2.41 pio data register (pcipdr) bit: 31 30 29 28 27 26 25 24 ppda31 ppda30 ppda29 ppda28 ppda27 ppda26 ppda25 ppda24 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ppda23 ppda22 ppda21 ppda20 ppda19 ppda18 ppda17 ppda16 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ppda15 ppda14 ppda13 ppda12 ppda11 ppda10 ppda9 ppda8 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ppda7 ppda6 ppda5 ppda4 ppda3 ppda2 ppda1 ppda0 initial value: ? ? ? ? ? ? ? ? pci-r/w: ? ? ? ? ? ? ? ? pp bus-r/w: r/w r/w r/w r/w r/w r/w r/w r/w the pio data register (pcipdr) sets the data for read/write in the pci configuration cycle. this 32-bit read/write register can be accessed from the pp bus. the pcipdr register is not initialized at a power-o n reset or software reset. the initial value is undefined.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 928 of 1122 rej09b0370-0400 always write to this register before accessing th e pci configuration space. always read/write to this register after setting the value in the pio address register (pcipar). the configuration cycle on the pci bus can be generated by reading/writing to this register. bits 31 to 0?pio configuration data (ppda31 to 0): read/write register for configuration data in pio transfers. the configuration cycle on the pci bus can be generated by reading/writing to this register. 22.3 description of operation 22.3.1 operating modes the external mode pins (md9 and md10) select wh ether the pcic operates as the host on the pci bus and also select the bus clock for the pci bus. the mode selection signals input via the external mode pins are fetched on negation of a power-on reset. table 22.8 operating modes md9 md10 operating modes 0 the pcic host functions are enabled and the external input via the pciclk pin is the operating clock for the pci bus 0 1 the pcic host functions are enabled and this lsi bus clock (feedback input clock from ckio pin) is the operating clock for the pci bus 1 0 the pcic host functions are disabled (non-host) and the input clock from the pciclk pin is selected as the clock for the pci bus 1 pcic-disabled mode. in this mode, pcic operation is disabled note: in pcic-disabled mode , do not attempt to access t he pcic local registers. in this section, the clock resulting from the above mode switching is known as the pci bus clock.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 929 of 1122 rej09b0370-0400 22.3.2 pci commands table 22.9 lists the pci commands and shows the pcic support. table 22.9 pci command support host operation non-host operation command master target master target remarks memory read o o o o memory read line x x when the target, operates as memory read memory read multiple x x when the target, operates as memory read memory write o o o o memory write and invalidate x x when the target, operates as memory write i/o read o o o o i/o write o o o o configuration read o ? ? o configuration write o ? ? o interrupt acknowledge cycle x x x x special cycle o ? ? x dual address cycle x x x x legend: o: supported : limited support x, ?: not issued by pcic or no response from pcic when pcic operates as master: the pcic supports the memory read command, memory write command, i/o read command, and i/o write command . when the host functions are enabled, the configuration command and speci al cycle can also be used. when pcic operates as target: the pcic receives the memory read command, memory write command, i/o read command, and i/o write co mmand. the memory read line command and memory read multiple command function as memory reads, while the memory write invalidate command functions as a memory write. when opera ting in non-host mode, the pcic accepts the configuration command.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 930 of 1122 rej09b0370-0400 22.3.3 pcic initialization after a power-on reset, the configuration register initialization bit (cfinit) of the pci control register (pcicr) is cleared. at this point, if th e pcic is operating as the pci bus host, the bus privileges are permanently granted to the pcic, and no device arbitration is performed on the pci bus. when the pcic is not operating as host, retries are returned without accepting access from pci devices connected to the pci bus. the pcic's internal configuration registers and local registers must be initialized while the cfinit bit is cleared to 0. on completion of initialization, set the cfinit bit to 1. when operating as host, arbitration is enabled; when operating as non-host, the pcic can be accessed from the pci bus. regardless of whether or not the pcic is operating as host, external pci devices cannot be accessed from the pcic while the cfinit bit is cleared. if the pcic's internal configuration registers and local registers are initialized correc tly, the pcic will operate correctly. however, we recommend first setting the cfinit bit to 1. when the pcic is operating as the host, arbitra tion is enabled. when operating as non-host, the pcic can be accessed from the pci bus. regardless of whether the pcic is operating as th e host or non-host, external pci devices cannot be accessed from the pcic while the cfint bit is being cleared. set the cfinit bit to 1 before accessing an external pcic device. be sure to initialize the following 13 registers while the cfinit bit is being cleared: configuration registers 1, 2, 11 (pciconf1, 2, 11) for pci, local space regist ers 0, 1 (pcilsr0, 1) for pci, local address registers 0, 1 (pcilar0, 1) for pci, pci bus control registers 1, 2 (pcibcr1, 2) for pcic-bsc, pci weight control registers 1, 2, 3 (pciwcr1, 2, 3), and pci-specific memory control register (pcimcr). since the pcic-bsc is fixed in sleep mode at a power-on reset regardless of the value of the external pin (md7) for master/slave designation, do not make a pcic-bsc register setting that is prohibited in the sleep mode. also, as the bsc has bcr1.breqen bits that enable an external request and a bus request from the pcic to be accepted, bcr1 .breqen should be set to 1 when the pcic is used. while 1 is being set in the cfinit bit, the registers for the pcic-b sc (pcibcr1, 2, pciwcr1, 2, 3, pcimcr) cannot be written to. the data tr ansfer accuracy between th e pci bus and local bus cannot be guaranteed if an attempt is made to write to any of these registers during this period.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 931 of 1122 rej09b0370-0400 22.3.4 local register access only longword (32-bit) access of the pcic's internal local re gisters and configuration registers from the cpu is supported. (it is possible to use pio transf ers to perform byte, word, and longword access of the memory space and i/o space on the pci bus.) if an attempt is made to access these registers us ing other than the prescr ibed access size, zero is returned when reading and writing is ignored. the same is true if you attempt to access the reserved areas in the re gister area in the pcic. some of the configuration registers and local registers can be accessed both from the cpu and from the pci device(s). therefore, arbitration is performed for both types of access and either the cpu or pci device access made to wait according to the access timing. in the read bus cycle from the cpu, the internal bus cycle for the peripheral module is made to wait until the data is actually ready. in the write bus cycle, the bus cycle of the internal bus for peripheral modules ends with the data having been written to the interface (register located immediately after the pcic input) register on the in ternal bus for peripheral modules, but the data is not actually written to the local register(s) or pci bus until the following clock cycle. if it is necessary to check that the data has actually been written, read the register to which the data was to have been written. this is because the read cy cle must be after the wr ite cycle has completed. when accessing from a pci device, the pci bus cycl e is caused to wait until the read or write operation has actually completed. the internal bus for peripheral m odules used for read/write operatio ns from the cpu operates only with big endians. 22.3.5 host functions the pcic has the following pci bus host functions (host devices): ? inter-pci device arbitration function ? configuration regi ster access function ? special cycle generation function ? reset output function ? clock output function
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 932 of 1122 rej09b0370-0400 inter-pci device arbitration: the pci bus arbitration circuit in the pcic can be used when the pcic is operating as the host device. the arbitration circuit can be connected to up to four external pci devices (devices that ca n operate as master devices) that request bus privileges. if multiple bus privilege requests are made simultaneously by the pci devices, the bus privilege is grated in the predetermined order of priority. there are two orders of priority: fixed, and pseudo round robin. the mode is selected by setting the bus master arbitration mode control bit (bmabt) of the pci control register (pcicr). ? priority-fixed mode (bmabt = 0) in priority-fixed mode, the priority order of bus privilege requests is fixed and cannot be changed. the order is as follows: pcic (device 0) > device 1 > device 2 > device 3 > device 4 that is, the pcic has the highest order of priority and device 4 has the lowest. when bus privilege requests occur simultaneously, the device with the highest order of priority takes precedence. here, device 1 is the pci device using bus privilege request pins pcireq1 and pcignt1 , device 2 uses pcireq2 and pcignt2 , device 3 uses pcireq3 and pcignt3 , and device 4 uses pcireq4 and pcignt4 . when the pcic is operatin g as the host device, no bus privilege request signals are output from the pcic to the pci bus arbitration circuit. ? pseudo round-robin mode (bmabt = 1) in pseudo round-robin mode, when a device takes the bus privilege, the priority order of that device becomes lowest. in the initial state, the priority order is set to the same as in the fixed mode. here, device 1 outputs a bus privilege request, after which the priority order changes to ? pcic > device 2 > device 3 > device 4 > device 1. if the pcic then outputs a bus privilege request and takes the bus privilege, the priority order changes to ? device 2 > device 3 > device 4 > device 1 > pcic. likewise, if device 3 outputs a bus privilege request and takes the bus privilege, the priority order becomes ? device 2 > device 4 > device 1 > pcic > device 3. in this way, the priority order of the master device that takes the bus privilege always changes to lowest after the data transfer is completed.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 933 of 1122 rej09b0370-0400 initial order of priority (transfer by device 1) pcic > device 1 > device 2 > device 3 > device 4 order of priority after transfer (transfer by pcic) pcic > device 2 > device 3 > device 4 > device 1 order of priority after transfer (transfer by device 3) device 2 > device 3 > device 4 > device 1 > pcic order of priority after transfer device 2 > device 4 > device 1 > pcic > device 3 1. 2. 3. 4. when the pcic is operating as the host device, the pcic performs the pci bus parking (bus drive when not in use). when 3 or fewer master devices are connected, set the level of the unused pins of pcireq [4:1] high. in non-host mode, the pci bus arbitration function of the pcic is disabled. pci bus arbitration is performed according to the specifications of the connected pci bus arbiter. for details, see section 22.3.6, pci bus arbitration in non-host mode. configuration register access: the configuration register of external pci devices can be accessed when the pcic is operatin g as the host device. the pio address register (pcipar) and pio data register (pcipdr) are used to generate a configuration read/write transfer for accessing the configuration register. the pcic supports the configuration mechan ism stipulated in the pci local bus spec. first, specify in the pcipar the address of the configuration regist er of the external pci device to be accessed. see section 22.2, pcic register descriptions, for ho w to set the pcipar. next, read data from the pcipdr or write data to the pcipdr. only longword (32-bit) access of the pcipdr is supported. special cycle generation: when the pcic operates as the host device, a special cycle is generated by setting h'8000ff00 in the pcipar and writing to the pcipdr. reset output: when the pcic is opera ting as the host device, pcirst can be used to reset the pci bus. see section 22.5, resetting, for details of pcirst . clock output: when the pcic is operating as the host device and the bus clock (ckio pin) is selected as the pci bus clock, not only does the pcic's pci bus clock operate using the ckio clock but the ckio clock can also be used as the pci bus clock. thus, there is no requirement for an external pci clock oscillation circuit.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 934 of 1122 rej09b0370-0400 when using the ckio clock, please note the limitations on ckio clock frequency, stability, and load capacitance that can be co nnected to the ckio pin. check the clock oscillation circuit and electrical characteristics in section 10, clock oscillation circuits, and section 23, electrical characteristics. 22.3.6 pci bus arbitration in non-host mode when operating in non-host mode, the pci bus arbitration function in the pcic is disabled and pci bus arbitration is performed according to th e specifications of the ex ternally connected pci bus arbiter. in this case, the pcic must request pci bus pr ivileges from the pci bus arbiter (system host device). the pcignt1 / reqout pins are used for the bus request signals, and the pcireq1 / gntin pins are used for the bus grant signals. when the bus grant signals are asserted when the bus request signals are not asserted, the pcic performs bus parking. also, when the pcic is used as a target de vice that does not request bus privileges, the pcireq1 / gntin pins must be fixed at the high level. 22.3.7 pio transfers pio transfer is a data tr ansfer mode in which a peripheral bu s is used to access the memory space and i/o space of the pci bus. the following commands are supp orted in pio transfer mode: ? memory read, memory write, i/o read, and i/o write ? locked transfer (high-speed back-to- back transfers are not supported.) in pio transfer mode, only single transfers are supported. 32-byte burst transfers are not supported. in memory transfers and i/o transfers, the supported, so generate byte enable signals ( be[3:0] ) to match the respective access sizes and output these signals to the pci bus. access sizes are byte, word, and longword. locked transfers are supported only in the case of memory transfers and i/o transfers. high-speed back-to-back transfers are not supported.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 935 of 1122 rej09b0370-0400 memory transfers: this section describes how pio transf ers are used to access memory space. 16mb between h'fd000000 and h'fdffffff of area p4 (h'1d000000 to h'1dffffff in area 7) is allocated as pci memory ad dress space. this space is used as the least significant 24 bits of the pci address. however, in memo ry transfers, the two low bits of the pci address are ignored, and b'00 is output to the pci bus. the most si gnificant 8 bits (mbr [31:24]) of the memory space base register (pcimbr) are used as the most significant bits of the pci address. these two addresses are combined to specify a 32-bit pci address. to transfer to the memory space, first specify the most significant 8 bits of the pci address in the pcimbr, then access the pci memo ry address space. if within the 16mb space, the pci memory address space can be consecutively accessed simply by setting the pcim br once. if it is necessary to access an address space over the 16mb, set pcimbr again. when performing locked transf ers in memory transfer mode, set the pcimbr memory space lock specification bit (lock). while the lock bit is set, the memory space is locked. note the following when pe rforming lock transfers: ? a lock transfer consists of one read transfer and one write tr ansfer. always start with the read transfer. the system will operate correctly if you start with a write transfer, but the resource lock will not be established. also, th e system will operate correctly if you perform two lock read transfers, but the lock will be released at the next lock write transfer. ? the minimum resource for which the lock is gu aranteed is a 16-byte block. however, the system will operate correctly even if lock tr ansfers are made to addresses other than where the lock is established. ? you cannot access other targets while a target is locked (from the lock read until the lock write). ? pio lock access of another target ends norm ally and transfers on the pci bus are also generated. ? unlocked pio transfer reque sts invoked between a lock read and lock write end normally, but no transfers are generated on the pci bus. ? dma transfers are postponed un til the lock transfer ends.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 936 of 1122 rej09b0370-0400 pci memory space address pci memory space h'fd000000 h'fdffffff 16 mbytes 31 24 23 0 31 24 23 0 31 24 23 0 pci address lock identifier pcimbr h'fd 2 00 figure 22.2 pio memory space access i/o transfers: this section describes how to access i/ o space using pio tran sfers. the 256kb from h'fe240000 to h'fe27ffff of area p4 (h'1e2 40000 to h'1e27ff ff in area 7) is allocated as pci i/o address space. this space is used for th e least significant 18 bi ts of the pci address. the most significant 14 bits (iobr [31:18]) of th e i/o space base register (pciiobr) are used as the most significant 14 bits of the pci address. these two addresses are combined to specify the 32-bit pci address. for transfers to the i/o space, first specify the mo st significant 14 bits of the pci address in pciiobr, then access the pci i/o address space. if within the 256kb space, you can access the pci i/o address space consecutivel y simply by setting the pciiobr once. if it is necessary to access another address space beyon d 256kb, set pciiobr again. when performing locked transfer s in i/o transfers, set the i/o space lock specification bit (lock) in the pciiobr. the i/o space is locked while th e lock bit is set. the same precautions apply to lock i/o transfers as to lock memory transfers.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 937 of 1122 rej09b0370-0400 pci i/o space address pic i/o space h'fe240000 h'fe27ffff 256 kbytes pci re g ister space h'fe200000 h'fe23ffff 256 kbytes 31 18 17 0 31 18 17 0 31 18 17 0 pci address lock identifier pciiobr h'fe24?h'fe27 figure 22.3 pio i/o space access pio transfer error: an error on the pci bus that occurs in a transfer during a pio write operation is not detected. when an error is generate d during a pio read oper ation, the pio transfer is forcibly terminated to prevent effects on the dma transfer and target transfer. however, accuracy of the read data is not guaranteed. 22.3.8 target transfers the following commands are av ailable for transferring data in target transfers. ? memory read and memory write ? i/o read and i/o write (access to pcic local registers) ? configuration read, configuration write ? locked transfer is supported. ? high-speed back-to-back, is not supported. when the pcic is operating in non-host mode, no response is made on reception of special cycle commands. memory read/memory write commands: in the case of memory read and memory write commands, both single transfers and burst transfers are supported on the pci bus. data on the pci bus is always longword data, but be[3:0] can be used to control the valid byte lane. in the case of memory read, longword data is always read from the local bus and output to the pci bus. in the
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 938 of 1122 rej09b0370-0400 case of memory write, the internal control allows only the writing of valid byte lane data to the local bus. only the linear mode is supported for addressing for burst transfers, and the 2 least significant bits of the pci a ddress are regarded as b'00. if a memory read line command or memory read multiple command is received, they operate as memory reads. similarly, when a memory write invalidate command is received, it functions as a memory write. data must be set in the following registers prior to performing target transfers using memory read or memory write commands: pci configuration register 5 (pcicnf5), pci configuration register 6 (pcicnf6), pci local space register 0 (pcils r [0]), pci local space register 1 (pcilsr [1]), pci local address register 0 (pcilar [0]), an d pci local address register 1 (pcilar [1]). pciconf5 (pciconf6) pcilsr0 (pcilsr1) pcilar0 (pcilar1) 31 20 19 0 31 0 31 28 20 19 0 31 28 20 19 0 31 28 0 000001111 pci address local address pcic access adjudication figure 22.4 local addres s space accessing method the pcic supports two local address sp aces (address space 0 and address space 1). a certain range of the address space on the pc i bus corresponds to th e local address space. the local address space 0 is controlled by the pciconf5, pcilar0 and pcisr0. figure 22.4 shows the method of accessing the local address space.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 939 of 1122 rej09b0370-0400 the pciconf5 indicates the star ting address of the memory space used by the pci device. the pcilar0 specifies the starting address of the lo cal address space 0. the pcilsr0 expresses the size of the memory used by the pci device. regard ing the method of setting each register, refer to section 22.2, pcic register descriptions. for the pciconf5 and pcilar0, the most significant address bit that is higher than the memory size set in the pcilsr0 becomes valid. the most significant address bit of the pciconf5 and the pci address output from an external pci devi ce are compared for the purpose of determining whether the access is made to the pcic. when th e addresses correspond, the access to the pcic is recognized, and a local address is generated from the most significant address bit of the pcilar0 and the least significant bit of the pci address output from the external pci device. the pci command is executed for this local address. if the most significant address bit of the pci address output from the external pci device does not correspond with the most significant address bit of the pciconf5, the pcic does not respond to the pci command. address space 1 is, like address space 0, controlled by the pcic onf6, pcilsr1, and pcilar1. in this way, it is possible to se t two address spaces. in systems with two or less local bus areas that can be accessed from the pci bus, separate addr ess spaces can be allocated to each of them. to make it possible to access two or more areas from the pci bus, set the address spaces so that multiple areas are covered. in this case, we can assume that the address space includes areas for which no memory is installed. note that, in this case, it is not possible to disable target transfers to areas for which no memory is installed. note: see 22.3.11 (2), target read/write cycle timing. i/o-read and i/o-write commands: the local registers of the pc ic are accessed by means of a target transfer triggered by an i/o-read or i/o-write command. in the sh7751, acce ssing the local registers by means of i/o transfer is made possible by setting a base address that specifies 1 mbyte of i/o space* in pci configurati on register 4 (pciconf 4). in the sh7751r, a base address that specifies 256 bytes of i/o space should be set. i/o-read and i/o-write commands only supports single transfers. the values of the byte-enable signals ( be [3:0]) are ignored, and longword accesses are carried out inside the pcic. when executing an i/o-read and i/o-write comm ands transfer, spec ify b'0000 as the be [3:0] value. note that some of the local registers are not acce ssible from the pci bus. for details, see section 22.2, pcic register descriptions.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 940 of 1122 rej09b0370-0400 note: * in version 2.1 of the pci specifications the i/o space for pci devices is defined as being no more than 256 bytes. as a result, when the sh7751 is used in a pci non-host device, for example on an add-in card, it may be identified as an unusable device during device configuration because it requ ires an i/o space larger than 256 bytes. configuration-read and configuration-write commands: when the pcic operates as a non- host device, the configuration re gisters of the pcic are accessed by using configuration-read and configuration-write commands. configuration access only su pports single transfers. in the sh 7751, the values of the byte-enable signals ( be [3:0]) are ignored, and longword accesses ar e carried out inside the pcic*. in the sh7751r, the values of be[3:0] are enabled. when executing a configuration-write operation, specify b'0000 as the be [3:0] value. note: * version 2.1 of the pci specifications sp ecifies that any combination of byte-enable signal ( be[3:0] ) values must be allowed when acce pting a configuration access. as a result, when byte or word access is specified by the combination of be[3:0] , the remaining portion of the data in the longword unit is also overwritten by the write operation. locked transfer: locked transfers are supported, but the locked space becomes the whole memory of the pcic in the case of memory transf ers, and becomes the whol e register space in the case of i/o transfers or configurat ion transfers. while the memory is locked, retry is returned for all memory accesses of the pcic from other pc i devices. register access is, however, accepted. similarly, while the registers are locked, retry is returned for all i/o accesses or configuration accesses of the pcic from another pci device, but memory access is accepted. 22.3.9 dma transfers dma transfers allow the high-speed transfer of data between devi ces connected to the local bus and pci bus when the pcic has bus privileges as master. the following commands are supported in the case of dma transfers: ? memory read, memory write, i/o read, and i/o write (locked transfers are not supported.) (high-speed back-to-back tr ansfers are not supported.) there are four dma channels. in each channel, a maximum of 64mb can be set for each transfer, the number of transfer bytes and the starting addr ess for the tran sfer being set at a longword boundary.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 941 of 1122 rej09b0370-0400 in dma transfers, all transferred data is handled in long word un its, so the number of transfer bytes and the low 2 bits of the transfer initial ad dress are ignored and b'0000 is always output for be[3:0] . also, in dma transfers, because burst transfers are effected using linear addressing, the low 2 bits of the output pci address are always b'00. note that locked transfers are not s upported in the case of dma transfers. starting dma transfer: the following registers exist to control dma transfers: pci dma transfer arbitration register (pcidmabt) and, for four channels, the pci dma transfer pci address register [3:0] (pcidpa [3:0]), pci dma tran sfer local bus starting address register [3:0] (pcidla [3:0]), pci dma transfer count regist er [3:0] (pcidtc [3:0]), and pci dma control register [3:0] (pcidcr [3:0]). set the arbitration mode in pcidmabt prior to starting the dma transfer. also select the dma channel to be used, set the pci bus starting address and local bus starting address in the appropriate pcidpa and pcidla fo r the selected channel, respectiv ely, set the number of bytes in the transfer in pcidtc, set th e dma transfer mode in the pcid cr, and specify a transfer start request. the transfer starting addre ss and the number of bytes in the transfer can be set on byte or word boundaries, but because the least significant two bits of these registers are ignored, the transfer is performed in longword units. also, note that the local bus starting address set in pcidla is the physical address. pcidpa, pcidla, and pcidtc are updated during data transfer. if another dma transfer is to be performed on completion of one dma transfer, new values must be set in these registers. the registers controlling dma transfers can be set from both cpu and pci device. note that the dma channel allocated to the cpu and pci device must be predetermined when configuring the system. when performing dma transfers, the address of the local bus and the size of data to be transferred can be set to a 32-byte boundary to ensure that data transfers on the local bus are as efficient as possible. pcidcr can be used to control the abortion of dma transfers, the direction of dma transfers, to select pci commands (memory/i/o) whether to update the pci address, whether to update the local address, whether to use tran sfer termination interrupts, and, when the local bus is big endian, the method of alignment. figure 22.5 shows an example of dm a transfer control register settings.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 942 of 1122 rej09b0370-0400 31 pcidmabt h'0000 0000 h'0000 0004 h'1bff fffc h'0000 0000 h'0000 0004 h'0000 000c h'ffff fffc arbitration mode external memory space pci memory/ i/o space dma transfer 32 bits 0: fixed priority 1: pseudo round-robin 0 1 31 28 pcidla 0 31 26 25 pcidtc 0 31 pcidpa 0 31 11 10 pcidcr 0 transfer control pci address transfer count local address area 0: h'00000000 to h'03ffffff area 1: h'04000000 to h'07ffffff area 2: h'0800 0000 to h'0bffffff area 3: h'0c000000 to h'0fffffff area 4: h'10000000 to h'13ffffff area 5: h'14000000 to h'17ffffff area 6: h'18000000 to h'1bffffff 32 bits . . . . . . . . . . . . . figure 22.5 example of dma tr ansfer control register settings
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 943 of 1122 rej09b0370-0400 dma transfer end: the following describes the status on termination of a dma transfer. ? normal termination dma transfer ends after the set number of bytes has been transf erred. in the case of normal termination, the dma end status bit (dmast) of the pcidcr and the dma transfer start control bit (dmastart) are cleared, and the dm a transfer termination interrupt status bit (dmais) is set. if the dma transfer interrupt mask bit (dmaim) is set to 1, the dma transfer termination interrupt is issued. note that the dmais bit is set even if the dmaim bit is set to 0. the dmais bit is maintained until it is cleared. therefore, the dm ais bit must be cleared before starting the next dma transfer. ? abnormal termination the dma transfer may terminate abnormally if an error on the pci bus is detected during data transfer or the dm a transfer is forcibly terminated. ? error in data transfer when an error occurs during dma transfer, the dma transfer is forcibly terminated on the channel in which the error occurred. there is no effect on data transfers on other channels. ? forced termination of dma transfer when the pcidcr and dmastop bits for a channe l are set, data transfer on that channel is forcibly terminated. however, when the dmastop bit is set, do not write 1 to the dmastrt bit. also, in control bits other than the dmastop bit, write the value at the time of transfer started. in the case of an abnormal te rmination, the dma termination status bit (dmast) in the pcidcr is set when the cause of that abnormal termination (error detection or forced termination of dma transfer) occurs. after the da ta transfer terminates, the dma transfer start control bit (dmastart) is cleared and the dm a transfer termination interrupt status bit (dmais) is set. if the dma transfer interrupt mask bit (dmaim) is set to 1, the dma transfer termination interrupt is issued. in the event of an abnormal termination, the transferred data is not guaranteed. figure 22.6 shows an example of dma transfer flowchart.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 944 of 1122 rej09b0370-0400 dma transfer start dma transfer ( ? fifo) transfer address update transfer count decrement is transfer error detected? dmastop = 1? pcidtc > 0? dmast = 0 normal endin g dmast = 1 abnormal endin g yes yes yes no no no dma transfer starts when 1 is set in the dmastrt bit of the pcidcr re g ister. the pcidpa and pcidla re g isters are updated (increment/fixed) by the lahold bit of the pcidcr re g ister. the pcidtc decrements at a rate equalin g the number of transfer bytes (4 bytes). after dma transfer completion, the dmastrt bit of the pcidcr re g ister is cleared to 0, and the dmais bit of the pcidcr re g ister is set to 1. dma transfer is forcibly stopped when 1 is set in the dmastop bit of the pcidcr re g ister. (do not set 1 in the dmastrt bit at the same time.) figure 22.6 example of dma transfer flowchart
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 945 of 1122 rej09b0370-0400 ? termination by software reset when the rstctl bit of the pcicr is asserted , the pcic is reset and dma transfers are forcibly terminated. note, however, that when tran sfers are terminated by a software reset, the pcidcr is also reset and the dma transf er control registers are all cleared. dma arbitration: if transfer requests are made simultaneously on multiple dma channels in the pci, transfer arbitration is requ ired. there are two modes that can be selected to determine order of priority of the dma transfers on the four channels: fixed order of priority and pseudo round- robin. the mode is selected using the dmabt bit of the pci's dma transfer arbitration register (pcidmabt). for arbitration to be performed in such a way as to maintain high-speed da ta transfer, there are 4 fifos (32-byte 2 buffer structure) for the four dma transfer channels. the fifos have a 2- buffer structure, enabling one buffer to be accessed from the pci bus while the other is being accessed from the local bus. dependin g on the direction of the transf er, the input port of the fifo for dma transfers. transf ers are possible in both directions between the local bus and pci bus by selecting the transfer direction. the arbitration circuit monitors the data transfer requests (data write requests to the fifo when the fifo is empty and read requests from the fifo when it is full) 4 dm a transfer channels to control the data transfers. for each transfer request, a transfer of up to 32 bytes of data is performed. if a dma transfer request occurs at the same time as a pio transfer request , the pio transfer takes precedence over transfers on the four dma channels, regardless of the specified mode of dma transfer prio rity order. fixed priority mode (dmabt = 0): in fixed priority mode, the order of priority of data transfer requests is fixed and cannot be changed. the order is as follows: channel 0 dma transfer > channel 1 dma transfer > channel 2 dma transfer > channel 3 dma transfer dma transfer on channel 0. take the highest priority and channel 3 dma transfers take the lowest priority. when data tran sfer requests occur simultaneousl y, the data transfer with the highest priority takes precedence. let's look at data transfers from the local bus to the pci bus in fixed priority mode. the arbitration circuit monitors the transfer requests from the re spective data transfer co ntrol circuits and writes data read from the local bus to the data transfer fifo that not only is empty but also has the highest priority.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 946 of 1122 rej09b0370-0400 on the other hand, it checks if transfer data exists in the respective fifos an d reads that data from the data transfer fifo in which there is data and which has the highest priority, and outputs that data to the pci bus. for example, if channel 1 fifo is empty, the arbitration circuit writes the data from the local bus into the channel 1 fifo. next, if data of 32 bytes or more is in the channel 1 fifo, it outputs that data to the pci bus. if data has been written to both buffers of the channel 1 fifo, the channel 1 fifo is busy while data is output from one of those buffers to the pc i bus. while it is busy, data is written from the local bus to the channel 2 fifo, which has the next highest order of priority. when all data has been output from the channel 1 fifo to the pci bus, data is output from the channel 2 fifo, which still contains data, to the pci bus. thus, in fixed priority mode, execution alternates between the two data transfers with the highest priority. that is, if dma transfers are performed simultaneously on 4 channels, the data transfers start with alternation between channels 1 and 2 and then mo ve to alternating between 2 and 3 when all the data in channel 1 has been transferred. likewise, execution moves to alternation between channels 3 and 4 on completion of channel 2. this pattern is the same when data is tran sferred from the pci bus to the local bus. pseudo round-robin mode (dmabt = 1): in pseudo round-robin mode, as each time data is transferred, the order of priority is changed so that the priority level of the completed data transfer becomes the lowest. regarding pseudo round-robin mode operations, refer to section 22.3.5, host functions. 22.3.10 transfer contention within pcic no contention occurs in the pcic in the case of pio transfer requests from the cpu and memory reads/memory writes due to target transfers. this is because pio transfers use an internal bus for peripheral modules, and this operates independently of the local bus that has memory accessed by external pci devices. contention can occur in the pc ic in the case of pio tr ansfer requests from the cpu and io reads/io writes du e to target transfers (pcic local register access). in this case, however, arbitration is performed in the pcic such that priority is given to register access by the external pci device that has the pci bus rights.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 947 of 1122 rej09b0370-0400 22.3.11 pci bus basic interface the pci interface of the mcu supports a subset of version 2.1 of the pci specifications and enables connection to a device with a pci bus interface. while the pcic is set in host mode, or while set in non-host mode, operation differs according to whether or not bus parking is performed, and whether or not the pci bus arbiter function is enabled or not. in host mode, the ad, par, c/ be signal lines are driven by the pcic when transfers are not being performed on the pci bus (bus parking). when the pcic subsequently starts transfers as master, these signal lines continue to be driven until the end of the address phase. however, in non-host mode, the master performing parking is determined according to the gnt output by the external arbiter. when the master performing parking is not the sa me master as that starting the subsequent transfer, a high impedance state of at least one clock is generated prior to the address phase. in host mode, the arbiters in the pcics an d the req and gnt between pcics are connected internally. here, pins pcireq1 / gntin , pcireq2 /md9, pcireq3 /md10, and pcireq4 function as the req inputs from the ex ternal masters 1 to 4. similarly, pcignt1 / reqout , pcignt2 , pcignt3 , and pcignt4 function as the gnt outputs to external masters 1 to 4. including the pcic, arbitration of up to five masters is possible. in non-host mode, pins pcireq1 / gntin functions as the gnt input of the pcic, while pcignt1 / reqout functions as the req output of the pcic. master read/write cycle timing: figures 22.7 is an example of a single-write cycle in host mode. figure 22.8 is an example of a single read cycle in host mode. figure 22.9 is an example of a burst write cycle in non-host mode. and figure 22 .10 is an example of a burst read cycle in non- host mode. note that the response speed of devsel and trdy differs according to the connected target device. in pio transfers, always us e single read/write cycles. the issuing of configuration transfers is only possible in host mode. lock transfers are possible only using pio transfers.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 948 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin , pcireq2 ? pcireq4 le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable pcignt1 / reqout , pcignt2 ? pcignt4 addr d0 com be0 ap dp0 locked figure 22.7 master write cy cle in host mode (single)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 949 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin , pcireq2 ? pcireq4 le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable pcignt1 / reqout , pcignt2 ? pcignt4 addr d0 com be0 ap dpn locked figure 22.8 master read cy cle in host mode (single)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 950 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable pcignt1 / reqout addr d0 d1 dn com be0 be1 ben ap dp0 dp n-1 apn figure 22.9 master memory write cycle in non-host mode (burst)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 951 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable pcignt1 / reqout addr d0 d1 dn com be0 be1 ben ap dp0 dp n-1 dpn figure 22.10 master memory read cycle in non-host mode (burst)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 952 of 1122 rej09b0370-0400 target read/write cycle timing: the pcic responds to target memory read accesses from an external master by retries until 8 longword data are prepared in the pcic's internal fifo. that is, it always responds to the first target read with a retry. also, if a target memory write access is made, the pcic responds to all subsequent target memory accesses with a retry until the write data is comple tely written to local me mory. thus, the content of the data is guaranteed when data written to th e target is immediately subject to a target read operation. the following restrictions apply to the sh7751. with the sh7751r, in the following case the values of data are discarded for a target read that is executed immediately after a target write because the data read in an earlie r read operation that was carried out by a different pci device are discarded. [restrictions] in a system in which access is made to the same address* 1 in local memory by two or more pci devices, the data cannot be guaranteed when a targ et read is performed immediately after a target write. the possibility of an error occurs when the target read immediately after the target write gets bus privileges at the point the data is ready for a target read by a different pci device prior to the target write. in this case, the data prior to the target wr ite is read. if such tran sfers are likely to occur, implement either (a) or (b) below. (a) if using the data that has been read, perform two read operations and use only the data from the second read operation. (b) if not using the data that has been read (if you are performing the read operation in order to determine the timing for actually writing data to the destination), be sure that the read address* 2 immediately after writing is different from the write address. notes: 1. address matching ad[31:2] in the address phase. 2. the address that does not correspond to the address ad[31:2] on a longword boundary. only single transfers are supported in the case of target accesses of the configuration space and i/o space. if there is a burst access request, the ex ternal master is disconnected on completion of the first transfer. note that the devsel response speed is fi xed at 2 clocks (medium) in the case of target access of the pcic.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 953 of 1122 rej09b0370-0400 figure 22.11 shows an example target single read cycle in non-host mode. figure 22.12 shows an example target single write cycl e in non-host mode. figure 22.13 is an example of a target burst read cycle in host mode. and figu re 22.14 is an example target burst write cycle in host mode. pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin pcignt1 / reqout addr d0 be0 dp0 ap pcistop com locked at confi g access le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable disconnect figure 22.11 target read cycle in non- host mode (single)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 954 of 1122 rej09b0370-0400 pciclk ad31 ? ad0 pa r c/ be 3 ? c/ be 0 pciframe irdy devsel trdy pcilock idsel pcireq1 / gntin pcignt1 / reqout addr be0 ap pcistop com d0 dp0 locked at confi g access le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable disconnect figure 22.12 target write cycle i n non-host mode (single)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 955 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel pcistop idsel pcireqn pcigntn addr d0 be0 dp0 ap pcilock com be1 ben d1 dn dpn-1 dpn trdy le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable locked disconnect figure 22.13 target memory re ad cycle in host mode (burst)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 956 of 1122 rej09b0370-0400 pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy pcilock idsel pcireqn pcigntn addr dn d1 d0 be0 dp0 ap dp n-1 dpn pcistop com be1 ben le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable locked disconnect figure 22.14 target memory wr ite cycle in host mode (burst)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 957 of 1122 rej09b0370-0400 address/data stepping timing: by writing 1 to the wcc bit (bit 7 of the pciconf1), a wait (stepping) of one clock can be inserted when the pcic is driving the ad bus. as a result, the pcic drives the ad bus over 2 clocks. this function can be used when there is a heavy load on the pci bus and the ad bus does not achieve the stipulated logic level in one clock. when the pcic operates as the host, it is reco mmended to use this function for the issuance of configuration transfers. figure 22.15 is an example of burst memory write cycle with stepping. figu re 22.16 is an example of target burst read cycle with stepping. pciclk ad31?ad0 pa r c/ be3 ?c/ be0 pciframe irdy devsel trdy com be0 ben ap dp0 dpn-1 dpn addr d0 dn legend: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable figure 22.15 master memory write cycle in host mode (burst, with stepping)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 958 of 1122 rej09b0370-0400 pciclk ad31?ad0 par pciframe irdy devsel trdy le g end: addr: pci space address dn: nth data ap: address parity dpn: nth data parity com: command ben: nth data byte enable addr ben ap dp0 dpn-1 dpn com d0 dn be0 c/ be3 ?c/ be0 figure 22.16 target memo ry read cycle in host mo de (burst, with stepping)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 959 of 1122 rej09b0370-0400 22.4 endians 22.4.1 internal bus (peripheral bus) interface for peripheral modules the internal bus (peripheral bus) for the periphera l modules that write data from cpu to the pcic registers operates in big endians. on the other ha nd, pci bus operates in little endian. therefore, big/little endian conversion is required in pio tr ansfer, as shown in figure 22.17. the pcic supports two endian conversion modes, the byteswap bit of the pci control register (pcicr) switching between these modes. peripheral bus bi g endian 32 bits 32 bits 32 bits 32 bits little endian pci bus bi g little little bi g figure 22.17 endian conver sion modes for peripheral bus 1. byte data boundary mode: big/little endian conversion is performed on the assumption that all data is on byte boundaries. (byteswap = 1) 2. word/longword (w/lw) boundary mode: big/little endian conv ersion is performed according to the size of data accessed. (byteswap = 0) table 22.10 shows the access sizes supported by the conversion modes at the destination of peripheral bus access. the local registers in the pcic are always accessed in the word/longword boundary mode regardless of the transfer mode. figure 22.18 shows the data alignment between peripheral bus and pci bus in each boundary mode.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 960 of 1122 rej09b0370-0400 table 22.10 access size transfer mode access destination access size w/lw boundary mode byte data boundary mode memory space b, w, lw yes yes i/o space b, w, lw yes yes pci external device configuration register lw yes yes pcic register lw yes w/lw boundary mode legend: b: byte w: word lw: longword size address data data (w/lw boundary mode) address (memory i/o) be[3:0] data (byte data boundary mode) lon g word b0 b0 b0 4n+0/4n+0 1110 4n+0 byte b1 b1 b1 4n+0/4n+1 1101 4n+1 b2 b2 b2 4n+0/4n+2 1011 4n+2 b3 b3 b3 4n+0/4n+3 0111 4n+3 b0 b1 b0 b1 b1 b0 4n+0/4n+0 1100 4n+0 b2 b3 b2 b3 b3 b2 4n+0/4n+2 0011 4n+2 b0 b1 b2 b3 b0 b1 b2 b3 b3 b2 b1 b0 4n+0/4n+0 0000 4n+0 peripheral bus pci bus word memory/i/o spa c e a cc ess (peripheral bus ? pci bus) 31 0 31 0 31 0 figure 22.18 peripheral bus ? pci bus data alignment
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 961 of 1122 rej09b0370-0400 22.4.2 endian control for local bus big and little endians are supported on the local bus, determined at power-on reset by the external endian specification pin (md5). therefore, when transferring data betwee n the local bus and the pci bus, when the local bus is set for big endian, big/little endian conversion is therefore required. figure 22.19 shows the block diagram of the local bus endian control. an endian conversion circuit is provided between the local bus and the fifo. for details of the endian control, refer to section 22.4.3, endian control in dma transfers, and section 22.4.4, endian control in target transfers (memory read/memory write). local bus pci bus little endian bi g /little endian bi g /little little little bi g /little 32 bits 32 bits 32 bits 32 bits lw lw lw b, w, lw fifo dma ta r g et rd dma ta r g er wt fifo figure 22.19 endian control for local bus 22.4.3 endian control in dma transfers although only the longword access size is suppor ted in dma transfers (see table 22.11), the endian conversion mode can be selected from the following four types depending on whether the longword data consists of four byte data units or two word data units. the conversion mode can be switched by the setting of bits 10 and 9 (alnmd) of the dma control registers (pcidcr0 to 3) for pci. 1. byte data boundary mode: big/little endian conversion is performed on the assumption that all data is on a byte boundary. (alnmd = b'00) 2. word/longword (w/lw) boundary mode 1: longword data is transferred as byte data x 4. (alnmd = b'01) 3. word/longword (w/lw) boundary mode 2: longword data is transferred as word data x 2. (alnmd = b'10)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 962 of 1122 rej09b0370-0400 4. word/longword (w/lw) boundary mode 3: longword data is transferred as longword data x 1. (alnmd = b'11) only longword access size is supporte d in the case of dma transfers. figure 22.20 shows the data alignment in the respective boundary modes in dma transfers. table 22.11 dma transfer access size and endian conversion mode endian conversion mode local bus endian data transfer direction access size w/lw boundary mode (1 to 3) byte data boundary mode big endian local bus ? pci bus lw yes yes little endian local bus ? pci bus lw conversion not required conversion not required b0 be = 0000 b1 b2 b3 size = lw b3 b2 b1 b0 b3 b2 b1 b0 b2 b3 b0 b1 b0 b1 b2 b3 when lo c al bus is big endian local bus pci bus byte data boundary mode w/lw boundary mode 1 w/lw boundary mode 2 w/lw boundary mode 3 b3 be = 0000 b2 b1 b0 size = lw b3 b2 b1 b0 when lo c al bus is little endian local bus pci bus 31 0 31 0 31 0 31 0 31 0 31 0 31 0 figure 22.20 data alignment at dma transfer
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 963 of 1122 rej09b0370-0400 22.4.4 endian control in target transfers (memory read/memory write) in target transfers, for memory read and memory write that pe rform data transfer between the local bus and the pci bus, big/little endian conversion is required in the same way as for dma transfers when the local bus is set for big endians. word/longword boundary modes are not supported in the case of target transfers. as shown in table 22.12, the byte data boundary mode is used, for all transfers. the access sizes supported in the case of target transfers are as follo ws: for target reads (local bus to pci bus), longword only. for target writes (pci bus to local bus), longword/word/byte. in target write operations, the byte, word and longword data in the pcic are transferred to the local bus in one or two transfer operations depending on the type of the byte enable signal of the pci bus. for example, when c/ be = b'1010, byte access to the local bus is generated twice. when c/ be = b'1000, byte access and word access are each generated once. table 22.12 target transfer access si ze and endian co nversion mode endian conversion mode local bus endian data transfer direction access size w/lw boundary mode (1 to 3) byte data boundary mode big endian target read lw no yes target write b, w, lw no yes little endian target read lw target write b, w, lw conversion not required conversion not required
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 964 of 1122 rej09b0370-0400 size b b b b w w b + b b + b b + b b + b w + b w + b b + w b + w ? lw b0 b1 b2 b3 b0 b1 b2 b3 b0 b2 + b1 b3 + b0 b3 + b1 b2 + b0 b1 b2 + b0 b1 b3 + b0 b2 b3 + b1 b2 b3 + b0 b1 b2 b3 b0 1110 1101 1011 0111 1100 0011 1010 0101 0110 1001 1000 0100 0010 0001 1111 0000 b1 b2 b3 b1 b0 b3 b2 b2 b0 b3 b1 b3 b0 b2 b1 b2 b1 b0 b3 b1 b0 b3 b2 b0 b3 b2 b1 b3 b2 b1 b0 local bus pci bus 31 0 31 0 target memory write transfers (lo c al bus pci bus) when lo c al bus is big endian be size lw b0 b1 b2 b3 b3 b2 b1 b0 h'0 to h'f local bus pci bus 31 0 31 0 target memory read transfers (lo c al bus pci bus) when lo c al bus is big endian be ? figure 22.21 (1) data alignment at targ et memory transfer (big-endian local bus)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 965 of 1122 rej09b0370-0400 size b b b b w w b + b b + b b + b b + b w + b w + b b + w b + w ? lw b0 b1 b2 b3 b1 b0 b3 b2 b0 b2 + b1 b3 + b0 b3 + b1 b2 + b1 b0 b2 + b1 b0 b3 + b0 b3 b2 + b1 b3 b2 + b3 b2 b1 b0 b0 1110 1101 1011 0111 1100 0011 1010 0101 0110 1001 1000 0100 0010 0001 1111 0000 b1 b2 b3 b1 b0 b3 b2 b2 b0 b3 b1 b3 b0 b2 b1 b2 b1 b0 b3 b1 b0 b3 b2 b0 b3 b2 b1 b3 b2 b1 b0 local bus pci bus 31 0 31 0 target memory write transfers (lo c al bus pci bus) when lo c al bus is little endian be size lw b3 b2 b1 b0 b3 b2 b1 b0 h'0 to h'f local bus pci bus 31 0 31 0 target memory read transfers (lo c al bus pci bus) when lo c al bus is little endian be ? figure 22.21 (2) data alignment at target memory transfer (little-endian local bus)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 966 of 1122 rej09b0370-0400 22.4.5 endian control in target transfers (i/o read/i/o write) the access size is fixed at longwo rd when accessing the pcic local register using i/o read or i/o write commands. addresses are specifi ed using 4-byte boundaries, and be [3:0] is specified as b'0000. the data alignment in target transfers (i/o re ad and i/o write) is shown in figure 22.22. size lw address 4n h'0000 pci bus b3 b2 b1 b0 31 0 be local re g ister b3 b2 b1 b0 31 0 size lw address 4n h'0000 pci bus b3 b2 b1 b0 31 0 be local re g ister b3 b2 b1 b0 31 0 target i/o read transfer data alignment (lo c al register pci bus) target i/o write transfer data alignment (pci bus lo c al register) figure 22.22 data alignment at target i/o transfer (both big endian and little endian) 22.4.6 endian control in target transfers (configuration read/configuration write) the data alignment when accessing the pcic confi guration register using the target configuration read and configuration write commands is shown in figure 22.23. in the sh7751 the access size is fixed at longword. the be [3:0] value is ignored. in the sh7751r all be combinations are valid.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 967 of 1122 rej09b0370-0400 0000 0001 0010 0011 0100 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 h'0 to h'f pci bus b3 b2 b1 b0 31 0 be confi g uration re g ister pci bus be confi g uration re g ister b3 b2 b1 b0 31 0 b3 b2 b1 31 0 b3 b2 b0 31 0 b3 b2 31 0 b3 b1 b0 31 0 b3 b1 b0 31 0 b3 b1 31 0 b3 b0 31 0 b3 31 0 b2 b1 b0 31 0 b2 b1 31 0 b2 b0 31 0 b2 31 0 b1 b0 31 0 b1 31 0 b3 b2 b1 b0 31 0 31 0 h'0 to h'f pci bus b3 b2 b1 b0 31 0 be confi g uration re g ister b3 b2 b1 b0 31 0 b0 31 0 b3 b2 b1 31 0 b3 b2 b0 31 0 b3 b2 31 0 b3 b1 b0 31 0 b3 b1 b0 31 0 b3 b1 31 0 b3 b0 31 0 b3 31 0 b2 b1 b0 31 0 b2 b1 31 0 b2 b0 31 0 b2 31 0 b1 b0 31 0 b1 31 0 b3 b2 b1 b0 31 0 31 0 b0 31 0 target c onfiguration read transfer data alignment ( c onfiguration register pci bus) sh7751 target c onfiguration write transfer data alignment (pci bus c onfiguration register) sh7751r target c onfiguration transfer data alignment (pci bus c onfiguration register) figure 22.23 data alignment at target configuration transfer (both big endian and little endian)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 968 of 1122 rej09b0370-0400 22.5 resetting this section describes the resetting supported by the pcic. power-on reset when host: a reset ( pcirst ) can be output to the pci bus when the pcic is host. the pcirst pin is asserted when a power-on reset is generated at the reset pin or when a software reset is generated by setting 1 in the pcirst output control bit (rstctl) of the pci control register (pcicr). reset input in non-host mode: the pcic has no dedicated reset input pin. a reset signal from the pci bus can be connected to the reset pin and a power-on reset applied to this lsi, but the following point must be noted: in the pci standard, the reset ( rst ) signal must be asserted for a minimum of 1msec, check the time required for the power-on reset of this ls i (see section 23, electrical characteristics), and design the timing of power-on resets so that it satisfies the conditions of the reset period for both. manual reset: the pcic does not support the input of manual reset signals via the mreset pin. no initialization therefore occurs by manual resets. software reset: software resets are generated by setting 1 in the pcirst output control bit (rstctl) of the pci control register (pcicr). the pcirst pin is asserted at the same time as the pcic is reset. while a software reset is asserted, the pcic registers cannot be accessed. assertion requires a minimum of 1ms. software re sets are canceled by setting a 0 to the rstctl bit. it is not possible to set 0 in the rstctl bit and set other bits of the pcicr at the same time. after setting 0 in the rstctl bit, set other bits of the pcicr. note that not all pcic registers are reset at a software reset. see section 22.2, pcic register descriptions, for details of which registers are reset. use software clears as required for any registers that are not cleared by the software reset. note that, since software resets cannot be asserted while the pci bus clock is stopped, software resets must be asserted when the pci bus clock (pciclk or ckio) is being input. note that data cannot be guaranteed if a software re set is used while a data transfer is in progress.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 969 of 1122 rej09b0370-0400 22.6 interrupts 22.6.1 interrupts from pcic to cpu there are 8 interrupts, as shown in the following, that can be generated by the pcic for the cpu. the interrupt controller also controls the individu al interrupt priority levels and interrupt masks, etc. see the section 19, interrupt controller (intc), for details. table 22.13 interrupts interrupt source function intpri00 priority pciserr serr error interrupt [3:0] high pcierr err error interrupt [7:4] high pcipwdwn power-down request interrupt pcipwon power-on request interrupt pcidma0 dma0 transfer end interrupt pcidma1 dma1 transfer end interrupt pcidma2 dma2 transfer end interrupt pcidma3 dma3 transfer end interrupt low low system error ( serr ) interrupt (pciserr): this interrupt shows detection of the serr pin being asserted. this interrupt is generated only when the pcic is operating as host. when the pcic is operating as non-host, the serr bit in the pci control register (pcicr) is used to notify the host device of the system error (assertion of serr pin). the serr pin can be asserted when the serr bit is a sserted and when an ad dress parity error is detected in a target transfer. when the ser bit of the pci configuration register 1 (pciconf1) is set to 0, the serr pin is not asserted. error interrupt (pcierr): shows error detection by the pcic. the error interrupt is asserted when either of the following errors is detected: ? interrupts detected by pci in terrupt register (pciint) ? interrupts detected by pci arbiter interrupt register (pciaint)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 970 of 1122 rej09b0370-0400 the interrupts that can be detect ed by these two registers can al so be masked. the pci interrupt mask register (pciintm) masks the pciint interrupts, and the pci arbiter interrupt mask register (pciaintm) masks the pciaint interrupts. see s ection 22.2, pcic register descriptions, for details. the following are also set in relation to error interrupts: of the pci configuration register 1 (pciconf1), the parity erro r output status (dpe) the system erro r output status (sse), the master abort reception status (rma), th e target abort reception status (r ta), the target abort execution status (sta) and the data parity status (dpd). dma channel 0 transfer termin ation interrupt (pcidma0): the dma termination interrupt status (dmais) bit of the dma control re gister 0 (pcidcr0) is set. the interrupt mask is set by the dma termination interrupt mask (dmaim) bit of the same register. dma channel 1 transfer termin ation interrupt (pcidma1): the dma termination interrupt status (dmais) bit of the dma control re gister 1 (pcidcr1) is set. the interrupt mask is set by the dma termination interrupt mask (dmaim) bit of the same register. dma channel 2 transfer termin ation interrupt (pcidma2): the dma termination interrupt status (dmais) bit of the dma control re gister 2 (pcidcr2) is set. the interrupt mask is set by the dma termination interrupt mask (dmaim) bit of the same register. dma channel 3 transfer termin ation interrupt (pcidma3): the dma termination interrupt status (dmais) bit of the dma control re gister 3 (pcidcr3) is set. the interrupt mask is set by the dma termination interrupt mask (dmaim) bit of the same register. power management interrupt (transition request to normal status) (pcipwon): the power state d0 (pwrst_d0) bit of the pci power management interrupt register (pcipint) is set. the power state d0 interrupt mask can be set using the power state d0 (pwrst_d0) bit of the pci power management interrupt mask register (pcipintm). power management interrupt (transition re quest to power-down mode) (pcipwdwn): the power state d3 (pwrst_d3) bit of the pci power management interrupt register (pcipint) is set. the power state d3 interrupt mask can be set using the power state d3 (pwrst_d3) bit of the pci power management interrupt mask register (pcipintm). 22.6.2 interrupts from external pci devices to receive interrupt signals from external pci de vices, etc., while the pcic is operating as the host device, use the irl [3:0] pin. the pcic has no dedicated external interrupt input pin.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 971 of 1122 rej09b0370-0400 22.6.3 inta when the pcic is operating as a non-host device, the inta output can be used for interrupts to the host device. inta can be asserted (low output)/negated (high output) using the inta output soft control bit (inta) of the pci control register (pcicr). inta is open collector output. 22.7 error detection the pcic can store error information generated on the pci bus. the address information (alog [31:0]) at the time of the error is stored in the pci error address data register (pcialr). the pci error command information register (pciclr) stor es the type of transf er (mstpio, mstdma0, mstdma1, mstdma2, mstdma3, tgt) at the time of the error, and the pci command (cmdlog [3:0]). when the pcic is operating as host, the pci error bus master information register (pcibmlr) stores the bus master in formation (req4id, req3id, req2id, req1id, req0id) at the time of the error. the error information storage circuit can only store information for one error. therefore, when errors occur consecutively, no information is stored for the second or subsequent errors. error information is cleared by resets. 22.8 pcic clock three clocks are used with the pcic. the peripheral module clock (pck) is used for pcic register access and pio transfers. the bus cl ock (bck) is used for local bus control. the pci bus clock is used for pci bus operation. the peripheral module clock and pci bus clock do not need to be in sync, and there is no particular limit on the frequency ratio. however, in pio transfers and when registers are being accessed, etc., circuits operating with the peripheral module clock and circuits operating with the pci bus clock and circuits that synchronize both clocks are used, so the transfer speed depends on the frequency of the peripheral module clock as well. the bus clock (bck) and pci bus clock do not need to be in sync. however, the pci bus clock should be set to the same frequency as the bus clock (bck) or lower. the maximum pci bus clock is 66 mhz. either of the following can be selected using md9 as the pci bus clock: the ckio feedback input clock and the clock input from the external input pin (pciclk).
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 972 of 1122 rej09b0370-0400 external input pin (pciclk) operating mode: in this mode the pci bus clock is input from outside. this mode requires the provision of an external oscillation module for the pci. ckio operating mode: in this mode, the clock output from the ckio pin is used as the pci bus clock. the feedback input from the ckio pin is used as the pci bus clock. this mode can only be used when the pcic is operating as the host bridge. it cannot be used in non-host mode. when using this mode, note the ckio load capacita nce and only use it with in the prescribed load stated in the manual. note, too, that the clock frequency of ckio cannot be guaranteed until the pll oscillation stabilizes after a power-on reset or the clock frequency is changed. also, in standby mode, the clock stops. this mode should only be employed after checking that these points do not cause any problems from the viewpoint of the system configuration. in ckio operating mode, the maximum bck frequency is 66 mhz. when not using the pciclk pin, fix the pin level high. 66 mhz compatibility: the pcic is not necessarily fully compatible with the 66 mhz bus standard of the pci. for details, see section 23, electrical characteristics. in the electrical characteristics of the pci bus-related pins, the perm issible delay on the board is extremely short. for this reason, the on-board load capacitance and impedance ma tching should be considered before connecting to a 66mhz-compatible pci devi ce. note, too, that only one pci device can be connected. in the pci standard, there are two methods for ch ecking if a pci device can operate at 66 mhz: checking the 66 mhz operating status in the co nfiguration register 1, and monitoring the m66enb pin in the pci bus standard. the pcic supports the 66 mhz operating status (66m) bit of the configuration register 1 (pciconf1). the pcic does not have a special pin for directly monitoring the m66enb pin. also, there is no control output pin for switching between 33 mhz and 66 mhz when an external oscillator is used. a special external circuit is required to effect these controls. 22.9 power management 22.9.1 power management overview the pcic supports the pci power management (version 1.0 compatible) configuration registers. these are as follows:
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 973 of 1122 rej09b0370-0400 ? support for the pci power management control configuration register; ? support for the power-down/restore request interrupts from hosts on the pci bus. there are three configuration registers for pci power management control. pci configuration register 13 shows the address offset (capptr) of the configuration registers for power management. in the pcic, this offset is fixed at capptr = h'40. pci configuration register 16 and pci configuration register 17 are power management registers. they support two states: power state d0 (norma l) and power state d3 (power down mode). the pcic detects when the power state (pwrst) bit of the pci conf iguration register 17 changes (when it is written to from an external pci devi ce), and issues a power management interrupt. to control the power management interrupts, there are a pci power management interrupt register (pcipint) and pci power management interrupt mask register (pcipintm). of the power management interrupts, the power state d3 (pwr st_d3) interrupt detects a transition from the power state d0 to d3, while powe r state d0 (pwrst_d0) interrup t detects a transition from the power state d3 to d0. interrupt ma sks can be set for each interrupt. no power state d0 interrupt is generated at a power-on reset. the following cautions should be noted when the pcic is operating in non-host mode and a power down interrupt is received from the host: in pci power management (version 1.0 compatible), the pci bus clock stops within a minimum of 16 clocks after the host device has instructed a transition to power state d3. after detecting a power state d3 (power down) interrupt, do not, theref ore, attempt to read or write to local registers that can be accessed from the cp u and pci bus. because these registers operate using the pci bus clock, the read/write cycle for these registers will not be completed if the clock stops. 22.9.2 stopping the clock power savings can be achieved by stopping the bus clock used by the pcic and the pci bus clock. the pci clock control register (pciclkr) is prov ided for controlling the pcic clock. regarding the control register for stopping the peripheral module clock (pck) in the pcic, refer to section 9, power-down modes. the method of stopping the clock differs according to the operating mode of the pci bus clock. see table 22.14.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 974 of 1122 rej09b0370-0400 table 22.14 method of stoppi ng clock per operating mode pcic master slave lsi (other than pcic) pciclk operation ckio operation pciclk operation bck normal operation normal operation normal operation normal operation pck normal operation normal operation normal operation normal operation normal operation/ sleep pciclk not used normal operation not used normal operation bck stopped stopped stopped stopped pck normal operation normal operation normal operation normal operation deep sleep pciclk not used normal operation not used normal operation bck stopped stopped stopped stopped pck stopped stopped stopped stopped clock operating status standby pciclk not used stopped not used stopped transition sleep command bck stopped from lsi bck and pciclk stopped from lsi pci command + interrupt (pcic lsi) + bck restarted from lsi transition/ recovery deep sleep recovery 1 not used pme interrupt (connected to irl) + bck restarted from lsi pme interrupt (connected to irl) + bck and pciclk restarted from lsi pci command + interrupt (pcic lsi) + bck restarted from lsi recovery 2 nmi, irl, and reset on-chip peripheral interrupt nmi, irl, reset + bck restarted from lsi nmi, irl, reset + bck and pciclk restarted from lsi nmi, irl, reset + bck restarted from lsi + wait for pci command (recovery)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 975 of 1122 rej09b0370-0400 pcic master slave lsi (other than pcic) pciclk operation ckio operation pciclk operation transition/ recovery standby transition standby command standby command pciclk stopped from lsi + standby command pci command + interrupt (pcic lsi) + standby command recovery 1 not used pme interrupt (connected to irl) pme interrupt (connected to irl) + pciclk restarted from lsi power-on reset recovery 2 nmi, irl, and reset on-chip peripheral interrupt nmi, irl, and reset nmi, irl, reset + pciclk restarted from lsi nmi, irl, reset + wait for pci command (recovery) notes: recovery 1: recovery from pci bus recovery 2: recovery from other than pci bus external input pin (pciclk) operating mode: the pci bus clock can be stopped by writing 1 to the pciclkstop bit. the bus clock can be stopped by writing 1 to the bclkstop bit. it requires a minimum of 2 clocks of the pci bus cloc k for the clock to actually stop after writing to pciclkr (setting the pciclkstop bit to 1). it takes a similar time for the clock to restart. bus clock (ckio) operating mode: both the pci bus clock and bus clock can be stopped by writing 1 to the bclkstop bit. it requires a minimum of 2 clocks of the bus clock for the clock to actually stop after writing to pciclkr (setting the bclkstop bit to 1). it takes a similar time for the clock to restart. while the pci bus clock is stopped, it is not po ssible to access the local registers that can be accessed both from the peripheral module internal bus and from the pci bus. neither writing nor reading can be performed correctly. also, the following cautions must be observed when stopping the bus clock and pci bus clock while the pci is in use:
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 976 of 1122 rej09b0370-0400 ? when operating as host device the clock must be stopped only after stopping the operation of external pci devices connected to the pci bus. if you stop the clock prior to stopping the external devices, access from those external devices will cause a hang-up. stop the clock only after checki ng that there is no problem in respect to the system configuration. one method of stopping the operation of external pci devices is to use the pci power management, as discussed above. stop the clock after switching the external pci devices to power state d3 (power-down mode). in this cas e, all external pci devices must support pci power management. ? when operating in non-host mode when operating in non-host mode, the pci bus clock must be in external input operating mode (pciclk). in this case, the host device is responsible for stopping and restarting the pci bus clock, so it is not necessary to stop the clock using pciclkr of the pcic. make sure that the cpu receives the interrupt in accordance with the power management sequence. 22.9.3 compatibility with standby and sleep to stop all the pcic's internal clocks, the sl eep command must be used to transit to standby mode. when operating in external input pin (pciclk) operating mode, set the pciclkstop bit to 1 to stop the pci bus clock, transit to standb y, then, after recovering from standby, clear the pciclkstop bit to 0 to prevent hazards occuring in the pci bus clock. when using the standby command in systems using the pci bus, first check that the system does not hang up if the clock is stopped. note that the pcic clock does not stop after transiting to sleep mode. 22.10 port functions when the pcic is operating in non-host mode, the arbitration pin of the pci bus can be used as a port. when using the host functions (arbitration), the port functions cannot be used. the following six pins can be used: pcireq2 , pcireq3 , pcireq 4, pcignt2 , pcignt3 , and pcignt4 . the three pins pcireq2, pcireq3 , and pcireq4 can be used as i/o ports. the three pins pcignt2 , pcignt3 , and pcignt4 can be used as output ports. data is output in synchronous with the bus clock (ckio). input data is fetched at the rising edge of the bus clock. port control is performed by the port control register (pcipctr) and port data register (pcipdtr). pcipctr controls the existence of th e port function, the switching on/off of the pull-up resistance, and the switching between input and output. pcipdtr performs the input/output of port data.
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 977 of 1122 rej09b0370-0400 22.11 version management the pcic version management is written in the re vision id (8 bits) of the pci configuration register 2 (pciconf2). 22.12 usage notes 22.12.1 notes on arbiter in terrupt usage (sh7751 only) when the pcic function of the sh7751 is employed as a host with an arbitration function, care must be exercised as follows with regard to the target bus timeout interrupt and master bus timeout interrupt in the pci arbiter in terrupt register (pciaint). description: on the sh7751, notification of violations of the 16-clock rule or 8-clock rule for external pci devices (target latency and master data latency clock cycle limitations under the pci 2.1 specification) are provided by setting bit 12 (target bus timeout interrupt) or bit 11 (master bus timeout interrupt) in the pci arbiter interrupt register (pciaint) of the pcic. however, on the sh7751 these clock cycle limitations are set to on e clock cycle fewer than the values defined in the pci 2.1 specification. in other words, in the timings described in 1. and 2. below, even though the target latency or master data latency of the external pci device does not violate the 16-clock rule or 8-clock rule according to the pci 2.1 specifica tion, the sh7751 judges that a 16 -clock rule or 8-clock rule violation has occurred and sets to 1 bit 12 (tar get bus timeout interrupt) or bit 11 (master bus timeout interrupt) in the pci arbiter interrupt register (pciaint). 1. target latency: a target bus timeout interrupt occurs (see figures 22.24 and 22.25). during the first data transfer, the external pci device functioning as the target asserts trdy or stop at the sixteenth clock cycle after the da ta transfer request from the master device ( frame asserted). alternately, duri ng the second or a subseque nt data transfer, it asserts trdy or stop at the eighth clock cycle after th e immediately preceding data phase. 2. master data latency: a master bus timeout interrupt occurs (see figures 22.26 and 22.27). the external pci device functioning as the master acquires the bus and asserts frame , then asserts irdy at the eighth clock cycle during the firs t data transfer. alternately, during the second or a subsequent data transfer, it asserts irdy at the eighth clock cycle after the immediately preceding data phase. workarounds: when the pcic function of the sh7751 is employed as a host with an arbitration function, and an external device is connected that employs the full nu mber of clock cycles permitted under the 16-clock rule or 8-clock rule, use the pci arbiter interrupt mask register (pciaintm) to mask the bus timeout interrupts in the pci arbiter interrupt register (pciaint).
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 978 of 1122 rej09b0370-0400 1. if the problem concerns target latency, clear to 0 bit 12 (target bus timeout interrupt mask) in the pci arbiter interrupt mask register (pciaintm) to mask the target bus timeout interrupt. 2. if the problem concerns master data latency, clear to 0 bit 11 (master bus timeout interrupt mask) in the pci arbiter interrupt mask register (pciaintm) to mask the master bus timeout interrupt. note that if the above interrupts are masked, no interrupt will occur when the 16-clock rule or 8-clock rule of pci 2.1 specification is violated, even if the violation is detected. a 0 pciclk ad[31:0] c/ be [3:0] frame irdy devsel trdy stop 1234 111213141516 c pciaint: bit 12 asserted figure 22.24 target bus timeou t interrupt generation example 1 (example in which the target device asserts stop at the sixteenth clock cycle after frame was asserted)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 979 of 1122 rej09b0370-0400 add dddddd pciclk (hi g h) ad[31:0] c/ be [3:0] frame irdy devsel trdy stop 2 01 345678 c bebe bebe be be be be pciaint: bit 12 asserted figure 22.25 target bus timeou t interrupt generation example 2 (example in which the target device takes 8 clock cycles to prepare for the third data transfer) a 0 pciclk ad[31:0] c/ be [3:0] frame irdy devsel trdy stop 12345678 c dddd dd be be be d be be be be (hi g h) pciaint: bit 11 asserted figure 22.26 master bus timeout interrupt generation example 1 (example in which the master devi ce prepares the data and asserts irdy at the eighth clock cycle after frame was asserted)
22. pci controller (pcic) rev.4.00 oct. 10, 2008 page 980 of 1122 rej09b0370-0400 add d ddddd pciclk ad[31:0] c/ be [3:0] frame irdy devsel trdy stop 2 01 345678 cbebe bebe be be be be (hi g h) pciaint: bit 11 asserted figure 22.27 master bus timeout interrupt generation example 2 (example in which the master device takes 8 cl ock cycles to prepare for the third data transfer following the second data phase) 22.12.2 notes on i/o read and i/o write commands (sh7751 only) see i/o-read and i/o-write commands in 22.3.8. 22.12.3 notes on configuration-read and configuration-write commands (sh7751 only) see configuration-read and config uration-write commands in 22.3.8. 22.12.4 notes on target read/write cycle timing (sh7751 only) see target read/write cy cle timing in 22.3.11.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 981 of 1122 rej09b0370-0400 section 23 electrical characteristics 23.1 absolute maximum ratings table 23.1 absolute maximum ratings item symbol value unit i/o, rtc, cpg power supply voltage v ddq , v dd-rtc , v dd-cpg ?0.3 to 4.2 ?0.3 to 4.6 * v internal power supply voltage v dd , v dd-pll1/2 ?0.3 to 2.5 ?0.3 to 2.1 * v input voltage v in ?0.3 to v ddq +0.3 v operating temperature t opr ?20 to 75 c storage temperature t stg ?55 to 125 c notes: the lsi may be permanently damaged if the maximum ratings are exceeded. the lsi may be permanently damaged if any of the vss pins are not connected to gnd. for the powering-on and powering-off sequences, see appendix g, power-on and power- off procedures. * hd6417751r only.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 982 of 1122 rej09b0370-0400 23.2 dc characteristics table 23.2 dc characteristics (hd6417751rbp240 (v), hd6417751rbg240 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, deep-sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.4 1.5 1.6 v normal mode, sleep mode, deep-sleep mode, standby mode current dissipation normal operation i dd ? 255 660 sleep mode ? 140 180 ma ick = 240 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 current dissipation normal operation i ddq ? 100 145 sleep mode ? 60 115 ma bck = 120 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 standby mode ? 15 25 rtc on * 2 current dissipation i dd-rtc ? 3 5 a rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq + 0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 983 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v output voltage pci pins v oh 2.4 ? ? v v ddq = 3.0 v, i oh = ?4 ma other output pins 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins v ol ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma other output pins ? ? 0.55 v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode (there is no need to input a clock from extal2). 2. to reduce the leakage current in standby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 984 of 1122 rej09b0370-0400 table 23.3 dc characteristics (hd6417751rf240 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, deep-sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.4 1.5 1.6 v normal mode, sleep mode, deep-sleep mode, standby mode current dissipation normal operation i dd ? 255 660 sleep mode ? 140 180 ma ick = 240 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 current dissipation normal operation i ddq ? 70 100 sleep mode ? 42 80 ma bck = 84 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 standby mode ? 15 25 rtc on * 2 current dissipation i dd-rtc ? 3 5 a rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq +0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 985 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v output voltage pci pins v oh 2.4 ? ? v v ddq = 3.0 v, i oh = ?4 ma other output pins 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins v ol ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma other output pins ? ? 0.55 v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode (there is no need to input a clock from extal2). 2. to reduce the leakage current in standby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 986 of 1122 rej09b0370-0400 table 23.4 dc characteristics (hd6417751rbp200 (v), hd6417751rbg200 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, deep-sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.35 1.5 1.6 v normal mode, sleep mode, deep-sleep mode, standby mode current dissipation normal operation i dd ? 210 550 sleep mode ? 115 150 ma ick = 200 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 current dissipation normal operation i ddq ? 85 120 sleep mode ? 50 95 ma bck = 100 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 standby mode ? 15 25 rtc on * 2 current dissipation i dd-rtc ? 3 5 a rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq +0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 987 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v pci pins 2.4 ? ? v ddq = 3.0 v, i oh = ?4 ma other output pins v oh 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma output voltage other output pins v ol ? ? 0.55 v v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode (there is no need to input a clock from extal2). 2. to reduce the leakage current in standby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 988 of 1122 rej09b0370-0400 table 23.5 dc characteristics (hd6417751rf200 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, deep-sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.35 1.5 1.6 v normal mode, sleep mode, deep-sleep mode, standby mode current dissipation normal operation i dd ? 210 550 sleep mode ? 115 150 ma ick = 200 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 current dissipation normal operation i ddq ? 70 100 sleep mode ? 42 80 ma bck = 84 mhz standby mode ? ? 400 a t a = 25 c * 1 ? ? 800 t a > 50 c * 1 standby mode ? 15 25 rtc on * 2 current dissipation i dd-rtc ? 3 5 a rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq +0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 989 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 input voltage other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v pci pins 2.4 ? ? v ddq = 3.0 v, i oh = ?4 ma other output pins v oh 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma output voltage other output pins v ol ? ? 0.55 v v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode (there is no need to input a clock from extal2). 2. to reduce the leakage current in standby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 990 of 1122 rej09b0370-0400 table 23.6 dc characteristics (hd6417751bp167 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.6 1.8 2.0 v normal mode, sleep mode, standby mode current dissipation normal operation i dd ? 420 750 sleep mode ? 100 130 ma ick = 167 mhz standby mode ? ? 400 a t a = 25 c (rtc on) * ? ? 800 t a > 50 c (rtc on) * current dissipation normal operation i ddq ? 70 100 sleep mode ? 40 80 ma ick = 167 mhz, bck = 84 mhz standby mode ? ? 400 a t a = 25 c (rtc on) * ? ? 800 t a > 50 c (rtc on) * standby mode i dd-rtc ? ? 25 a rtc on current dissipation ? ? 5 rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq +0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 991 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 input voltage other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v pci pins v oh 2.4 ? ? v v ddq = 3.0 v, i oh = ?4 ma other output pins 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins v ol ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma output voltage other output pins ? ? 0.55 v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. * to reduce the leakage current in st andby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 992 of 1122 rej09b0370-0400 table 23.7 dc characteristics (hd6417751f167 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-cpg v dd-rtc 3.0 3.3 3.6 normal mode, sleep mode, standby mode power supply voltage v dd v dd-pll1/2 1.6 1.8 2.0 v normal mode, sleep mode, standby mode current dissipation normal operation i dd ? 420 750 sleep mode ? 100 130 ma ick = 167 mhz standby mode ? ? 400 a t a = 25 c (rtc on) * ? ? 800 t a > 50 c (rtc on) * current dissipation normal operation i ddq ? 70 100 sleep mode ? 40 80 ma ick = 167 mhz, bck = 84 mhz standby mode ? ? 400 a t a = 25 c (rtc on) * ? ? 800 t a > 50 c (rtc on) * standby mode i dd-rtc ? ? 25 a rtc on current dissipation ? ? 5 rtc off input voltage reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v ih v ddq 0.9 ? v ddq +0.3 v pciclk v ddq 0.6 ? v ddq +0.3 other pci input pins v ddq 0.5 ? v ddq +0.3 other input pins 2.0 ? v ddq +0.3
23. electrical characteristics rev.4.00 oct. 10, 2008 page 993 of 1122 rej09b0370-0400 item symbol min typ max unit test conditions reset , nmi, trst , asebrk / brkack, mreset , sleep , ca v il ?0.3 ? v ddq 0.1 v pciclk ?0.3 ? v ddq 0.2 other pci input pins ?0.3 ? v ddq 0.3 input voltage other input pins ?0.3 ? v ddq 0.2 input leak current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leak current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v pci pins v oh 2.4 ? ? v v ddq = 3.0 v, i oh = ?4 ma other output pins 2.4 ? ? v ddq = 3.0 v, i oh = ?2 ma pci pins v ol ? ? 0.55 v ddq = 3.0 v, i ol = 4 ma output voltage other output pins ? ? 0.55 v ddq = 3.0 v, i ol = 2 ma pull-up resistance all pins r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-rtc , and v dd-cpg to v ddq , v dd-pll1/2 to v dd , and v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i dd is the sum of the v dd and v dd-pll1/2 currents. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg currents. * to reduce the leakage current in st andby mode, the rtc must be turned on (rcr2.trcen = 1 and clock is input to extal2).
23. electrical characteristics rev.4.00 oct. 10, 2008 page 994 of 1122 rej09b0370-0400 table 23.8 permissible output currents item symbol min typ max unit permissible output low current (per pin; other than pci pins) i ol ? ? 2 ma permissible output low current (per pin; pci pins) i ol ? ? 4 permissible output low current (total) i ol ? ? 120 permissible output high current (per pin; other than pci pins) ?i oh ? ? 2 ma permissible output high current (per pin; pci pins) ?i oh ? ? 4 permissible output high current (total) (?i oh ) ? ? 40 note: to protect chip reliability, do not exc eed the output current values in table 23.8. 23.3 ac characteristics in principle, this lsi's input should be synchronous. unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. table 23.9 clock timing (hd6417751rbp240 (v), hd6417751rbg240 (v)) item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 240 mhz external bus 1 ? 120 operating frequency peripheral modules 1 ? 60 table 23.10 clock timing (hd6417751rf240 (v)) item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 240 mhz external bus 1 ? 84 operating frequency peripheral modules 1 ? 60
23. electrical characteristics rev.4.00 oct. 10, 2008 page 995 of 1122 rej09b0370-0400 table 23.11 clock timing (hd6417751rbp200 (v), hd6417751rbg200 (v)) item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 200 mhz external bus 1 ? 100 operating frequency peripheral modules 1 ? 50 table 23.12 clock timing (hd6417751rf200 (v)) item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 200 mhz external bus 1 ? 84 operating frequency peripheral modules 1 ? 50 table 23.13 clock timing (hd6417751bp167 (v), hd6417751f167 (v)) item symbol min typ max unit notes cpu, fpu, cache, tlb f 1 ? 167 mhz external bus 1 ? 84 operating frequency peripheral modules 1 ? 42
23. electrical characteristics rev.4.00 oct. 10, 2008 page 996 of 1122 rej09b0370-0400 23.3.1 clock and cont rol signal timing table 23.14 clock and control signal timing (hd6417751rbp240 (v), hd6417751rbg240 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation 16 34 pll1 12-times/pll2 operation 14 20 extal clock input frequency pll1/pll2 not operating f ex 1 34 mhz extal clock input cycle time t excyc 30 1000 ns 23.1 extal clock input low-level pulse width t exl 3.5 ? ns 23.1 extal clock input high-level pulse width t exh 3.5 ? ns 23.1 extal clock input rise time t exr ? 4 ns 23.1 extal clock input fall time t exf ? 4 ns 23.1 pll1/pll2 operating 25 120 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 8.3 1000 ns 23.2(1) ckio clock output low-level pulse width t ckol1 1 ? ns 23.2(1) ckio clock output high-level pulse width t ckoh1 1 ? ns 23.2(1) ckio clock output rise time t ckor ? 3 ns 23.2(1) ckio clock output fall time t ckof ? 3 ns 23.2(1) ckio clock output low-level pulse width t ckol2 3 ? ns 23.2(2) ckio clock output high-level pulse width t ckoh2 3 ? ns 23.2(2) power-on oscillation settling time t osc1 10 ? ms 23.3, 23.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 23.3, 23.5 md reset setup time t mdrs 3 ? t cyc md reset hold time t mdrh 20 ? ns 23.3, 23.5 reset assert time t resw 20 ? t cyc 23.3, 23.4, 23.5, 23.6 pll synchronization settling time t pll 200 ? s 23.9, 23.10 standby return oscillation settling time 1 t osc2 3 ? ms 23.4, 23.6 standby return oscillation settling time 2 t osc3 3 ? ms 23.7 standby return oscillation settling time 3 t osc4 3 ? ms 23.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 23.10 trst reset hold time t trstrh 0 ? ns 23.3, 23.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. as there is feedback from the ckio pin wh en pll2 is operating, the load capacitance connected to the ckio pin should be a maximum of 50 pf. * when the oscillation settling time of t he crystal resonator is 1 ms or less.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 997 of 1122 rej09b0370-0400 table 23.15 clock and control signal timing (hd6417751rf240 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation 16 34 pll1 12-times/pll2 operation 16 20.0 extal clock input frequency pll1/pll2 not operating f ex 1 34 mhz extal clock input cycle time t excyc 30 1000 ns 23.1 extal clock input low-level pulse width t exl 3.5 ? ns 23.1 extal clock input high-level pulse width t exh 3.5 ? ns 23.1 extal clock input rise time t exr ? 4 ns 23.1 extal clock input fall time t exf ? 4 ns 23.1 pll1/pll2 operating 25 84 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 11.9 1000 ns 23.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 23.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 23.2 (1) ckio clock output rise time t ckor ? 3 ns 23.2 (1) ckio clock output fall time t ckof ? 3 ns 23.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 23.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 23.2 (2) power-on oscillation settling time t osc1 10 ? ms 23.3, 23.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 23.3, 23.5 md reset setup time t mdrs 3 ? t cyc md reset hold time t mdrh 20 ? ns 23.3, 23.5 reset assert time t resw 20 ? t cyc 23.3, 23.4, 23.5, 23.6 pll synchronization settling time t pll 200 ? s 23.9, 23.10 standby return oscillation settling time 1 t osc2 3 ? ms 23.4, 23.6 standby return oscillation settling time 2 t osc3 3 ? ms 23.7 standby return oscillation settling time 3 t osc4 3 ? ms 23.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 23.10 trst reset hold time t trstrh 0 ? ns 23.3, 23.5 notes: when a crystal resonator is connected to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. as there is feedback from the ckio pin when pll2 is operating, the load capacitance connected to the ckio pin should be a maximum of 50 pf. * when the oscillation settling time of the crystal resonator is 1 ms or less.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 998 of 1122 rej09b0370-0400 table 23.16 clock and control signal timing (hd6417751rbp200 (v), hd6417751rbg200 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation 16 34 pll1 12-times/pll2 operation 14 17 extal clock input frequency pll1/pll2 not operating f ex 1 34 mhz extal clock input cycle time t excyc 30 1000 ns 23.1 extal clock input low-level pulse width t exl 3.5 ? ns 23.1 extal clock input high-level pulse width t exh 3.5 ? ns 23.1 extal clock input rise time t exr ? 4 ns 23.1 extal clock input fall time t exf ? 4 ns 23.1 pll1/pll2 operating 25 100 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 10 1000 ns 23.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 23.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 23.2 (1) ckio clock output rise time t ckor ? 3 ns 23.2 (1) ckio clock output fall time t ckof ? 3 ns 23.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 23.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 23.2 (2) power-on oscillation settling time t osc1 10 ? ms 23.3, 23.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 23.3, 23.5 md reset setup time t mdrs 3 ? t cyc md reset hold time t mdrh 20 ? ns 23.3, 23.5 reset assert time t resw 20 ? t cyc 23.3, 23.4, 23.5, 23.6 pll synchronization settling time t pll 200 ? s 23.9, 23.10 standby return oscillation settling time 1 t osc2 5 ? ms 23.4, 23.6 standby return oscillation settling time 2 t osc3 5 ? ms 23.7 standby return oscillation settling time 3 t osc4 5 ? ms 23.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 23.10 trst reset hold time t trstrh 0 ? ns 23.3, 23.5 notes: when a crystal resonator is connected to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. as there is feedback from the ckio pin when pll2 is operating, the load capacitance connected to the ckio pin should be a maximum of 50 pf. * when the oscillation settling time of the crystal resonator is 1 ms or less.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 999 of 1122 rej09b0370-0400 table 23.17 clock and control signal timing (hd6417751rf200 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation 16 34 pll1 12-times/pll2 operation 14 17 extal clock input frequency pll1/pll2 not operating f ex 1 34 mhz extal clock input cycle time t excyc 30 1000 ns 23.1 extal clock input low-level pulse width t exl 3.5 ? ns 23.1 extal clock input high-level pulse width t exh 3.5 ? ns 23.1 extal clock input rise time t exr ? 4 ns 23.1 extal clock input fall time t exf ? 4 ns 23.1 pll1/pll2 operating 25 84 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 11.9 1000 ns 23.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 23.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 23.2 (1) ckio clock output rise time t ckor ? 3 ns 23.2 (1) ckio clock output fall time t ckof ? 3 ns 23.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 23.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 23.2 (2) power-on oscillation settling time t osc1 10 ? ms 23.3, 23.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 23.3, 23.5 md reset setup time t mdrs 3 ? t cyc md reset hold time t mdrh 20 ? ns 23.3, 23.5 reset assert time t resw 20 ? t cyc 23.3, 23.4, 23.5, 23.6 pll synchronization settling time t pll 200 ? s 23.9, 23.10 standby return oscillation settling time 1 t osc2 5 ? ms 23.4, 23.6 standby return oscillation settling time 2 t osc3 5 ? ms 23.7 standby return oscillation settling time 3 t osc4 5 ? ms 23.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 23.10 trst reset hold time t trstrh 0 ? ns 23.3, 23.5 notes: when a crystal resonator is connected to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. as there is feedback from the ckio pin when pll2 is operating, the load capacitance connected to the ckio pin should be a maximum of 50 pf. * when the oscillation settling time of the crystal resonator is 1 ms or less.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1000 of 1122 rej09b0370-0400 table 23.18 clock and control signal timing (hd6417751bp167 (v), hd6417751f167 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 30 56 mhz pll1/pll2 operating 1/2 divider not operating f ex 15 28 1/2 divider operating f ex 2 56 extal clock input frequency pll1/pll2 not operating 1/2 divider not operating f ex 1 28 extal clock input cycle time t excyc 17.8 1000 ns 23.1 extal clock input low-level pulse width t exl 3.5 ? ns 23.1 extal clock input high-level pulse width t exh 3.5 ? ns 23.1 extal clock input rise time t exr ? 4 ns 23.1 extal clock input fall time t exf ? 4 ns 23.1 pll2 operating f op 30 84 mhz ckio clock output pll2 not operating f op 1 84 mhz ckio clock output cycle time t cyc 11.9 1000 ns 23.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 23.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 23.2 (1) ckio clock output rise time t ckor ? 3 ns 23.2 (1) ckio clock output fall time t ckof ? 3 ns 23.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 23.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 23.2 (2) power-on oscillation settling time t osc1 10 ? ms 23.3, 23.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 23.3, 23.5 md reset setup time t mdrs 3 ? t cyc md reset hold time t mdrh 20 ? ns 23.3, 23.5 reset assert time t resw 20 ? t cyc 23.3, 23.4, 23.5, 23.6 pll synchronization settling time t pll 200 ? s 23.9, 23.10 standby return oscillation settling time 1 t osc2 10 ? ms 23.4, 23.6 standby return oscillation settling time 2 t osc3 5 ? ms 23.7 standby return oscillation settling time 3 t osc4 5 ? ms 23.8 irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 23.10 trst reset hold time t trstrh 0 ? ns 23.3, 23.5 notes: when a crystal resonator is connected to extal and xtal, the maximum frequency is 28 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. as there is feedback from the ckio pin when pll2 is operating, the load capacitance connected to the ckio pin should be a maximum of 50 pf.
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1001 of 1122 rej09b0370-0400 t excyc t exh t exl t exr t exf 1/2v ddq v ih v ih v il v il v ih 1/2v ddq note: when the clock is input from the extal pin figure 23.1 extal clock input timing t cyc t ckoh1 t ckol1 t ckor t ckof 1/2v ddq v oh v oh v ol v ol v oh 1/2v ddq figure 23.2 (1) ckio clock output timing t ckoh2 1.5 v 1.5 v 1.5 v t ckol2 figure 23.2 (2) ckio clock output timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1002 of 1122 rej09b0370-0400 ckio, internal clock vdd md10 to md0 ca (hi g h) reset trst t osc1 v dd min t mdrh t oscmd t trstrh stable oscillation t resw notes: 1. oscillation settlin g time when on-chip resonator is used 2. pll2 not operatin g figure 23.3 power-on oscillation settling time reset or mreset t resw t osc2 standby stable oscillation ckio, internal clock notes: 1. oscillation settlin g time when on-chip resonator is used 2. pll2 not operatin g figure 23.4 standby return osc illation settling time (return by reset or mreset )
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1003 of 1122 rej09b0370-0400 internal clock vdd md10 to md0 reset trst t osc1 v dd min t mdrh t oscmd t trstrh stable oscillation t resw ckio notes: 1. oscillation settlin g time when on-chip resonator is used 2. pll2 operatin g figure 23.5 power-on oscillation settling time reset or mreset t resw t osc2 ckio stable oscillation standby internal clock notes: 1. oscillation settlin g time when on-chip resonator is used 2. pll2 operatin g figure 23.6 standby return osc illation settling time (return by reset or mreset )
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1004 of 1122 rej09b0370-0400 ckio, internal clock nmi stable oscillation standby t osc3 note: oscillation settlin g time when on-chip resonator is used figure 23.7 standby return oscilla tion settling time (return by nmi) irl3 ? irl0 t osc4 standby stable oscillation ckio, internal clock note: oscillation settlin g time when on-chip resonator is used figure 23.8 standby return oscillation settling time (return by irl3 ? irl0 )
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1005 of 1122 rej09b0370-0400 extal input pll output, ckio output internal clock status1? status0 note: when an external clock is input from extal. stable input clock normal standby normal t pll 2 stable input clock reset or nmi interrupt request pll synchronization pll synchronization figure 23.9 pll synchronization settling time in case of reset, mreset or nmi interrupt irl3 ? irl0 interrupt request t irlstb status1? status0 note: when an external clock is input from extal. normal standby normal t pll 2 extal input pll output, ckio output internal clock stable input clock stable input clock pll synchronization pll synchronization figure 23.10 pll synchronization sett ling time in case of irl interrupt
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1006 of 1122 rej09b0370-0400 23.3.2 control signal timing table 23.19 control signal timing hd6417751r bp240 (v) hd6417751r bg240 (v) hd6417751r bp200 (v) hd6417751r bg200 (v) hd6417751r f240 (v) hd6417751r f200 (v) * * * * item symbol min max min max min max min max unit figure breq setup time t breqs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns 23.11 breq hold time t breqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 23.11 back delay time t backd ? 5.3 ? 5.3 ? 6 ? 6 ns 23.11 bus tri-state delay time t boff1 ? 12 ? 12 ? 12 ? 12 ns 23.11 bus tri-state delay time to standby mode t boff2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (2) bus buffer on time t bon1 ? 12 ? 12 ? 12 ? 12 ns 23.11 bus buffer on time from standby t bon2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (2) t std1 ? 6 ? 6 ? 6 ? 6 ns 23.12 (1) status 0/1 delay time t std2 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (1) (2) t std3 ? 2 ? 2 ? 2 ? 2 t cyc 23.12 (2) note: * v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1007 of 1122 rej09b0370-0400 table 23.20 control signal timing hd6417751bp167 (v) hd6417751f167 (v) * item symbol min max unit figure breq setup time t breqs 3.5 ? ns 23.11 breq hold time t breqh 1.5 ? ns 23.11 back delay time t backd ? 8 ns 23.11 bus tri-state delay time t boff1 ? 12 ns 23.11 bus tri-state delay time to standby mode t boff2 ? 2 t cyc 23.12 (2) bus buffer on time t bon1 ? 12 ns 23.11 bus buffer on time from standby t bon2 ? 2 t cyc 23.12 (2) status 0/1 delay time t std1 ? 6 ns 23.12 (1) t std2 ? 2 t cyc 23.12 (1) (2) t std3 ? 2 t cyc 23.12 (2) note: * v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1008 of 1122 rej09b0370-0400 ckio a25?a0, csn , bs , rd/ wr , ce2a , ce2b , ras , wen , rd , casn breq back t breqh t breqs t breqh t breqs t backd t boff1 t bon1 t backd figure 23.11 control signal timing t std1 ckio status1, status0 reset or sleep normal normal t std2 normal operation normal operation reset or sleep mode figure 23.12 (1) pin drive ti ming for reset or sleep mode
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1009 of 1122 rej09b0370-0400 t std3 t bon2 ckio note: * these pins can be put into a hi g h-impedance state with stbcr.phz. status1, status0 csn , rd , rd/ wr , wen , bs , ras ce2a , ce2b , casn dackn, drakn, sck, * txd, txd2, cts2 , rts2 a25 ? a0, d31 ? d0 t boff2 software standby normal normal t std2 normal operation normal operation reset or sleep mode figure 23.12 (2) pin drive timi ng for software standby mode
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1010 of 1122 rej09b0370-0400 23.3.3 bus timing table 23.21 bus timing (1) hd6417751r bp240 (v) hd6417751r bg240 (v) hd6417751r bp200 (v) hd6417751r bg200 (v) hd6417751r f240 (v) hd6417751r f200 (v) * * * * item symbol min max min max min max min max unit notes address delay time t ad 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns bs delay time t bsd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns cs delay time t csd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns rw delay time t rwd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns rd delay time t rsd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns read data setup time t rds 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns read data hold time t rdh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns we delay time (falling edge) t wedf ? 5.3 ? 5.3 ? 6 ? 6 ns relative to ckio falling edge we delay time t wed1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns write data delay time t wdd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns rdy setup time t rdys 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns rdy hold time t rdyh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns ras delay time t rasd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns cas delay time 1 t casd1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns dram cas delay time 2 t casd2 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns sdram cke delay time t cked 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns sdram dqm delay time t dqmd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns sdram frame delay time t fmd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns mpx iois16 setup time t io16s 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns pcmcia iois16 hold time t io16h 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns pcmcia iciowr delay time (falling edge) t icwsdf 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns pcmcia iciord delay time t icrsd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns pcmcia dack delay time t dacd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1011 of 1122 rej09b0370-0400 hd6417751r bp240 (v) hd6417751r bg240 (v) hd6417751r bp200 (v) hd6417751r bg200 (v) hd6417751r f240 (v) hd6417751r f200 (v) * * * * item symbol min max min max min max min max unit notes dack delay time (falling edge) t dacdf 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns relative to ckio falling edge dtr setup time t dtrs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns dtr hold time t dtrh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns dbreq setup time t dbqs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns dbreq hold time t dbqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns tr setup time t trs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns tr hold time t trh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns bavl delay time t bavd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tdack delay time t tdad 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns id1, id0 delay time t idd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns note: * v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1012 of 1122 rej09b0370-0400 table 23.22 bus timing (2) hd6417751bp167 (v) hd6417751f167 (v) * item symbol min max unit notes address delay time t ad 1.0 8 ns bs delay time t bsd 1.0 8 ns cs delay time t csd 1.0 8 ns rw delay time t rwd 1.0 8 ns rd delay time t rsd 1.0 8 ns read data setup time t rds 3.5 ? ns read data hold time t rdh 1.5 ? ns we delay time (falling edge) t wedf 1.0 8 ns relative to ckio falling edge we delay time t wed1 1.0 8 ns write data delay time t wdd 1.0 8 ns rdy setup time t rdys 3.5 ? ns rdy hold time t rdyh 1.5 ? ns ras delay time t rasd 1.0 8 ns cas delay time 1 t casd1 1.0 8 ns dram cas delay time 2 t casd2 1.0 8 ns sdram cke delay time t cked 1.0 8 ns sdram dqm delay time t dqmd 1.0 8 ns sdram frame delay time t fmd 1.0 8 ns mpx iois16 setup time t io16s 3.5 ? ns pcmcia iois16 hold time t io16h 1.5 ? ns pcmcia iciowr delay time (falling edge) t icwsdf 1.0 8 ns pcmcia iciord delay time t icrsd 1.0 8 ns pcmcia dack delay time t dacd 1.0 8 ns dack delay time (falling edge) t dacdf 1.0 8 ns relative to ckio falling edge dtr setup time t dtrs 3.5 ? ns dtr hold time t dtrh 1.5 ? ns
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1013 of 1122 rej09b0370-0400 hd6417751bp167 (v) hd6417751f167 (v) * item symbol min max unit notes dbreq setup time t dbqs 3.5 ? ns dbreq hold time t dbqh 1.5 ? ns tr setup time t trs 3.5 ? ns tr hold time t trh 1.5 ? ns bavl delay time t bavd 1.0 8 ns tdack delay time t tdad 1.0 8 ns id1, id0 delay time t idd 1.0 8 ns note: * v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75 c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1014 of 1122 rej09b0370-0400 t1 t ad t ad t2 ckio a25 ? a0 csn rd/ wr rd d31 ? d0 (read) d31 ? d0 (write) bs dackn (da) t wdd t wdd t wdd t rdh t rds t csd t csd t rwd t rwd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd t dacd t dacd t dacdf t dacdf t dacd rdy wen dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.13 sram bus cycl e: basic bus cycle (no wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1015 of 1122 rej09b0370-0400 t wdd t wdd t wdd t dacdf t dacdf ckio a25 ? a0 csn rd/ wr rd d31 ? d0 (read) d31 ? d0 (write) bs dackn (da) rdy wen t1 t ad tw t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t bsd t bsd t dacd t dacd t dacd t dacd t dacd dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.14 sram bus cycle: ba sic bus cycle (one internal wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1016 of 1122 rej09b0370-0400 t wdd t wdd t wdd t dacdf t dacdf ckio a25?a0 csn rd/ wr rd d31?d0 (read) d31?d0 (write) bs dackn (da) rdy wen t1 t ad tw twe t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t rdyh t rdys t bsd t bsd t dacd t dacd t dacd t dacd t dacd dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.15 sram bus cycle: basic bus cycle (one internal wait + one external wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1017 of 1122 rej09b0370-0400 t wdd t wdd t wdd t dacdf t dacdf t dacd t dacd t dacd ts1 t ad t1 t2 th1 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd ckio a25 ? a0 csn rd/ wr rd d31 ? d0 (read) d31 ? d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) dackn (da) rdy wen le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.16 sram bus cycle: basic bus cycle (no wait, addres s setup/hold time insertion, ans = 1, anh = 1)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1018 of 1122 rej09b0370-0400 ckio a25?a5 t1 t2 csn rd/ wr rd d31?d0 (read) bs rdy a4?a0 tb2 tb1 tb2 tb1 tb2 tb1 t csd t ad t rwd t bsd t rds t bsd t rsd t rsd t rdh t ad t ad t csd t rwd t rdh t rsd t rds dackn (sa: io memory) dackn (da) t dacd t dacd t dacd t dacd t dacd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.17 burst rom bus cycle (no wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1019 of 1122 rej09b0370-0400 t1 t2 tb2 tb1 tb2 tb1 tb2 tb1 twb twb twb twe tw t ad t csd t rsd t rdh t rds t bsd t ad t rdh t rsd t rds t ad t csd t rdyh t rdys t rdyh t rdys t rdyh t rdys t dacd t dacd t dacd t dacd t rwd t rwd ckio a25?a5 csn rd/wr rd d31?d0 (read) bs rdy a4?a0 dackn (sa: io memory) dackn (da) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.18 burst rom bus cycle (1st data: one internal wait + one external wait; 2nd/3rd/4th data: one internal wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1020 of 1122 rej09b0370-0400 t1 tb2 t csd t rwd t bsd t rds t bsd t rsd t ad ts1 t dacd tb1 tb2 t ad t rdh t dacd t dacd tb1 tb2 t2 tb1 t ad t csd t rwd t rdh t rsd t rds th1 ts1 th1 ts1 th1 ts1 th1 ckio a25?a5 csn rd/ wr rd d31?d0 (read) bs rdy a4?a0 dackn (sa: io memory) dackn (da) t dacd t dacd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.19 burst rom bus cycle (no wait, address setup/hold time insertion, ans = 1, anh = 1)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1021 of 1122 rej09b0370-0400 tw t1 twe tb2 tb1 twb twbe tb1 tb2 twb twbe twb t2 tb2 twbe tb1 ckio a25?a5 a4?a0 d31?d0 (read) t ad t ad t ad t rdh t rds t rdh t rds bs rdy dackn (da) rd t dacd t dacd t dacd t bsd t bsd t bsd t bsd t rsd t rsd csn t rwd t csd t rwd t csd t dacd t dacd t rsd rd/ wr t rdyh t rdys t rdyh t rdys t rdyh t rdys t rdyh t rdys dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.20 burst rom bus cycle (one internal wait + one external wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1022 of 1122 rej09b0370-0400 trw tr tc1 tc2 tc3 tc4/td1 td2 td4 td3 tpc tpc tpc ckio bank prechar g e-sel d31?d0 (read) address row row row h/l t ad t ad t ad t rdh c1 t rds dqmn bs cke ras t casd2 t casd2 cass t dacd t dacd t rasd t rasd t dqmd t dqmd csn t rwd t rwd t bsd t bsd rd/ wr t csd t csd dackn (sa: io memory) column le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.21 synchronous dram auto -precharge read bus cycle: single (rcd [1:0] = 01, cas latency = 3, tpc [2:0] = 011)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1023 of 1122 rej09b0370-0400 trw tr tc1 tc2 tc3 tc4/td1 td2 td4 td3 td5 td6 td7 td8 tpc tpc tpc ckio bank prechar g e-sel d31?d0 (read) address t ad row row h/l c5 row t ad t ad t rdh c1 c2 c3 c4 c5 c6 c7 c8 t rds dqmn bs cke ras t casd2 t casd2 cass t dacd t dacd t rasd t rasd t dqmd t dqmd csn t rwd t rwd t bsd t bsd rd/ wr t csd t csd t ad h/l c1 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.22 synchronous dram au to-precharge read bus cycle: burst (rcd [1:0] = 01, cas latency = 3, tpc [2:0] = 011)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1024 of 1122 rej09b0370-0400 tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 td5 td6 td8 td7 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad row row h/l row c5 t ad h/l c1 t ad t ad t rdh t rds c1 c2 c3 c4 c5 c6 c7 c8 t csd t csd t rwd t rwd t rasd t rasd t bsd t bsd t dqmd t dqmd t dacd t dacd t casd2 t casd2 d31?d0 (read) dackn (sa: io memory) le g end: :io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.23 synchronous dram normal read bus cycle: act + read commands, burst (rasd = 1, rcd [1:0] = 01, cas latency = 3)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1025 of 1122 rej09b0370-0400 tpr tpc tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 td5 td7 td6 td8 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad row row h/l row h/l c1 c5 t ad t ad h/l t ad t ad t rdh t rds c1 c2 c3 c4 c5 c6 c7 c8 t csd t csd t rwd t rwd t rasd t rasd t bsd t bsd t dqmd t dacd t dacd t casd2 t casd2 t dqmd d31?d0 (read) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.24 synchronous dram normal read bus cycle: pre + act + read commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, cas latency = 3)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1026 of 1122 rej09b0370-0400 tc1 tc2 tc3 tc4/td1 td3 td2 td4 td5 td7 td6 td8 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad t ad h/l c1 h/l c5 t rdh t rds c1 c2 c3 c4 c5 c6 c7 c8 t ad t csd t rwd t csd t rwd t rasd t rasd t bsd t bsd t dqmd t dqmd t casd2 t casd2 t dacd t dacd d31?d0 (read) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.25 synchronous dram normal read bus cycle: read command, burst (rasd = 1, cas latency = 3)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1027 of 1122 rej09b0370-0400 trw tr tc1 tc2 tc3 tc4 trwl trwl tpc ckio bank prechar g e-sel address t ad t ad t ad h/l c1 row row row t wdd c1 t wdd dqmn bs cke ras t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd t dqmd csn t bsd t bsd rd/ wr t csd t csd d31?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.26 synchronous dram auto -precharge write bus cycle: single (rcd [1:0] = 01, tpc [2:0] = 001, trwl [2:0] = 010)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1028 of 1122 rej09b0370-0400 trw tr tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 trwl trwl tpc ckio bank precharge-sel address t ad t ad t ad h/l c1 row row row t ad h/l c5 t wdd c1 t wdd c2 c3 c4 c5 c6 c7 c8 dqmn bs cke ras t casd2 t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd csn t bsd t bsd rd/ wr t csd t csd d31?d0 (write) dackn (sa: io memory) t dqmd legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 23.27 synchronous dram au to-precharge write bus cycle: burst (rcd [1:0] = 01, tpc [2:0] = 001, trwl [2:0] = 010)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1029 of 1122 rej09b0370-0400 trw tr tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 trwl trwl ckio bank precharge-sel address t ad t ad t ad h/l c5 h/l c1 row row row t ad t wdd c1 t wdd c2 c3 c4 c5 c6 c7 c8 dqmn bs cke ras t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd t dqmd csn t bsd t bsd rd/ wr t csd t csd d31?d0 (write) dackn (sa: io memory) legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 23.28 synchronous dram normal write bus cycle: act + write commands, burst (rasd = 1, rcd [1:0] = 01, trwl [2:0] = 010)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1030 of 1122 rej09b0370-0400 trw tr tpc tpr tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 trwl trwl ckio bank precharge-sel address t ad t ad t ad h/l h/l c5 h/l c1 row row row t ad t ad t wdd c1 t wdd c2 c3 c4 c5 c6 c7 c8 dqmn bs cke ras t casd2 t casd2 cass t dqmd t dqmd t dacd t rwd t rwd t rasd t rasd t dacd csn t bsd t bsd rd/ wr t csd t csd d31?d0 (write) dackn (sa: io memory) legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 23.29 synchronous dram normal write bus cycle: pre + act + write commands, burst (rasd = 1, rcd [1:0] = 01, tpc [2:0] = 001, trwl [2:0] = 010)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1031 of 1122 rej09b0370-0400 tnop (tnop) tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 trwl trwl t ad t ad h/l c5 h/l c1 t ad t wdd c1 t wdd c2 c3 c4 c6 c7 c8 c5 t dqmd t dqmd t dacd t rwd t rwd t casd2 t casd2 t dacd t rasd t dacd t bsd t bsd t csd t csd ckio bank prechar g e-sel address dqmn bs cke ras cass csn rd/ wr d31?d0 (write) dackn (sa: io memory) normal write sin g le address dma le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h note: in the case of sa-dma only, the (tnop) cycle is inserted, and the dackn si g nal is output as shown by the solid line. in a normal write, the (tnop) cycle is omitted and the dackn si g nal is output as shown by the dotted line. figure 23.30 synchronous dram normal write bus cycle: write command, burst (rasd = 1, trwl [2:0] = 010)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1032 of 1122 rej09b0370-0400 tpc tpr ckio bank prechar g e-sel address t ad t ad h/l row dqmn bs cke ras t casd2 t casd2 cass t dqmd t dqmd t rwd t rwd dackn t rasd t rasd t dacd t dacd csn t bsd t wdd t wdd rd/ wr t csd t csd d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.31 synchronous dram bus cycl e: precharge command (tpc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1033 of 1122 rej09b0370-0400 trr1 trr2 trr3 trr4 trrw trr5 trc trc trc ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn cke t ad t ad t rwd t rwd t dqmd t dqmd t bsd t dacd t wdd t wdd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t rasd t csd t csd t csd t csd t dacd d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.32 synchronous dram bus cycle: auto-refresh (tras = 1, trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1034 of 1122 rej09b0370-0400 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn cke trs1 trs2 trs3 trs4 trs5 trc trc trc t ad t ad t rwd t rwd t dqmd t dqmd t bsd t dacd t dacd t wdd t wdd t casd2 t casd2 t casd2 t cked t cked t casd2 t rasd t rasd t rasd t rasd t csd t csd t csd t csd d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.33 synchronous dram bus cycle: self-refresh (trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1035 of 1122 rej09b0370-0400 trp1 trp2 trp3 trp4 tmw tmw2 tmw4 tmw3 tmw5 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn cke t ad t ad t ad t rwd t rwd t rwd t csd t csd t csd t bsd t dqmd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t dqmd d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.34 (a) synchronous dram bus cycle: mode register setting (pall)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1036 of 1122 rej09b0370-0400 trp1 trp2 trp3 trp4 tmw tmw2 tmw4 tmw3 tmw5 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn cke t ad t ad t ad t rwd t rwd t rwd t csd t csd t csd t bsd t dqmd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t dqmd d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.34 (b) synchronous dram bus cycle: mode register setting (set)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1037 of 1122 rej09b0370-0400 tr2 tr1 trw tc1 tcw tc2 tpc tpc t ad t ad t ad row column t wdd t wdd t wdd t casd1 t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t csd t csd t dacd t dacd t dacd t rwd t rwd t rasd t rasd t rasd t rdh t rds ckio a25?a0 bs ras casn csn rd/ wr tr2 tr1 tc1 tc2 tpc t ad t ad t ad row column t wdd t wdd t wdd t casd1 t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t csd t csd t dacd t dacd t dacd t rwd t rwd t rasd t rasd t rasd t rdh t rds (1) (2) dackn (sa: io memory) dackn (sa: io memory) d31?d0 (read) d31?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.35 d ram bus cycles (1) rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 001 (2) rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 010
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1038 of 1122 rej09b0370-0400 tr2 tr1 tc1 tc2 tce tpc ckio row bs ras casn csn rd/ wr address dackn (sa: io memory) d31?d0 (read) t ad t csd t ad t rasd t rwd t rasd t casd1 t casd1 t dacd t dacd t bsd t bsd t rdh t rds t casd1 t rasd t rwd t csd t ad column le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.36 d ram bus cycle (edo mode, rcd [1:0] = 00, anw [2:0] = 000, trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1039 of 1122 rej09b0370-0400 tr2 tr1 tc1 tc2 tc1 tc2 tc1 tc2 tc1 tc2 tce tpc ckio t ad t ad t ad row c1 c2 c8 bs ras t rasd t rasd t rasd casn csn t rwd t casd1 t casd1 t casd1 t casd1 t casd1 t bsd t bsd rd/ wr t csd t csd t dacd t dacd t dacd t rwd t rdh t rds address dackn (sa: io memory) d31?d0 (read) d1 t rdh t rds d8 d2 le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.37 d ram bus cycle (edo mode, rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1040 of 1122 rej09b0370-0400 tr2 tr1 trw tc1 tcw tc2 tc1 tc2 tcw tc1 tcw tc1 tc2 tce tpc tcw tc2 ckio t ad t ad t ad t rdh d1 t rds t rdh d8 d7 t rds bs ras t rasd t rasd csn casn row c1 c2 c8 rd/ wr t csd t csd t casd1 t casd1 t casd1 t casd1 t rasd t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t rwd t rwd address dackn (sa: io memory) d31?d0 (read) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.38 dram burst bus cycle (edo mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1041 of 1122 rej09b0370-0400 tr2 tr1 trw tc1 tcw tc2 tcnw tcw tc1 tc2 tc2 tcw tcnw tc1 tcw tcw tc1 tc2 tcnw tce tpc ckio t ad t ad t ad t rdh d1 t rds t rdh d8 d2 t rds bs ras t rasd t rasd csn casn row c1 c2 c8 rd/ wr t csd t csd t casd1 t casd1 t casd1 t rasd t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t rwd t rwd address dackn (sa: io memory) d31?d0 (read) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.39 dram burst bus cycle (edo mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001, 2-cycle cas negate pulse width)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1042 of 1122 rej09b0370-0400 tr1 t ad row tc1 tc2 tc1 tc2 tr2 tpc c1 c2 c8 ckio csn rd/ wr ras casn bs t ad t ad t rdh t rds t rdh t rds t csd t rwd t rwd t csd t casd1 t rasd t rasd t casd1 t casd1 t casd1 t casd1 d8 d2 d1 t bsd t bsd t dacd t dacd t dacd tc1 tc1 tc2 tce tc2 address dackn (sa: io memory) d31?d0 (read) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.40 dram burst bus cycle: ras down mode state (edo mode, rcd [1:0] = 00, anw [2:0] = 000)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1043 of 1122 rej09b0370-0400 tnop tc2 tc1 tc2 tc1 tc1 c1 c2 c8 ckio address csn rd/ wr ras casn bs t ad t ad t ad t rdh t rds t rdh t rds t csd t rwd t rwd t rasd ras-down mode ended t csd t casd1 t casd1 t casd1 t casd1 d8 d2 d1 t bsd t bsd t dacd t dacd tc2 t2 tc1 tce dackn (sa: io memory) d31?d0 (read) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.41 dram burst bus cycle: ras down mode continuation (edo mode, rcd [1:0] = 00, anw [2:0] = 000)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1044 of 1122 rej09b0370-0400 tr1 tr2 tc1 tc2 tc1 tc2 tc2 tc1 tc1 tc2 tpc ckio address csn rd/ wr ras casn d31?d0 (read) d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) t ad c1 row c2 c8 t ad t ad t rwd t rwd t rdh t rds d1 t wdd d1 d2 d8 t bsd t bsd t wdd d2 t rdh t wdd t rds d8 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.42 dram burst bus cycle (fast page mode, rcd [1:0] = 00, anw [2:0] = 000, tpc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1045 of 1122 rej09b0370-0400 tr1 tr2 trw tc1 tcw tc2 tcw tc1 tc2 tc1 tcw ckio csn rd/ wr ras casn bs t ad c1 row c2 c8 t ad t ad t rwd t rwd t rdh t rds d1 t wdd d1 d2 d8 t bsd t bsd t wdd d2 t rdh t wdd t rds d3 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd tc1 tc2 tc2 tcw tpc address d31?d0 (read) d31?d0 (write) dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.43 dram burst bus cycle (fast page mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1046 of 1122 rej09b0370-0400 tr1 tr2 trw tc1 tcw tc2 tc1 tcnw tcw tc2 tcw ckio csn rd/ wr ras casn bs t ad c1 row c2 c8 t ad t ad t rwd t rwd t rdh t rds d1 t wdd d1 d2 d8 t bsd t bsd t wdd d2 t rdh t wdd t rds d8 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd tcw tc1 tcnw tc2 tc1 tpc tc2 tcnw tcw address d31?d0 (read) d31?d0 (write) dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.44 dram burst bus cycle (fast page mode, rcd [1:0] = 01, anw [2:0] = 001, tpc [2:0] = 001, 2-cycle cas negate pulse width)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1047 of 1122 rej09b0370-0400 tpc tr1 tr2 tc1 tc2 tc1 tc1 tc2 tc2 tc1 tc2 ckio address csn rd/ wr ras casn d31?d0 (read) d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) t ad c1 row c2 c8 t ad t ad t rwd t rwd t rdh t rds d1 t wdd t wdd d1 d2 d8 t bsd t bsd t wdd d2 t rdh t wdd t rds d8 t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t dacd t dacd t dacd t rasd t rasd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.45 dram burst bus cycle: ras down mode state (fast page mode, rcd [1:0] = 00, anw [2:0] = 000)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1048 of 1122 rej09b0370-0400 ckio csn rd/ wr ras casn bs t ad c1 c2 c8 t ad t rwd t rdh t rds d1 d1 d2 d8 t bsd t bsd t wdd d2 t rdh t wdd t rds d8 t wdd t csd t rasd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t dacd t dacd tnop tc1 tc2 tc1 tc1 tc2 tc2 tc1 tc2 address d31?d0 (read) d31?d0 (write) dackn (sa: io memory) dackn (sa: io memory) ras down mode ended le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.46 dram burst bus cycle: ras down mode continuation (fast page mode, rcd [1:0] = 00, anw [2:0] = 000)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1049 of 1122 rej09b0370-0400 trr1 trr2 trr3 trr4 trr5 trc trc trc ckio a25?a0 csn rd/ wr ras casn d31?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.47 dram bus cycle: dram cas- before-ras refresh (tras [2:0] = 000, trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1050 of 1122 rej09b0370-0400 trr1 trr2 trr3 trr4 trr5 trr4w trc trc trc ckio csn rd/ wr ras casn bs t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 a25?a0 d31?d0 (write) dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.48 dram bus cycle: dram cas- before-ras refresh (tras [2:0] = 001, trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1051 of 1122 rej09b0370-0400 trr1 trr2 trr3 trr4 trr5 trc trc trc ckio csn rd/ wr ras casn bs t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 a25?a0 d31?d0 (write) dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.49 dram bu s cycle: dram self-refresh (trc [2:0] = 001)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1052 of 1122 rej09b0370-0400 tpcm1 tpcm2 tpcm0 tpcm1 tpcm2 tpcm1w tpcm1w tpcm2w ckio cexx reg (we0) rd/wr rd d15?d0 (read) d15?d0 (write) bs dackn (da) rdy we1 t ad t ad t wdd t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd ted teh t rdh t rds t dacd (1) (2) a25?a0 legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 23.50 pcmc ia memory bus cycle (1) ted [2:0] = 000, teh [2:0] = 000, no wait (2) ted [2:0] = 001, teh [2:0] = 001, one internal wait + one external wait
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1053 of 1122 rej09b0370-0400 tpci1 tpci2 tpci0 tpci1 tpci2 tpci1w tpci1w tpci2w ckio cexx reg ( we0 ) rd/ wr iciord ( we2 ) bs dackn (da) rdy iois16 iciowr ( we3 ) t ad t ad t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icwsdf t icwsdf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t io16h t io16s t io16h t io16s t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icrsd t icwsdf t icwsdf t icwsdf t dacd t rdh t rds t dacd d15?d0 (read) d15?d0 (write) (1) (2) a25?a0 le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.51 pcmc ia i/o bus cycle (1) ted [2:0] = 000, teh [2:0] = 000, no wait (2) ted [2:0] = 001, teh [2:0] = 001, one internal wait + one external wait
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1054 of 1122 rej09b0370-0400 tpci0 tpci1 tpci2w tpci2 tpci1w tpci0 tpci1 tpci2w tpci2 tpci1w ckio a25?a1 a0 cexx reg ( we0 ) rd/ wr iciord ( we2 ) d15?d0 (read) d15?d0 (write) bs rdy iois16 iciowr ( we3 ) t bsd t bsd t ad t ad t wdd t wdd t wdd t wdd t wdd t rwd t rwd t ad t csd t csd t csd t icrsd t icrsd t icrsd t icwsdf t icwsdf t icwsdf t icwsdf t icwsdf t rdh t rds t rdys t rdyh t io16s t io16h t rdys t rdyh le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.52 pcmc ia i/o bus cycle (ted [2:0] = 001, teh [2:0] = 001, one internal wait, bus sizing)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1055 of 1122 rej09b0370-0400 tm1 tmd1w tmd1 tm0 tmd1w tmd1 tmd1w ckio csn rd/ wr wen d63?d0 bs dackn (da) rdy rd / frame t fmd t fmd t bsd t bsd t bsd t bsd t csd t csd t dacd t rdh t rds d0 t rdyh t rdys t dacd t rwd t rwd t wed1 t wed1 t fmd t fmd t csd t csd t rdh t rds t wdd ad0 t wdd t wdd a t wdd t rwd t rwd t wed1 t wed1 t dacd t dacd t rdyh t rdys t rdyh t rdys 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address (1) (2) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.53 mpx basic bus cycle: read (1) 1st data (one internal wait) (2) 1st data (one internal wait + one external wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1056 of 1122 rej09b0370-0400 tm1 tmd1w tmd1 ckio csn rd/ wr wen d63?d0 bs dackn (da) rdy rd / frame t fmd t fmd t bsd t bsd t csd t csd t dacd t rdyh t rdys t dacd t wed1 t wed1 tm1 tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd d0 d0 t rdyh t rdys t dacd t rwd t rwd t rwd t rwd t wed1 t wed1 a t rdyh t rdys t rdyh t rdys t wdd t wdd t wdd a t wdd t wdd t wdd tm1 tmd1w tmd1w tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd t dacd t wed1 t wed1 d0 t rwd t rwd a t wdd t wdd t wdd (1) (2) (3) 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.54 mpx basic bus cycle: write (1) 1st data (no wait) (2) 1st data (one internal wait) (3) 1st data (one internal wait + one external wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1057 of 1122 rej09b0370-0400 ckio csn rd/ wr d31?d0 bs dackn (da) rdy rd / frame tm1 tmd1w tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t dacd t dacd d4 t rwd t rwd a t wdd d3 d2 d1 d7 d6 d5 d8 t wdd t rdh t rds tm1 tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd d8 t rwd t rwd a t wdd d7 d3 d1 d2 t wdd t rdh t rds t rdys t rdyh t rdyh (1) (2) 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.55 mpx bus cycle: burst read (1) 1st data (one internal wait), 2nd to 8th data (no internal wait) (2) 1st data (no internal wait), 2nd to 8th data (no internal wait + external wait control)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1058 of 1122 rej09b0370-0400 ckio csn rd/ wr d31?d0 bs dackn (da) rdy rd / frame tm1 tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd d4 t rwd t rwd a t wdd d3 d2 d1 d7 d6 d5 d8 d8 d7 d2 d1 d3 t wdd t wdd tm1 tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd t rwd t rwd a t wdd t wdd t wdd t rdys t rdyh (1) 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d31?d29: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address (2) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.56 mpx bus cycle: burst write (1) no internal wait (2) 1st data (one internal wait), 2nd to 8th data (no internal wait + external wait control)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1059 of 1122 rej09b0370-0400 t1 tw t2 ckio csn rd/ wr rd (1) wen d31?d0 (read) bs dackn (da) rdy a25?a0 t dacd t dacd t csd t csd t dacd t rdyh t rdys t dacd t dacd t rwd t rwd t1 t2 t dacd t dacd t csd t csd t dacd t dacd t wed1 t dacd t rwd t rwd t rdyh t rdys t rdyh t rdys t ad t ad t ad t ad t1 tw twe t2 t dacd t dacd t rsd t rsd t rsd t rsd t rsd t rsd t rsd t rsd t wed1 t wed1 t wedf t wed1 t wedf t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t bsd t bsd t bsd t bsd t dacd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds t rdh t rds t rdh t rds dackn (sa: io memory) (2) (3) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.57 memory byte control sram bus cycles (1) basic read cycle (no wait) (2) basic read cycle (one internal wait) (3) basic read cycle (one internal wait + one external wait)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1060 of 1122 rej09b0370-0400 ckio csn rd/ wr rd wen d31?d0 (read) bs dackn (da) rdy a25?a0 ts1 t1 t2 th1 t rsd t rsd t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds dackn (sa: io memory) t dacd t dacd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 23.58 memory byte control sram bu s cycle: basic read cycle (no wait, address setup/hold time insertion, ans [0] = 1, anh [1:0] = 01)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1061 of 1122 rej09b0370-0400 23.3.4 peripheral mo dule signal timing table 23.23 peripheral module signal timing (1) hd6417751 rbp240 (v) hd6417751 rbg240 (v) hd6417751 rbp200 (v) hd6417751 rbg200 (v) hd6417751 rf240 (v) hd6417751 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure notes tmu, rtc timer clock pulse width (high) t tclkwh 4 ? 4 ? 4 ? 4 ? pcyc * 1 23.59 timer clock pulse width (low) t tclkwl 4 ? 4 ? 4 ? 4 ? pcyc * 1 23.59 timer clock rise time t tclkr ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 23.59 timer clock fall time t tclkf ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 23.59 oscillation settling time t rosc ? 3 ? 3 ? 3 ? 3 s 23.60 sci input clock cycle (asyn- chronous) t scyc 4 ? 4 ? 4 ? 4 ? pcyc * 1 23.61 input clock cycle (syn- chronous) t scyc 6 ? 6 ? 6 ? 6 ? pcyc * 1 23.61 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t scyc 23.61 input clock rise time t sckr ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 23.61 input clock fall time t sckf ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 23.61 transfer data delay time t txd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.62 receive data setup time (synchronous) t rxs 16 ? 16 ? 16 ? 16 ? ns 23.62 receive data hold time (synchronous) t rxh 16 ? 16 ? 16 ? 16 ? ns 23.62 i/o ports output data delay time t portd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.63 input data setup time t ports 2 ? 2.5 ? 3.5 ? 3.5 ? ns 23.63 input data hold time t porth 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 23.63
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1062 of 1122 rej09b0370-0400 hd6417751 rbp240 (v) hd6417751 rbg240 (v) hd6417751 rbp200 (v) hd6417751 rbg200 (v) hd6417751 rf240 (v) hd6417751 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure notes dmac dreqn setup time t drqs 2 ? 2.5 ? 3.5 ? 3.5 ? ns 23.64 dreqn hold time t drqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 23.64 drakn delay time t drakd 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.64 intc nmi pulse width (high) t nmih 5 ? 5 ? 5 ? 5 ? t cyc 23.69 normal or sleep mode 30 ? 30 ? 30 ? 30 ? ns 23.69 standby mode nmi pulse width (low) t nmil 5 ? 5 ? 5 ? 5 ? t cyc 23.69 normal or sleep mode 30 ? 30 ? 30 ? 30 ? ns 23.69 standby mode input clock cycle t tckcyc 50 ? 50 ? 50 ? 50 ? ns 23.65, 23.67 input clock pulse width (high) t tckh 15 ? 15 ? 15 ? 15 ? ns 23.65 input clock pulse width (low) t tckl 15 ? 15 ? 15 ? 15 ? ns 23.65 input clock rise time t tckr ? 10 ? 10 ? 10 ? 10 ns 23.65 input clock fall time t tckf ? 10 ? 10 ? 10 ? 10 ns 23.65 asebrk setup time t asebrks 10 ? 10 ? 10 ? 10 ? t cyc 23.66 asebrk hold time t asebrkh 10 ? 10 ? 10 ? 10 ? t cyc 23.66 tdi/tms setup time t tdis 15 ? 15 ? 15 ? 15 ? ns 23.67 tdi/tms hold time t tdih 15 ? 15 ? 15 ? 15 ? ns 23.67 h-udi tdo delay time t tdo 0 10 0 10 0 10 0 10 ns 23.67 ase-pinbrk pulse width t pinbrk 2 ? 2 ? 2 ? 2 ? pcyc * 1 23.68 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1063 of 1122 rej09b0370-0400 table 23.24 peripheral module signal timing (2) hd6417751bp167 (v) hd6417751f167 (v) * 2 module item symbol min max unit figure notes tmu, rtc timer clock pulse width (high) t tclkwh 4 ? pcyc * 1 23.59 timer clock pulse width (low) t tclkwl 4 ? pcyc * 1 23.59 timer clock rise time t tclkr ? 0.8 pcyc * 1 23.59 timer clock fall time t tclkf ? 0.8 pcyc * 1 23.59 oscillation settling time t rosc ? 3 s 23.60 sci input clock cycle (asynchronous) t scyc 4 ? pcyc * 1 23.61 input clock cycle (synchronous) t scyc 6 ? pcyc * 1 23.61 input clock pulse width t sckw 0.4 0.6 t scyc 23.61 input clock rise time t sckr ? 0.8 pcyc * 1 23.61 input clock fall time t sckf ? 0.8 pcyc * 1 23.61 transfer data delay time t txd ? 30 ns 23.62 receive data setup time (synchronous) t rxs 0.8 ? pcyc * 1 23.62 receive data hold time (synchronous) t rxh 0.8 ? pcyc * 1 23.62 i/o ports output data delay time t portd ? 8 ns 23.63 input data setup time t ports 3.5 ? ns 23.63 input data hold time t porth 1.5 ? ns 23.63 dmac dreqn setup time t drqs 3.5 ? ns 23.64 dreqn hold time t drqh 1.5 ? ns 23.64 drakn delay time t drakd ? 8 ns 23.64
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1064 of 1122 rej09b0370-0400 hd6417751bp167 (v) hd6417751f167 (v) * 2 module item symbol min max unit figure notes nmi pulse width (high) t nmih 5 ? t cyc 23.69 normal or sleep mode 30 ? ns 23.69 standby mode nmi pulse width (low) t nmil 5 ? t cyc 23.69 normal or sleep mode intc 30 ? ns 23.69 standby mode input clock cycle t tckcyc 50 ? ns 23.65, 23.67 input clock pulse width (high) t tckh 15 ? ns 23.65 input clock pulse width (low) t tckl 15 ? ns 23.65 input clock rise time t tckr ? 10 ns 23.65 input clock fall time t tckf ? 10 ns 23.65 asebrk setup time t asebrks 10 ? t cyc 23.66 asebrk hold time t asebrkh 10 ? t cyc 23.66 tdi/tms setup time t tdis 15 ? ns 23.67 tdi/tms hold time t tdih 15 ? ns 23.67 h-udi tdo delay time t tdo 0 10 ns 23.67 ase-pinbrk pulse width t pinbrk 2 ? pcyc * 1 23.68 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf, pll2 on
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1065 of 1122 rej09b0370-0400 tclk t tclkf t tclkwh t tclkwl t tclkr figure 23.59 tclk input timing rtc internal clock v dd -rtc oscillation settlin g time t rosc v dd -rtc min figure 23.60 rtc oscillation settling time at power-on sck, sck2 t sckf t scyc t sckw t sckr figure 23.61 sck input clock timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1066 of 1122 rej09b0370-0400 t txd sck txd rxd t txd t rxs t rxh t scyc figure 23.62 sci i/o synchronous mode clock timing t portd t portd ckio ports 31?0 (read) ports 31?0 (write) t ports t porth figure 23.63 i/o port input/output timing t drakd t drqh t drqh t drqs t drqs ckio dreqn drakn figure 23.64 (a) dreq /drak timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1067 of 1122 rej09b0370-0400 t dbqh t dbqs ckio d31 to d0 (read) dbreq bavl tr t bavd t bavd t trh (2) t trs t dtrh t dtrs (1) (1): [2ckio cycle ? t dtrs ] (= 18 ns: 100 mhz) (2): dtr = 1ckio cycle (= 10 ns: 100 mhz) (t dtrs + t dtrh ) < dtr < 10 ns figure 23.64 (b) dbreq / tr input timing and bavl output timing t tckcyc t tckh t tckl t tckr t tckf 1/2v ddq v ih v ih v il v il v ih 1/2v ddq note: when clock is input from tck pin figure 23.65 tck input timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1068 of 1122 rej09b0370-0400 asebrk / brkack reset t asebrkh t asebrks figure 23.66 reset hold timing tdi tms tck tdo t tckcyc t tdo t tdih t tdis figure 23.67 h-udi data transfer timing asebrk t pinbrk figure 23.68 pin break timing nmi t nmil t nmih figure 23.69 nmi input timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1069 of 1122 rej09b0370-0400 table 23.25 pcic signal timing (i n pcireq/pcignt non-port mode) (1) hd6417751rbp240 (v), hd6417751rbp200 (v), hd6417751rbg240 (v), hd6417751rbg200 (v), hd6417751rf240 (v), hd6417751rf200 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf 33 mhz 66 mhz pin item symbol min max min max unit figure clock cycle t pcicyc 30 ? 15 30 ns 23.70 clock pulse width (high) t pcihigh 11 ? 6 ? ns 23.70 clock pulse width (low) t pcilow 11 ? 6 ? ns 23.70 clock rise time t pcir ? 4 ? 1.5 ns 23.70 pciclk clock fall time t pcif ? 4 ? 1.5 ns 23.70 pcirst output data delay time t pcival ? 10 ? 8 ns 23.71 input hold time t pcih 1.5 ? 1.5 ? ns 23.72 idsel input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 output data delay time t pcival ? 10 ? 8 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 input hold time t pcih 1.5 ? 1.5 ? ns 23.72 ad31?ad0 c/ be3 ?c/ be0 par pciframe irdy trdy pcistop pcilock devsel perr input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 output data delay time t pcival ? 10 ? 8 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 12 ns 23.71 input hold time t pcih 1.5 ? 1.5 ? ns 23.72 pcireq1 / gntin pcireq2 / md9 pcireq3 / md10 pcireq4 / pcignt1 / reqout pcignt4 ? pcignt1 input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * )? ns 23.72 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 serr inta tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 note: * hd6417751rf240 (v), hd6417751rf200 (v)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1070 of 1122 rej09b0370-0400 table 23.26 pcic signal timing (i n pcireq/pcignt non-port mode) (2) hd6417751bp167 (v), hd6417751f167 (v): v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf 33 mhz 66 mhz pin item symbol min max min max unit figure clock cycle t pcicyc 30 ? 15 30 ns 23.70 clock pulse width (high) t pcihigh 11 ? 6 ? ns 23.70 clock pulse width (low) t pcilow 11 ? 6 ? ns 23.70 clock rise time t pcir ? 4 ? 1.5 ns 23.70 pciclk clock fall time t pcif ? 4 ? 1.5 ns 23.70 pcirst output data delay time t pcival ? 10 ? 10 ns 23.71 input hold time t pcih 1 ? 1 ? ns 23.72 idsel input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 output data delay time t pcival ? 10 ? 10 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 input hold time t pcih 1 ? 1 ? ns 23.72 ad31?ad0 c/ be3 ?c/ be0 par pciframe irdy trdy pcistop pcilock devsel perr input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 output data delay time t pcival ? 10 ? 10 ns 23.71 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 tri-state high-impedance delay time t pcioff ? 12 12 ns 23.71 input hold time t pcih 1 ? 1 ? ns 23.72 pcireq1 / gntin pcireq2 / md9 pcireq3 / md10 pcireq4 / pcignt1 / reqout pcignt4 ? pcignt1 input setup time t pcisu 3.0 (3.5 * ) ? 3.0 (3.5 * ) ? ns 23.72 tri-state drive delay time t pcion ? 10 ? 10 ns 23.71 serr inta tri-state high-impedance delay time t pcioff ? 12 ? 12 ns 23.71 note: * hd6417751f167 (v)
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1071 of 1122 rej09b0370-0400 0.5v ddq v h v h t pcif t pcir v l v l 0.5v ddq v h t pcilow t pcihigh t pcicyc figure 23.70 pci clock input timing pciclk 0.4v ddq 0.4v ddq t pcion t pcioff t pcival output delay 3-state output figure 23.71 output signal timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1072 of 1122 rej09b0370-0400 pciclk t pcisu t pcih 0.4v ddq 0.4v ddq 0.4v ddq input figure 23.72 output signal timing table 23.27 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (1) hd6417751rbp240 (v), hd6417751rbp200 (v), hd6417751rbg240 (v), hd6417751rbg200 (v), hd6417751rf240 (v), hd6417751rf200 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to 75 c, c l = 30 pf pin item symbol min max unit figure output data delay time t pciportd ? 10 ns 23.73 input hold time t pciporth 1.5 ? ns 23.73 pcireq2 /md9 pcireq3 /md10 pcireq4 input setup time t pciports 3.5 ? ns 23.73 pcignt4 ? pcignt1 output data delay time t pciportd ? 10 ns 23.73 table 23.28 pcic signal timing (with pcireq/pcignt port settings in non-host mode) (2) hd6417751bp167 (v), hd6417751f167 (v): v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to 75 c, c l = 30 pf pin item symbol min max unit figure output data delay time t pciportd ? 10 ns 23.73 input hold time t pciporth 1.5 ? ns 23.73 pcireq2 /md9 pcireq3 /md10 pcireq4 input setup time t pciports 3.5 ? ns 23.73 pcignt4 ? pcignt1 output data delay time t pciportd ? 10 ns 23.73
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1073 of 1122 rej09b0370-0400 ckio pcireqn (read) pcireqn pcigntn (write) t pciporth t pciportd t pciportd t pciports figure 23.73 i/o port input/output timing
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1074 of 1122 rej09b0370-0400 23.3.5 ac characteristic test conditions the ac characteristic test conditions are as follows: ? input/output signal reference level: 1.5 v (v ddq = 3.3 0.3 v) ? input pulse level: v ssq to 3.0 v (v ssq to v ddq for reset , trst , nmi, and asebrk /brkack) ? input rise/fall time: 1 ns the output load circuit is shown in figure 23.74 i ol i oh c l v ref lsi output pin dut output notes: 1. 2. c l is the total value, includin g the capacitance of the test ji g , etc. the capacitance of each pin is set to 30 pf. i ol and i oh values are as shown in table 23.10, permissible output currents. figure 23.74 output load circuit
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1075 of 1122 rej09b0370-0400 23.3.6 change in delay time based on load capacitance figure 23.75 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larg er than the stipulated value (30 pf) is connected to the lsi pins. when connecting an external device w ith a load capacitance exceeding the regulation, use the chart in figure 23.75 as reference for system design. note that if the load capacitance to be connec ted exceeds the range shown in figure 23.75 the graph will not be a straight line. +4.0 ns +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pf +25 pf +50 pf load capacitance delay time figure 23.75 load capacitance ? delay time
23. electrical characteristics rev.4.00 oct. 10, 2008 page 1076 of 1122 rej09b0370-0400
a. address list rev.4.00 oct. 10, 2008 page 1077 of 1122 rej09b0370-0400 appendix a address list table a.1 address list module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock pcic pcimem h'fd00 0000 to h'fdff ffff h'fd00 0000 to h'fdff ffff 8, 16, 32 according to pci memory space pck intc intpri00 h'fe08 0000 h'1e08 0000 32 h'0000 0000 held held held pck intc intreq00 h'fe08 0020 h'1e08 0020 32 h'0000 0000 held held held pck intc intmsk00 h'fe08 0040 h'1e08 0040 32 h'0000 03ff held held held pck intc intmskclr 00 h'fe08 0060 h'1e08 0060 32 write-only pck cpg clkstp00 h'fe0a 0000 h'1e0a 0000 32 h'0000 0000 held held held pck cpg clkstpclr 00 h'fe0a 0008 h'1e0a 0008 32 write-only pck tmu tstr2 h'fe10 0004 h'1e10 0004 8 h'00 held held held pck tmu tcor3 h'fe10 0008 h'1e10 0008 32 h'ffff ffff held held held pck tmu tcnt3 h'fe10 000c h'1e10 000c 32 h'ffff ffff held held held pck tmu tcr3 h'fe10 0010 h'1e10 0010 16 h'0000 held held held pck tmu tcor4 h'fe10 0014 h'1e10 0014 32 h'ffff ffff held held held pck tmu tcnt4 h'fe10 0018 h'1e10 0018 32 h'ffff ffff held held held pck tmu tcr4 h'fe10 001c h'1e10 001c 16 h'0000 held held held pck pcic pciconf0 h'fe20 0000 h'1e20 0000 32 h'35051054 (sh7751)/ h'350e1054 (sh7751r) held held held pck pcic pciconf1 h'fe20 0004 h'1e20 0004 32 h'02900080 held held held pck pcic pciconf2 h'fe20 0008 h'1e20 0008 32 undefined held held held pck pcic pciconf3 h'fe20 000c h'1e20 000c 32 h'00000000 held held held pck pcic pciconf4 h'fe20 0010 h'1e20 0010 32 h'00000001 held held held pck
a. address list rev.4.00 oct. 10, 2008 page 1078 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock pcic pciconf5 h'fe20 0014 h'1e20 0014 32 h'00000000 held held held pck pcic pciconf6 h'fe20 0018 h'1e20 0018 32 h'00000000 held held held pck pcic pciconf7 h'fe20 001c h'1e20 001c 32 h'00000000 held held held pck pcic pciconf8 h'fe20 0020 h'1e20 0020 32 h'00000000 held held held pck pcic pciconf9 h'fe20 0024 h'1e20 0024 32 h'00000000 held held held pck pcic pciconf10 h'fe20 0028 h'1e20 0028 32 h'00000000 held held held pck pcic pcicon111 h'fe20 002c h'1e20 002c 32 undefined held held held pck pcic pciconf12 h'fe20 0030 h'1e20 0030 32 h'00000000 held held held pck pcic pciconf13 h'fe20 0034 h'1e20 0034 32 h'00000040 held held held pck pcic pciconf14 h'fe20 0038 h'1e20 0038 32 h'00000000 held held held pck pcic pciconf15 h'fe20 003c h'1e20 003c 32 h'00000100 held held held pck pcic pciconf16 h'fe20 0040 h'1e20 0040 32 h'00010001 held held held pck pcic pciconf17 h'fe20 0044 h'1e20 0044 32 h'00000000 held held held pck pcic pcicr h'fe20 0100 h'1e20 0100 * 2 32 h'00000000 held held held pck pcic pcilsr0 h'fe20 0104 h'1e20 0104 32 h'00000000 held held held pck pcic pcilsr1 h'fe20 0108 h'1e20 0108 32 h'00000000 held held held pck pcic pcilar0 h'fe20 010c h'1e20 010c 32 h'00000000 held held held pck pcic pcilar1 h'fe20 0110 h'1e20 0110 32 h'00000000 held held held pck pcic pciint h'fe20 0114 h'1e20 0114 32 h'00000000 held held held pck pcic pciintm h'fe20 0118 h'1e20 0118 32 h'00000000 held held held pck pcic pcialr h'fe20 011c h'1e20 011c 32 undefined held held held pck pcic pciclr h'fe20 0120 h'1e20 0120 32 undefined held held held pck pcic pciaint h'fe20 0130 h'1e20 0130 32 h'00000000 held held held pck pcic pciaintm h'fe20 0134 h'1e20 0134 32 h'00000000 held held held pck pcic pcibllr h'fe20 0138 h'1e20 0138 32 undefined held held held pck pcic pcidmabt h'fe20 0140 h'1e20 0140 32 h'00000000 held held held pck pcic pcidpa0 h'fe20 0180 h'1e20 0180 32 h'00000000 held held held pck pcic pcidla0 h'fe20 0184 h'1e20 0184 32 h'00000000 held held held pck pcic pcidtc0 h'fe20 0188 h'1e20 0188 32 h'00000000 held held held pck
a. address list rev.4.00 oct. 10, 2008 page 1079 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock pcic pcidcr0 h'fe20 018c h'1e20 018c 32 h'00000000 held held held pck pcic pcidpa1 h'fe20 0190 h'1e20 0190 32 h'00000000 held held held pck pcic pcidla1 h'fe20 0194 h'1e20 0194 32 h'00000000 held held held pck pcic pcidtc1 h'fe20 0198 h'1e20 0198 32 h'00000000 held held held pck pcic pcidcr1 h'fe20 019c h'1e20 019c 32 h'00000000 held held held pck pcic pcidpa2 h'fe20 01a0 h'1e20 01a0 32 h'00000000 held held held pck pcic pcidla2 h'fe20 01a4 h'1e20 01a4 32 h'00000000 held held held pck pcic pcidtc2 h'fe20 01a8 h'1e20 01a8 32 h'00000000 held held held pck pcic pcidcr2 h'fe20 01ac h'1e20 01ac 32 h'00000000 held held held pck pcic pcidpa3 h'fe20 01b0 h'1e20 01b0 32 h'00000000 held held held pck pcic pcidla3 h'fe20 01b4 h'1e20 01b4 32 h'00000000 held held held pck pcic pcidtc3 h'fe20 01b8 h'1e20 01b8 32 h'00000000 held held held pck pcic pcidcr3 h'fe20 01bc h'1e20 01bc 32 h'00000000 held held held pck pcic pcipar h'fe20 01c0 h'1e20 01c0 32 undefined held held held pck pcic pcimbr h'fe20 01c4 h'1e20 01c4 32 undefined held held held pck pcic pciiobr h'fe20 01c8 h'1e20 01c8 32 undefined held held held pck pcic pcipint h'fe20 01cc h'1e20 01cc 32 h'00000000 held held held pck pcic pcipintm h'fe20 01d0 h'1e20 01d0 32 h'00000000 held held held pck pcic pciclkr h'fe20 01d4 h'1e20 01d4 32 h'00000000 held held held pck pcic pcibcr1 h'fe20 01e0 h'1e20 01e0 32 h'00000000 held held held pck pcic pcibcr2 h'fe20 01e4 h'1e20 01e4 32 h'00003ffc held held held pck pcic pcibcr3 h'fe20 01f8 h'1e20 01f8 32 h'0000 0001 held held held pck pcic pciwcr1 h'fe20 01e8 h'1e20 01e8 32 h'7777 7777 held held held pck pcic pciwcr2 h'fe20 01ec h'1e20 01ec 32 h'fffe efff held held held pck pcic pciwcr3 h'fe20 01f0 h'1e20 01f0 32 h'0777 7777 held held held pck pcic pcimcr h'fe20 01f4 h'1e20 01f4 32 h'0000 0000 held held held pck pcic pcipctr h'fe20 0200 h'1e20 0200 32 h'00000000 held held held pck pcic pcipdtr h'fe20 0204 h'1e20 0204 32 h'00000000 held held held pck pcic pcipdr h'fe20 0220 h'1e20 0220 32 undefined held held held pck
a. address list rev.4.00 oct. 10, 2008 page 1080 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock pcic pciio h'fe24 0000 to h'fe27 ffff h'1e24 0000 to h'1e27 ffff 8, 16, 32 according to pci i/o space pck ccn pteh h'ff00 0000 h'1f00 0000 32 undefined undefined held held ick ccn ptel h'ff00 0004 h'1f00 0004 32 undefined undefined held held ick ccn ttb h'ff00 0008 h'1f00 0008 32 undefined undefined held held ick ccn tea h'ff00 000c h'1f00 000c 32 undefined held held held ick ccn mmucr h'ff00 0010 h'1f00 0010 32 h'0000 0000 h'0000 0000 held held ick ccn basra h'ff00 0014 h'1f00 0014 8 undefined held held held ick ccn basrb h'ff00 0018 h'1f00 0018 8 undefined held held held ick ccn ccr h'ff00 001c h'1f00 001c 32 h'0000 0000 h'0000 0000 held held ick ccn tra h'ff00 0020 h'1f00 0020 32 undefined undefined held held ick ccn expevt h'ff00 0024 h'1f00 0024 32 h'0000 0000 h'0000 0020 held held ick ccn intevt h'ff00 0028 h'1f00 0028 32 undefined undefined held held ick ccn ptea h'ff00 0034 h'1f00 0034 32 undefined undefined held held ick ccn qacr0 h'ff00 0038 h'1f00 0038 32 undefined undefined held held ick ccn qacr1 h'ff00 003c h'1f00 003c 32 undefined undefined held held ick ubc bara h'ff20 0000 h'1f20 0000 32 undefined held held held ick ubc bamra h'ff20 0004 h'1f20 0004 8 undefined held held held ick ubc bbra h'ff20 0008 h'1f20 0008 16 h'0000 held held held ick ubc barb h'ff20 000c h'1f20 000c 32 undefined held held held ick ubc bamrb h'ff20 0010 h'1f20 0010 8 undefined held held held ick ubc bbrb h'ff20 0014 h'1f20 0014 16 h'0000 held held held ick ubc bdrb h'ff20 0018 h'1f20 0018 32 undefined held held held ick ubc bdmrb h'ff20 001c h'1f20 001c 32 undefined held held held ick ubc brcr h'ff20 0020 h'1f20 0020 16 h'0000 * 2 held held held ick bsc bcr1 h'ff80 0000 h'1f80 0000 32 h'0000 0000 held held held bck bsc bcr2 h'ff80 0004 h'1f80 0004 16 h'3ffc held held held bck bsc bcr3 h'ff80 0050 h'1f80 0050 16 h'0000 held held held bck bsc bcr4 h'fe0a 00f0 h'1e0a 00f0 32 h'0000 0000 held held held bck
a. address list rev.4.00 oct. 10, 2008 page 1081 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock bsc wcr1 h'ff80 0008 h'1f80 0008 32 h'7777 7777 held held held bck bsc wcr2 h'ff80 000c h'1f80 000c 32 h'fffe efff held held held bck bsc wcr3 h'ff80 0010 h'1f80 0010 32 h'0777 7777 held held held bck bsc mcr h'ff80 0014 h'1f80 0014 32 h'0000 0000 held held held bck bsc pcr h'ff80 0018 h'1f80 0018 16 h'0000 held held held bck bsc rtcsr h'ff80 001c h'1f80 001c 16 h'0000 held held held bck bsc rtcnt h'ff80 0020 h'1f80 0020 16 h'0000 held held held bck bsc rtcor h'ff80 0024 h'1f80 0024 16 h'0000 held held held bck bsc rfcr h'ff80 0028 h'1f80 0028 16 h'0000 held held held bck bsc pctra h'ff80 002c h'1f80 002c 32 h'0000 0000 held held held bck bsc pdtra h'ff80 0030 h'1f80 0030 16 undefined held held held bck bsc pctrb h'ff80 0040 h'1f80 0040 32 h'0000 0000 held held held bck bsc pdtrb h'ff80 0044 h'1f80 0044 16 undefined held held held bck bsc gpioic h'ff80 0048 h'1f80 0048 16 h'0000 0000 held held held bck bsc sdmr2 h'ff90 xxxx h'1f90 xxxx 8 bck bsc sdmr3 h'ff94 xxxx h'1f94 xxxx 8 write-only bck dmac sar0 h'ffa0 0000 h'1fa0 0000 32 undefined undefined held held bck dmac dar0 h'ffa0 0004 h'1fa0 0004 32 undefined undefined held held bck dmac dmatcr0 h'ffa0 0008 h'1fa0 0008 32 undefined undefined held held bck dmac chcr0 h'ffa0 000c h'1fa0 000c 32 h'0000 0000 h'0000 0000 held held bck dmac sar1 h'ffa0 0010 h'1fa0 0010 32 undefined undefined held held bck dmac dar1 h'ffa0 0014 h'1fa0 0014 32 undefined undefined held held bck dmac dmatcr1 h'ffa0 0018 h'1fa0 0018 32 undefined undefined held held bck dmac chcr1 h'ffa0 001c h'1fa0 001c 32 h'0000 0000 h'0000 0000 held held bck dmac sar2 h'ffa0 0020 h'1fa0 0020 32 undefined undefined held held bck dmac dar2 h'ffa0 0024 h'1fa0 0024 32 undefined undefined held held bck dmac dmatcr2 h'ffa0 0028 h'1fa0 0028 32 undefined undefined held held bck dmac chcr2 h'ffa0 002c h'1fa0 002c 32 h'0000 0000 h'0000 0000 held held bck dmac sar3 h'ffa0 0030 h'1fa0 0030 32 undefined undefined held held bck dmac dar3 h'ffa0 0034 h'1fa0 0034 32 undefined undefined held held bck
a. address list rev.4.00 oct. 10, 2008 page 1082 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock dmac dmatcr3 h'ffa0 0038 h'1fa0 0038 32 undefined undefined held held bck dmac chcr3 h'ffa0 003c h'1fa0 003c 32 h'0000 0000 h'0000 0000 held held bck dmac dmaor h'ffa0 0040 h'1fa0 0040 32 h'0000 0000 h'0000 0000 held held bck dmac sar4 h'ffa0 0050 h'1fa0 0050 32 undefined undefined held held bck dmac dar4 h'ffa0 0054 h'1fa0 0054 32 undefined undefined held held bck dmac dmatcr4 h'ffa0 0058 h'1fa0 0058 32 undefined undefined held held bck dmac chcr4 h'ffa0 005c h'1fa0 005c 32 h'0000 0000 h'0000 0000 held held bck dmac sar5 h'ffa0 0060 h'1fa0 0060 32 undefined undefined held held bck dmac dar5 h'ffa0 0064 h'1fa0 0064 32 undefined undefined held held bck dmac dmatcr5 h'ffa0 0068 h'1fa0 0068 32 undefined undefined held held bck dmac chcr5 h'ffa0 006c h'1fa0 006c 32 h'0000 0000 h'0000 0000 held held bck dmac sar6 h'ffa0 0070 h'1fa0 0070 32 undefined undefined held held bck dmac dar6 h'ffa0 0074 h'1fa0 0074 32 undefined undefined held held bck dmac dmatcr6 h'ffa0 0078 h'1fa0 0078 32 undefined undefined held held bck dmac chcr6 h'ffa0 007c h'1fa0 007c 32 h'0000 0000 h'0000 0000 held held bck dmac sar7 h'ffa0 0080 h'1fa0 0080 32 undefined undefined held held bck dmac dar7 h'ffa0 0084 h'1fa0 0084 32 undefined undefined held held bck dmac dmatcr7 h'ffa0 0088 h'1fa0 0088 32 undefined undefined held held bck dmac chcr7 h'ffa0 008c h'1fa0 008c 32 h'0000 0000 h'0000 0000 held held bck cpg frqcr h'ffc0 0000 h'1fc0 0000 16 * 2 held held held pck cpg stbcr h'ffc0 0004 h'1fc0 0004 8 h'00 held held held pck cpg wtcnt h'ffc0 0008 h'1fc0 0008 8/16 * 3 h'00 held held held pck cpg wtcsr h'ffc0 000c h'1fc0 000c 8/16 * 3 h'00 held held held pck cpg stbcr2 h'ffc0 0010 h'1fc0 0010 8 h'00 held held held pck rtc r64cnt h'ffc8 0000 h'1fc8 0000 8 held held held held pck rtc rseccnt h'ffc8 0004 h'1fc8 0004 8 held held held held pck rtc rmincnt h'ffc8 0008 h'1fc8 0008 8 held held held held pck rtc rhrcnt h'ffc8 000c h'1fc8 000c 8 held held held held pck rtc rwkcnt h'ffc8 0010 h'1fc8 0010 8 held held held held pck
a. address list rev.4.00 oct. 10, 2008 page 1083 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock rtc rdaycnt h'ffc8 0014 h'1fc8 0014 8 held held held held pck rtc rmoncnt h'ffc8 0018 h'1fc8 0018 8 held held held held pck rtc ryrcnt h'ffc8 001c h'1fc8 001c 16 held held held held pck rtc rsecar h'ffc8 0020 h'1fc8 0020 8 held * 2 held held held pck rtc rminar h'ffc8 0024 h'1fc8 0024 8 held * 2 held held held pck rtc rhrar h'ffc8 0028 h'1fc8 0028 8 held * 2 held held held pck rtc rwkar h'ffc8 002c h'1fc8 002c 8 held * 2 held held held pck rtc rdayar h'ffc8 0030 h'1fc8 0030 8 held * 2 held held held pck rtc rmonar h'ffc8 0034 h'1fc8 0034 8 held * 2 held held held pck rtc rcr1 h'ffc8 0038 h'1fc8 0038 8 h'00 * 2 h'00 * 2 held held pck rtc rcr2 h'ffc8 003c h'1fc8 003c 8 h'09 * 2 h'00 * 2 held held pck rtc rcr3 h'ffc8 0050 h'1fc8 0050 8 h'00 held held held pck rtc ryrar h'ffc8 0054 h'1fc8 0054 16 undefined held held held pck intc icr h'ffd0 0000 h'1fd0 0000 16 h'0000 * 2 h'0000 * 2 held held pck intc ipra h'ffd0 0004 h'1fd0 0004 16 h'0000 h'0000 held held pck intc iprb h'ffd0 0008 h'1fd0 0008 16 h'0000 h'0000 held held pck intc iprc h'ffd0 000c h'1fd0 000c 16 h'0000 h'0000 held held pck intc iprd h'ffd0 0010 h'1fd0 0010 16 h'da74 h'da74 held held pck tmu tocr h'ffd8 0000 h'1fd8 0000 8 h'00 h'00 held held pck tmu tstr h'ffd8 0004 h'1fd8 0004 8 h'00 h'00 held h'00 * 2 pck tmu tcor0 h'ffd8 0008 h'1fd8 0008 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt0 h'ffd8 000c h'1fd8 000c 32 h'ffff ffff h'ffff ffff held held pck tmu tcr0 h'ffd8 0010 h'1fd8 0010 16 h'0000 h'0000 held held pck tmu tcor1 h'ffd8 0014 h'1fd8 0014 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt1 h'ffd8 0018 h'1fd8 0018 32 h'ffff ffff h'ffff ffff held held pck tmu tcr1 h'ffd8 001c h'1fd8 001c 16 h'0000 h'0000 held held pck tmu tcor2 h'ffd8 0020 h'1fd8 0020 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt2 h'ffd8 0024 h'1fd8 0024 32 h'ffff ffff h'ffff ffff held held pck tmu tcr2 h'ffd8 0028 h'1fd8 0028 16 h'0000 h'0000 held held pck
a. address list rev.4.00 oct. 10, 2008 page 1084 of 1122 rej09b0370-0400 module register p4 address area 7 address * 1 size power-on reset manual reset sleep stand- by synchro- nization clock tmu tcpr2 h'ffd8 002c h'1fd8 002c 32 held held held held pck sci scsmr1 h'ffe0 0000 h'1fe0 0000 8 h'00 h'00 held h'00 pck sci scbrr1 h'ffe0 0004 h'1fe0 0004 8 h'ff h'ff held h'ff pck sci scscr1 h'ffe0 0008 h'1fe0 0008 8 h'00 h'00 held h'00 pck sci sctdr1 h'ffe0 000c h'1fe0 000c 8 h'ff h'ff held h'ff pck sci scssr1 h'ffe0 0010 h'1fe0 0010 8 h'84 h'84 held h'84 pck sci scrdr1 h'ffe0 0014 h'1fe0 0014 8 h'00 h'00 held h'00 pck sci scscmr1 h'ffe0 0018 h'1fe0 0018 8 h'00 h'00 held h'00 pck sci scsptr1 h'ffe0 001c h'1fe0 001c 8 h'00 * 2 h'00 * 2 held h'00 * 2 pck scif scsmr2 h'ffe8 0000 h'1fe8 0000 16 h'0000 h'0000 held held pck scif scbrr2 h'ffe8 0004 h'1fe8 0004 8 h'ff h'ff held held pck scif scscr2 h'ffe8 0008 h'1fe8 0008 16 h'0000 h'0000 held held pck scif scftdr2 h'ffe8 000c h'1fe8 000c 8 undefined undefined held held pck scif scfsr2 h'ffe8 0010 h'1fe8 0010 16 h'0060 h'0060 held held pck scif scfrdr2 h'ffe8 0014 h'1fe8 0014 8 undefined undefined held held pck scif scfcr2 h'ffe8 0018 h'1fe8 0018 16 h'0000 h'0000 held held pck scif scfdr2 h'ffe8 001c h'1fe8 001c 16 h'0000 h'0000 held held pck scif scsptr2 h'ffe8 0020 h'1fe8 0020 16 h'0000 * 2 h'0000 * 2 held held pck scif sclsr2 h'ffe8 0024 h'1fe8 0024 16 h'0000 h'0000 held held pck h-udi sdir h'fff0 0000 h'1ff0 0000 16 h'ffff * 2 held held held pck h-udi sddr h'fff0 0008 h'1ff0 0008 32 held held held held pck hi-udi sdint h'fff0 0014 h'1ff0 0014 16 h'0000 held held held pck notes: 1. with control registers, the above addresses in the physical page number field can be accessed by means of a tlb setting. when these addresses are set directly without using the tlb, operations are limited. 2. includes undefined bits. see the de scriptions of the individual modules. 3. use word-size access when writing. perform the write with the upper byte set to h'5a or h'a5, respectively. byte- and longword-size writes cannot be used. use byte-size access when reading.
b. package dimensions rev.4.00 oct. 10, 2008 page 1085 of 1122 rej09b0370-0400 appendix b package dimensions the package dimention that is shown in the renesas semiconductor package data book has priority. 1.40 28 1.3 0.08 0 8 0.4 0.12 0.17 0.22 0.13 0.18 0.23 0.25 0.40 0.50 3.95 30.4 30.6 30.8 3.20 28 0.16 0.15 0.3 0.5 0.7 0.11 30.8 30.6 30.4 1.40 reference symbol dimension in millimeters min nom max l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e * 1 * 2 * 3 129 128 192 193 65 64 1 256 f xm y d e d e p z z b h d h e detail f 1 1 2 c l a l a a 1 p 1 terminal cross section b c c b note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. p-hqfp256-28x28-0.40 5.4g mass[typ.] fp-256g/fp-256gv prqp0256la-b renesas code jeita package code previous code figure b.1 package dimensions (256-pin qfp)
b. package dimensions rev.4.00 oct. 10, 2008 page 1086 of 1122 rej09b0370-0400 y w v u t r p n m l k j h g f e d c b 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 a a b s s y v s y 1 sab s a a prbg0256de-b p-bga256-27x27-1.27 d e s d s e z d z e mass[typ.] 3.0g bp-256a/bp-256av renesas code jeita package code previous code 0.20 0.35 y 1 0.635 0.635 w v 0.30 27.0 2.5 0.7 0.6 0.5 0.90 0.75 0.60 1.27 0.20 27.0 y x b a reference symbol dimension in millimeters min nom max a 1 e e e b m m 0.10 4 e d s s d e figure b.2 package dimensions (256-pin bga)
b. package dimensions rev.4.00 oct. 10, 2008 page 1087 of 1122 rej09b0370-0400 e a 1 max n om m i n d i mens i on i n m illi meters symbo l reference a b x y 17 . 00 0 . 10 0 . 80 0 .4 50 . 50 0 .4 0 0 .4 0 0 . 55 0 . 35 0 .4 00 .4 5 2 . 00 17 . 00 0 . 08 v w 0 . 9 0 . 9 y 1 0 . 20 0 . 20 0 . 15 prev i ous code j eit a package code r ene sas code ? 0 . 9g mass [t yp .] z e z d z d z e s d s e s e s d e d p -f bga292 - 17x17 - 0 . 80 prbg0292ga - a 1 1 a b a s s y s wb s wa v s y 1 23 4 5 6 7 8 9 10 11 12 13 1 4 15 16 17 18 19 20 b c d e f g h j k l m n p r t u v w y a a e e b a s b m 4 e d figure b.3 package dimensions (292-pin bga)
b. package dimensions rev.4.00 oct. 10, 2008 page 1088 of 1122 rej09b0370-0400
c. mode pin settings rev.4.00 oct. 10, 2008 page 1089 of 1122 rej09b0370-0400 appendix c mode pin settings the md10?md0 pin values are input in the event of a power-on reset via the reset pin. clock modes table c.1 clock operating modes (sh7751) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 off on on 6 3/2 3/2 h'0e1a 1 0 1 off on on 6 1 1 h'0e23 2 0 on on on 3 1 1/2 h'0e13 3 0 1 1 off on on 6 2 1 h'0e13 4 1 0 0 on on on 3 3/2 3/4 h'0e0a 5 1 off on on 6 3 3/2 h'0e0a 6 1 0 off off off 1 1/2 1/2 h'0808 notes: 1. the multiplication factor of 1/2 fr equency divider is solely determined by the clock operating mode. 2. for the ranges input clock frequency, s ee the description of the extal clock input frequency (f ex ) and the ckio clock output (f op ) in section 23.3.1, clock and control signal timing.
c. mode pin settings rev.4.00 oct. 10, 2008 page 1090 of 1122 rej09b0370-0400 table c.2 clock operating modes (sh7751r) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 on ( 12) on 12 3 3 h'0e1a 1 0 1 on ( 12) on 12 3/2 3/2 h'0e2c 2 0 on ( 6) on 6 2 1 h'0e13 3 0 1 1 on ( 12) on 12 4 2 h'0e13 4 0 on ( 6) on 6 3 3/2 h'0e0a 5 1 0 1 on ( 12) on 12 6 3 h'0e0a 6 1 0 off ( 6) off 1 1/2 1/2 h'0808 notes: 1. the multiplication factor of pll1 is solely determined by the clock operating mode. 2. for the ranges input clock frequency, s ee the description of the extal clock input frequency (f ex ) and the ckio clock output (f op ) in section 23.3.1, clock and control signal timing. table c.3 area 0 memory map and bus width pin value md6 md4 md3 memory type bus width 0 0 0 reserved (cannot be used) reserved (cannot be used) 1 reserved (cannot be used) reserved (cannot be used) 1 0 reserved (cannot be used) reserved (cannot be used) 1 mpx interface 32 bits 1 0 0 reserved (cannot be used) reserved (cannot be used) 1 sram interface 8 bits 1 0 sram interface 16 bits 1 sram interface 32 bits table c.4 endian pin value md5 endian 0 big endian 1 little endian
c. mode pin settings rev.4.00 oct. 10, 2008 page 1091 of 1122 rej09b0370-0400 table c.5 master/slave pin value md7 master/slave 0 slave 1 master table c.6 clock input pin value md8 clock input 0 external input clock 1 crystal resonator table c.7 pci mode pin value mode md10 md9 mode 0 0 0 pci host with external clock input 1 0 1 pci host with feedback input clock from ckio 2 1 0 pci non-host with external clock input 3 1 1 pci disabled note: when exiting standby mode or hardware standby mode using a power-on reset, do not change the pci mode.
c. mode pin settings rev.4.00 oct. 10, 2008 page 1092 of 1122 rej09b0370-0400
d. pin functions rev.4.00 oct. 10, 2008 page 1093 of 1122 rej09b0370-0400 appendix d pin functions d.1 pin states table d.1 pin states in reset, power- down state, and bus-released state (pci enable, disable common) reset (power-on) reset (manual) pin name i/o master slave master slave standby bus released hard- ware standby notes d0?d31 i/o z z z * 14 z * 14 z * 14 z * 14 z a2?a17, a0?a25 o z z z * 13 o * 7 z * 13 z * 13 o * 5 z * 13 z reset i i i i i i i i back / bsreq o h h h h h o z breq / bsack i pi pi i * 12 i * 12 i * 12 i i bs o h pz h z * 13 z * 13 h * 5 z * 13 z cke o h h o * 4 h l o * 4 z cs6 ? cs0 o h pz h z * 13 z * 13 h * 5 z * 13 z ras o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z rd / cass/frame o h pz o * 4 z z * 13 o * 3 z * 13 o * 3 z rd/ wr o h pz h z * 13 z * 13 h * 5 z * 13 z rdy i pi pi i * 12 i * 12 i * 12 i * 12 i cas3 /dqm3 o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z cas2 /dqm2 o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z cas1 /dqm1 o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z cas0 /dqm0 o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z we3 / ioicwr o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z we2 / ioicrd o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z we1 o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z we0 / reg o h pz o * 4 z * 13 z * 13 o * 3 z * 13 o * 3 z dack1?dack0 o l l l l z * 11 o * 6 o z dmac md7/cts2 i/o i * 17 i * 17 i * 11 i * 11 i * 11 o * 6 i * 11 o z scif md6/ iois16 i i * 17 i * 17 i * 12 i * 12 i * 12 i * 12 i pcmcia (i/o) md5 i i * 17 i * 17 z * 13 z * 13 z * 13 z * 13 z
d. pin functions rev.4.00 oct. 10, 2008 page 1094 of 1122 rej09b0370-0400 reset (power-on) reset (manual) pin name i/o master slave master slave standby bus released hard- ware standby notes md4/ ce2b i/o * 1 i * 17 i * 17 z * 13 h z * 13 z * 13 h * 5 z * 13 z pcmcia md3/ ce2a i/o * 2 i * 17 i * 17 z * 13 h z * 13 z * 13 h * 5 z * 13 z pcmcia ckio o o o zo * 8 zo * 8 zo * 8 zo * 8 z status1?status0 o o o o o o o zo * 9 irl3 ? irl0 i pi pi i * 12 i * 12 i * 12 i * 12 i intc nmi i pi pi i * 12 i * 12 i * 12 i * 12 i intc dreq1?dreq0 i pi pi i * 11 i * 11 i * 11 i * 11 i dmac drak1?drak0 o l l l l z * 11 o * 6 o z dmac md0/sck2 i/o i * 17 i * 17 i * 11 i * 11 i * 11 z * 11 o * 6 i * 11 o i scif rxd i pi pi i * 11 i * 11 i * 11 i * 11 i sci sck i/o pi pi i * 11 i * 11 i * 11 z * 11 o * 6 i * 11 o z sci md1/txd2 i/o i * 17 i * 17 z * 11 z * 11 z * 11 o * 6 z * 11 o z scif md2/rxd2 i i * 17 i * 17 i * 11 i * 11 i * 11 i * 11 i scif txd i/o pi pi z * 11 o z * 11 o z * 11 o * 6 o z sci md8/rts2 i/o i * 17 i * 17 i * 11 i * 11 i * 11 z 11 o * 6 i * 11 o z scif tclk i/o pi pi i * 11 i * 11 i * 11 o i * 11 o z tmu tdo o o o o o o o z h-udi tms i pi pi pi pi pi pi i h-udi tck i pi pi pi pi pi pi i h-udi tdi i pi pi pi pi pi pi i h-udi trst i pi pi pi pi pi pi i h-udi mreset i pi pi pi pi pi pi i sleep i pi pi i * 12 i * 12 i * 12 i * 12 i ca i i i i i i i i
d. pin functions rev.4.00 oct. 10, 2008 page 1095 of 1122 rej09b0370-0400 table d.2 pin states in reset, power-down state, and bus-released state (pci enable) reset (power on) reset (manual) standby reset (software) pin name i/o host non- host host non- host host non- host host non- host hard- ware standby notes ad31?ad31 i/o l z ioz ioz k z l z z cbe3 ? cbe0 i/o l z ioz ioz k z l z z par i/o l z ioz ioz k z l z z serr i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z perr i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z pcilock i/o pz pz iz * 10 iz * 10 z * 10 z * 10 pz pz z pcistop i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z devsel i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z trdy i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z irdy i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z pciframe i/o pz pz ioz * 10 ioz * 10 z * 10 z * 10 pz pz z pcireq4 i/o pi pz z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when using port pcireq2 / md9 i/o i * 17 i * 17 z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when using port pcireq3 / md10 i/o i * 17 i * 17 z * 10 z * 10 (io * 11, * 16 ) i * 10 z * 10 (io * 10, * 16 ) pi pz (io * 10, * 16 ) z values in paren- thesis are when using port pcireq1/ gntin i pi pi i * 10 i * 10 i * 10 i * 10 pi pi z
d. pin functions rev.4.00 oct. 10, 2008 page 1096 of 1122 rej09b0370-0400 reset (power on) reset (manual) standby reset (software) pin name i/o host non- host host non- host host non- host host non- host hard- ware standby notes pcignt4 ? pcignt2 o z z o z (k) k z (k) z z (k) z values in paren- thesis are when using port pcignt1 / reqout o z z o o k k z h z pciclk i i i i i i i i i z pcirst o l l k k k k l l z idsel i pi i pi i pi i pi i z inta o pz pz odk * 10 odk * 10 odk * 10 odk * 10 pz pz z
d. pin functions rev.4.00 oct. 10, 2008 page 1097 of 1122 rej09b0370-0400 table d.3 pin states in reset, power-down st ate, and bus-released state (pci disable) reset (power-on) reset (manual) pin name i/o master slave master slave standby bus released hard- ware standby notes ad31?ad0 i/o z z z (k) z (k) z * 15 (k) z * 15 (k) z values in paren- thesis are when using port cbe3 ? cbe0 ? z z z z z z z par o z z z z z z z serr ? z z z z z z z perr ? z z z z z z z pcilock ? z z z z z z z pcistop ? z z z z z z z devsel ? z z z z z z z trdy ? z z z z z z z irdy ? z z z z z z z pciframe ? z z z z z z z pcireq4 ? z z z z z z z pcireq2 /md9 i/o i * 17 i * 17 z z z z z pcireq3 /md10 i/o i * 17 i * 17 z z z z z pcireq1 ? z z z z z z z pcignt4 ? pcignt2 o z z z z z z z pcignt1 o z z z z z z z pciclk ? z z z z z z z pcirst o z z z z z z z idsel ? z z z z z z z inta ? z z z z z z z legend: i: input o: output h: high-level output l: low-level output z: high-impedance
d. pin functions rev.4.00 oct. 10, 2008 page 1098 of 1122 rej09b0370-0400 k: output state held iz/ioz: response to access from pci pz: pulled up with a built-in pull-up resistance pi: input pulled up with a built-in pull-up resistance odk: open-drain output state held notes: 1. output when area 5 pcmcia is used. 2. output when area 6 pcmcia is used. 3. z (i) or o (refresh), depending on register setting (bcr1.hizcnt). 4. depends on refresh operation. 5. z (i) or h (state held), dependi ng on register setting (bcr1.hizmem). 6. z or o, depending on register setting (stbcr.phz). 7. output when refreshing is set. 8. z or o, depending on register setting (frqcr.ckoen). 9. z or o, depending on register setting (stbcr.sthz). 10. pullup, depending on register setting (pcicr.pcipup). 11. pullup, depending on register setting (stbcr.ppu). 12. pullup, depending on register setting (bcr1.ipup). 13. pullup, depending on register setting (bcr1.opup). 14 pullup, depending on register setting (bcr1.dpup). 15. pullup, depending on regi ster setting (bcr2.porten). 16. pullup, depending on register setti ng (pcipctr.pb2pup to pcipctr.pb4pup). 17. pullup by on-chip pullup resistor. note t hat this cannot be used for pullup of the mode pin during a power-on reset. pullup or pulldown should be performed externally to this lsi. d.2 handling of unused pins ? when rtc is not used ? extal2: pull up to 3.3 v ? xtal2: leave unconnected ? vdd-rtc: power supply ? vss-rtc: power supply ? when pll1 is not used ? vdd-pll1: power supply ? vss-pll1: power supply
d. pin functions rev.4.00 oct. 10, 2008 page 1099 of 1122 rej09b0370-0400 ? when pll2 is not used ? vdd-pll2: power supply ? vss-pll2: power supply ? when on-chip crystal oscillator is not used ? xtal: leave unconnected ? vdd-cpg: power supply ? vss-cpg: power supply table d.4 handling of pins when pci is not used pin name i/o handling ad31?ad31 i/o pull up to 3.3 v * cbe3 ? cbe0 i/o pull up to 3.3 v par i/o pull up to 3.3 v serr i/o pull up to 3.3 v perr i/o pull up to 3.3 v pcilock i/o pull up to 3.3 v pcistop i/o pull up to 3.3 v devsel i/o pull up to 3.3 v trdy i/o pull up to 3.3 v irdy i/o pull up to 3.3 v pciframe i/o pull up to 3.3 v pcireq4 ? pcireq2 i/o pull up to 3.3 v pcireq1 i pull up to 3.3 v pcignt4 ? pcignt2 o pull up to 3.3 v pcignt1 o pull up to 3.3 v pciclk i pull up to 3.3 v pcirst o leave unconnected idsel i pull down to low level when idsel is not in use inta o leave unconnected note: * when not used as a general-purpose i/o port. d.3 note on pin processing to prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins.
d. pin functions rev.4.00 oct. 10, 2008 page 1100 of 1122 rej09b0370-0400
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1101 of 1122 rej09b0370-0400 appendix e synchronous dram address multiplexing tables (1) bus 32 (16m: 512k 16b 2) 2 * amx 0 amxext 0 16m, column-addr-8bit 4mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a21 a21 a11 bank selects bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1102 of 1122 rej09b0370-0400 (2) bus 32 (16m: 512k 16b 2) 2 * amx 0 amxext 1 16m, column-addr-8bit 4mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a20 a20 a11 bank selects bank address a12 a21 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1103 of 1122 rej09b0370-0400 (3) bus 32 (16m: 1m 8b 2) 4 * amx 1 amxext 0 16m, column-addr-9bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a22 a22 a11 bank selects bank address a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1104 of 1122 rej09b0370-0400 (4) bus 32 (16m: 1m 8b 2) 4 * amx 1 amxext 1 16m, column-addr-9bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a21 a21 a11 bank selects bank address a12 a22 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1105 of 1122 rej09b0370-0400 (5) bus 32 (64m: 1m 16b 4) 2 * amx 2 64m, column-addr-8bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a15 a23 a23 a13 a14 a22 a22 a12 bank selects bank address a13 a21 0 a11 a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1106 of 1122 rej09b0370-0400 (6) bus 32 (64m: 2m 8b 4) 4 * amx 3 64m, column-addr-9bit 32mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a15 a24 a24 a13 a14 a23 a23 a12 bank selects bank address a13 a22 0 a11 a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1107 of 1122 rej09b0370-0400 (7) bus 32 (64m: 512k 32b 4) 1 * amx 4 64m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a14 a22 a22 a12 a13 a21 a21 a11 bank selects bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1108 of 1122 rej09b0370-0400 (8) bus 32 (64m: 1m 32b 2) 1 * amx 5 64m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a14 a22 a22 a12 bank selects bank address a13 a21 0 a11 a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1109 of 1122 rej09b0370-0400 (9) bus 32 (64m: 4m 4b 4) 8 * (128m: 4m 8b 4) 4 * amx 6 64m, column-addr-10bit 64mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a25 a25 a13 a14 a24 a24 a12 bank selects bank address a13 a23 0 a11 a12 a22 h/l a10 address precharge setting a11 a21 a11 a9 a10 a20 a10 a8 a9 a19 a9 a7 a8 a18 a8 a6 a7 a17 a7 a5 a6 a16 a6 a4 a5 a15 a5 a3 a4 a14 a4 a2 a3 a13 a3 a1 a2 a12 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1110 of 1122 rej09b0370-0400 (10) bus 32 (256m: 4m 16b 4) 2 * amx 6 amxext1 256m, column-addr-9bit 64mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a25 a25 a14 a15 a24 a24 a13 bank selects bank address a14 a23 0 a12 a13 a22 0 a11 a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1111 of 1122 rej09b0370-0400 (11) bus 32 (16m: 256k 32b 2) 1 * amx 7 16m, column-addr-8bit 2mb lsi address pins ras cycle cas cycle synchronous dram address pins function a13 a12 a20 a20 a10 bank selects bank address a11 a19 h/l a9 address precharge setting a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used note: * example configurations of synchronous dram
e. synchronous dram address multiplexing tables rev.4.00 oct. 10, 2008 page 1112 of 1122 rej09b0370-0400
f. instruction prefetching and its side effects rev.4.00 oct. 10, 2008 page 1113 of 1122 rej09b0370-0400 appendix f instruction pref etching and its side effects the sh7751 group is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. therefore, program co de must not be located in the last 20-byte area of any memory space. if program code is located in these areas, the memory area will be exceeded and a bus access for instruc tion pre-reading may be initiated. a ca se in which this is a problem is shown below. address h'03fffff8 h'03fffffa h'03fffffc h'03fffffe h'04000000 h'04000002 area 0 area 1 add r1,r4 jmp @r2 nop nop . . . . . pc (pro g ram counter) instruction prefetch address figure f.1 instruction prefetch figure f.1 presupposes a case in which the instruction (add) indicated by the program counter (pc) and the address h'04000002 instruction pref etch are executed simult aneously. it is also assumed that the program branches to an area ot her than area 1 after executing the following jmp instruction and delay slot instruction. in this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1 may be initiated. instruction prefetch side effects 1. it is possible that an exte rnal bus access caused by an inst ruction prefetch may result in misoperation of an external device, such as a fifo, connected to the area concerned. 2. if there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. remedies 1. these illegal instruction fetches can be avoided by using the mmu. 2. the problem can be avoided by not locating program code in the last 20 bytes of any area.
f. instruction prefetching and its side effects rev.4.00 oct. 10, 2008 page 1114 of 1122 rej09b0370-0400
g. power-on and power-off procedures rev.4.00 oct. 10, 2008 page 1115 of 1122 rej09b0370-0400 appendix g power-on and power-off procedures g.1 power-on stipulations 1. supply power to power supply v ddq and to i/o, rtc, cpg, pll1, and pll2 simultaneously. 2. perform input to the signal lines ( reset , mreset , md0 to md10, external clock, etc.) after or at the same time power is supplied to v ddq . applying input to signal lines before power is supplied to v ddq could damage the product. ? drive the reset signal low when power is first supplied to v ddq . 3. apply power such that the voltage of power supply v dd is less than 1.2 v until the voltage of power supply v ddq reaches 2 v. note that the on-chi p pll circuit (pll2) may not operate correctly if this condition is not met. 4. it is recommended to apply power first to power supply v ddq and then to power supply v dd . 5. in addition to 1., 2., 3., and 4. above, also observe the stipulations in g.3. furthermore: ? there are no time restrictions on the power-on sequence for power supply v ddq and power supply v dd with regard to the lsi alone. refer to figure g.1. nevertheless, it is recommended that the power-on sequence be completed in as short a time as possible. ? when the lsi is mounted on a board and connect ed to other elements, ensure that ?0.3 v < vin < v ddq + 0.3 v. in addition, the time limit for the rise of either power supply v ddq or power supply v dd from v ddq 1.0 v or v dd 0.5 v, respectively, to above the minimum values in the lsi?s guaranteed operation voltage range (v ddq (min.) and v dd (min.)) is 100 ms (max.), as shown in figure g.2. the product may be damaged if this time limit is exceeded. it is recommended that the power-on se quence be completed in as short a time as possible. g.2 power-off stipulations 1. power off power supply v ddq and i/o, rtc, cpg, pll1, and pll2 simultaneously. 2. there are no timing restrictions for the reset and mreset signal lines at power-off. 3. cut off the input signal level for signal lines other than reset and mreset in the same sequence as power supply v ddq . 4. it is recommended to first power off power supply v dd and then power supply v ddq . 5. in addition to 1., 2., 3., and 4. above, also observe the stipulations in g.3. furthermore: ? there are no time restrictions on the power-off sequence for power supply v ddq and power supply v dd with regard to the lsi alone. refer to figure g.2. nevertheless, it is recommended that the power-off sequence be co mpleted in as short a time as possible.
g. power-on and power-off procedures rev.4.00 oct. 10, 2008 page 1116 of 1122 rej09b0370-0400 ? when the lsi is mounted on a board and connect ed to other elements, ensure that ?0.3 v < vin < v ddq + 0.3 v. in addition, the time limit for the fall of power supply v ddq and power supply v dd from the minimum values in the lsi?s guaranteed operation voltage range (v ddq (min.) and v dd (min.)) to v ddq 1.0 v or v dd 0.5 v, respectively, is 150 ms (max.), as shown in figure g.3. the product may be damaged if this time limit is exceeded. it is recommended that the power-off sequence be co mpleted in as short a time as possible. notes: 1. note on power-on if the below conditions (a) are not met during power-on, pll2 may not oscillate correctly and ckio may not be output properly. conditions (a): v ddq (v ddq , v dd-cpg , v dd-rtc ) is 2.0 v or above when v dd ( v dd , v dd-pll1 , v dd-pll2 ) is 1.2 v or above. 2. workarounds any of methods (1) to (3) below may be used to avoid the problem by stopping pll2 oscillation temporarily. (1) as shown in figure g.1, select mode 6* 1 immediately after po wer-on, select the desired clock mode once the above condi tions (a) are satisfied, and cancel the power-on reset. (2) after starting with clock operation mode 6* 1 selected, change frqcr to specify the desired frequency clock. note: it is not possible to use frequency divider 1 when this method is employed. (3) temporarily stop pll2 by writing 0 to frqcr.pll2en. after maintaining frqcr.pll2en as 0 for 1 s or more, write 1 to frqcr.pll2en to restart pll2. note: if this method is used, the clock output from ckio cannot be guaranteed until the above operations are completed. if abnormal signal output is produced, the frequency is higher than normal. therefore, it is possible that unwanted noise may be generated from the clock line or, if the lsi?s ckio pin is used to supply a clock to another device, the clock may not be supplied correctly to the external device. when using this method, it is recommended that sufficient verification testing be performed on the actual system.
g. power-on and power-off procedures rev.4.00 oct. 10, 2008 page 1117 of 1122 rej09b0370-0400 2.0 v reset md2 ? 0 v ddq v dd 1.2 v 3.3 v * 1 * 2 min. 0s period when conditions (a) not satisfied mode 6 figure g.1 method for temporarily selecting clock operation mode 6 notes: 1. clock operation mode 6 (i) sh7751 (1) external pin combination: md0 = low, md1 = high, md2 = high (2) frequency dividers 1 and 2 = off, pll1 = off, pll2 = off (3) frequencies (relative to input clock): cpu clock = 1 bus clock = 1/2 peripheral module clock = 1/2 (4) input clock frequency range = 1 to 66.7 mhz (ii) sh7751r (1) external pin combination: md0 = low, md1 = high, md2 = high (2) pll1 = off (6), pll2 = off (3) frequencies (relative to input clock): cpu clock = 1 bus clock = 1/2 peripheral module clock = 1/2 (4) input clock frequency range = 1 to 34 mhz 2. input to the md should be high-level and follow the voltage level of the i/o, pll, rtc, and cpg power supplies.
g. power-on and power-off procedures rev.4.00 oct. 10, 2008 page 1118 of 1122 rej09b0370-0400 g.3 common stipulations for power-on and power-off 1. always ensure that v ddq = v dd-cpg = v dd-rtc = v dd-pll1/2 . refer to 9.9.5, hardware standby mode timing, regarding v dd-rtc in hardware standby mode. 2. ensure that ?0.3 v < v dd < v ddq + 0.3 v. 3. ensure that v ss = v ssq = v ss-pll1/2 = v ss-cpg = v ss-rtc = gnd (0 v). the product may be damaged if conditions 1., 2., and 3. above are not satisfied. power supply v ddq power supply v dd 0.3 v (max) 0.3 v (max) gnd [v] [ t ] power-on power-off figure g.2 power-on procedure 1 v dd (min) v ddq (min) gnd 0.5 v 1.2 v 1.0 v 2.0 v t pwu t pwu < 100 ms (max) t pwd < 150 ms (max) t pwd [v] [ t ] power supply v ddq power supply v dd power-on power-off unstable period at power-on: t pwu normal operation period unstable period at power-off: t pwd figure g.3 power-on procedure 2
h. product lineup rev.4.00 oct. 10, 2008 page 1119 of 1122 rej09b0370-0400 appendix h product lineup table h.1 sh7751/sh7751r product lineup product name voltage operating frequency operating temperature * 1 part number * 2 package sh7751 1.8 v 167 mhz hd6417751bp167 (v) 256-pin bga ?20 to 75c hd6417751f167 (v) 256-pin qfp hd6417751rbp240 (v) 256-pin bga hd6417751rf240 (v) 256-pin qfp 240 mhz ?20 to 75c hd6417751rbg240 (v) 292-pin bga hd6417751rbp200 (v) 256-pin bga sh7751r 1.5 v 200 mhz hd6417751rf200 (v) 256-pin qfp hd6417751rbg200 (v) 292-pin bga notes: 1. contact a renesas sales office regar ding product versions with specifications for a wider temperature range ( ? 40 to +85 c). 2. all listed products are available in le ad-free versions. lead-free products have a ?v? appended at the end of the part number.
h. product lineup rev.4.00 oct. 10, 2008 page 1120 of 1122 rej09b0370-0400
i. version registers rev.4.00 oct. 10, 2008 page 1121 of 1122 rej09b0370-0400 appendix i version registers the configuration of the registers related to the product version is shown below. table i.1 register configuration name abbreviation read/write initial value p4 address area 7 address access size processor version register pvr r * h'ff000030 h'1f000030 32 product register prr r * h'ff000044 h'1f000044 32 note: * refer to table below. pvr and prr initial values product name pvr prr sh7751 h'041100xx h'xxxxxxxx sh7751r h'040500xx h'0000011x legend: x: undefined 1. processor version register (pvr ) initial value example for sh7751r bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 version information initial value: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version information ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? r/w: r r r r r r r r ? ? ? ? ? ? ? ?
i. version registers rev.4.00 oct. 10, 2008 page 1122 of 1122 rej09b0370-0400 2. product register (prr) initial value example for sh7751r bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 version information initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version information ? ? ? ? initial value: 0 0 0 0 0 0 0 1 0 0 0 1 ? ? ? ? r/w: r r r r r r r r r r r r ? ? ? ?
renesas 32-bit risc microcomputer hardware manual sh7751 group, sh7751r group publication date: 1st edition, april 2000 rev.4.00, october 10, 2008 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2008. renesas technology corp., all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2

sh7751 group, sh7751r group rej09b0370-0400 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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